LTC2328-16_技术文档

LTC2328-16

16-Bit, 1Msps, 1ꢀ0.24

True Bipolar, Pseudo-Differential

Input ADC with 9305dB SNR

FeaTures

DescripTion

The LTC^®2328-16 is a low noise, high speed 16-bit suc-

cessive approximation register (SAR) ADC with pseudo-

differential inputs. Operating from a single 5V supply, the

LTC2328-16hasa 10.24Vtruebipolarinputrange,making

n

1Msps Throughput Rate

n

1ꢀ.5LS ꢁI5 ꢂMaꢃx

n

Guaranteed 16-Sit Io Missing Codes

Pseudo-Differential ꢁnputs

n

True Sipolar ꢁnput Ranges 6ꢀꢄ.ꢅV 1ꢆꢀꢄ2ꢅV 1ꢄꢀ.ꢅ

it ideal for high voltage applications which require a wide

dynamic range. The LTC2328-16 achieves 1.5LSꢀ INL

maximum, no missing codes at 16 bits with 93.5dꢀ SNR.

n

93ꢀ.dS LIR ꢂTypx at f = ꢄkHz

ꢁI

–111dS THD ꢂTypx at f = ꢄkHz

Guaranteed Operation to 125°C

The LTC2328-16 has an onboard single-shot capable

reference buffer and low drift (20ppm/°C max) 2.048V

temperature compensated reference. The LTC2328-16

also has a high speed SPI-compatible serial interface that

supports 1.8V, 2.5V, 3.3V and 5V logic while also featur-

ing a daisy-chain mode. The fast 1Msps throughput with

no cycle latency makes the LTC2328-16 ideally suited

for a wide variety of high speed applications. An internal

oscillator sets the conversion time, easing external timing

considerations. The LTC2328-16 dissipates only 50mW

and automatically naps between conversions, leading to

reduced power dissipation that scales with the sampling

rate. A sleep mode is also provided to reduce the power

consumption of the LTC2328-16 to 300μW for further

power savings during inactive periods.

Single 5V Supply

Low Drift (20ppm/°C Max) 2.048V Internal Reference

Onboard Single-Shot Capable Reference ꢀuffer

No Pipeline Delay, No Cycle Latency

1.8V to 5V I/O Voltages

SPI-Compatible Serial I/O with Daisy-Chain Mode

Internal Conversion Clock

Power Dissipation 50mW (Typ)

16-Lead MSOP Package

applicaTions

n

Programmable Logic Controllers

n

Industrial Process Control

n

High Speed Data Acquisition

n

Portable or Compact Instrumentation

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 7705765, 7961132.

n

ATE

Typical applicaTion

3ꢄk Point FFT f_L= 1MspsV

f_ꢁI= ꢄkHz

0

5V

1.8V TO 5V

SNR = 93.5dB

–20

–40

THD = –111dB

SINAD = 93.4dB

SFDR = –115dB

10µF

2.2µF

0.1µF

+10.24V

–60

+

V

OV

DD

DDLBYP DD

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

–10.24V

–80

+

–

LT^®1468

IN

–100

–120

–140

–160

–180

LTC2328-16

–

IN

SAMPLE CLOCK

REF

REFBUF

REFIN

GND

232816 TA01a

100nF

47µF

0

100

200

300

400

500

FREQUENCY (kHz)

232816 TA01b

232816fb

1

For more information www.linear.com/LTC2328-16

LTC2328-16

absoluTe MaxiMuM raTings

pin conFiguraTion

ꢂIotes 1V ꢄx

Supply Voltage (V )..................................................6V

DD

TOP VIEW

Supply Voltage (OV )................................................6V

DD

V

1

2

16 GND

DDLBYP

Supply ꢀypass Voltage (V

Analog Input Voltage

) ...........................3.2V

DDLꢀYP

V

15 OV

DD

GND 3

14 SDO

13 SCK

+

–

IN

4

5

+

–

12 RDL/SDI

11 BUSY

10 CHAIN

IN , IN ..............................................–16.5V to 16.5V

REFꢀUF...................................................................6V

REFIN ..................................................................2.8V

Digital Input Voltage

GND 6

REFBUF 7

REFIN 8

9

CNV

MS PACKAGE

16-LEAD PLASTIC MSOP

T

JMAX

= 150°C, θ = 110°C/W

JA

(Note 3)........................... (GND –0.3V) to (OV + 0.3V)

DD

Digital Output Voltage

(Note 3)........................... (GND –0.3V) to (OV + 0.3V)

DD

Power Dissipation.............................................. 500mW

Operating Temperature Range

LTC2328C................................................ 0°C to 70°C

LTC2328I .............................................–40°C to 85°C

LTC2328H.......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

http://wwwꢀlinearꢀcom/product/5TCꢄ3ꢄ8-16#orderinfo

orDer inForMaTion

5EAD FREE FꢁIꢁLH

TAPE AID REE5

PART MARKꢁIG*

PACKAGE DELCRꢁPTꢁOI

16-Lead Plastic MSOP

TEMPERATURE RAIGE

0°C to 70°C

LTC2328CMS-16#PꢀF

LTC2328IMS-16#PꢀF

LTC2328HMS-16#PꢀF

LTC2328CMS-16#TRPꢀF 232816

LTC2328IMS-16#TRPꢀF 232816

LTC2328HMS-16#TRPꢀF 232816

–40°C to 85°C

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPꢀF suffix.

232816fb

2

For more information www.linear.com/LTC2328-16

LTC2328-16

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature rangeV otherwise specifications are at T_A= ꢄ.°Cꢀ ꢂIote 2x

LYMSO5

PARAMETER

COIDꢁTꢁOIL

MꢁI

TYP

MAX

UIꢁTL

V

+

l

V

IN

V

IN

V

IN

Absolute Input Range (IN )

(Note 5)

–2.5 • V

– 0.5

2.5 • V

+ 0.5

REFꢀUF

–

+

–

Absolute Input Range (IN )

(Note 5)

–0.5

0.5

V

–

+

–

– V

Input Differential Voltage Range

Analog Input Current

V

= V – V

–2.5 • V

2.5 • V

REFꢀUF

V

IN

REFꢀUF

I

–7.8

4.8

mA

pF

IN

C

Analog Input Capacitance

Analog Input Resistance

5

IN

R

2.083

66

kΩ

dꢀ

IN

CMRR

Input Common Mode Rejection Ratio

f

= 500kHz

IN

converTer characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature rangeV otherwise specifications are at T_A= ꢄ.°Cꢀ ꢂIote 2x

LYMSO5

PARAMETER

COIDꢁTꢁOIL

MꢁI

16

TYP

MAX

UIꢁTL

ꢀits

l

Resolution

No Missing Codes

16

ꢀits

Transition Noise

0.5

0.25

0.1

0

LSꢀ

RMS

l

INL

Integral Linearity Error

Differential Linearity Error

ꢀipolar Zero-Scale Error

ꢀipolar Zero-Scale Error Drift

ꢀipolar Full-Scale Error

(Note 6)

(Note 7)

–1.5

–1

1.5

1

LSꢀ

DNL

ꢀZE

LSꢀ

–10

10

0.01

LSꢀ/°C

LSꢀ

l

FSE

V

= 4.096V (REFꢀUF Overdriven)

–35

–45

–35

45

REFꢀUF

(Notes 7, 9)

REFIN = 2.048V (Note 7)

LSꢀ

ꢀipolar Full-Scale Error Drift

0.5

ppm/°C

The l denotes the specifications which apply over the full operating temperature rangeV

DynaMic accuracy

otherwise specifications are at T_A= ꢄ.°C and A_ꢁI= –1dSFLꢀ ꢂIotes 2V 8x

LYMSO5 PARAMETER COIDꢁTꢁOIL

6.25V Range, f = 2kHz, REFIN = 1.25V

MꢁI

87.1

90.2

90.5

87.5

91

TYP

90.4

93.4

94.2

90.5

93.5

94.5

–108

–111

–106

110

113

108

7

MAX

UIꢁTL

dꢀ

l

SINAD

Signal-to-(Noise + Distortion) Ratio

IN

10.24V Range, f = 2kHz, REFIN = 2.048V

dꢀ

IN

12.5V Range, f = 2kHz, REFꢀUF = 5V

dꢀ

IN

SNR

Signal-to-Noise Ratio

6.25V Range, f = 2kHz, REFIN = 1.25V

dꢀ

IN

10.24V Range, f = 2kHz, REFIN = 2.048V

dꢀ

IN

12.5V Range, f = 2kHz, REFꢀUF = 5V

92

dꢀ

IN

THD

Total Harmonic Distortion

Spurious Free Dynamic Range

6.25V Range, f = 2kHz, REFIN = 1.25V

–98

–96

dꢀ

IN

10.24V Range, f = 2kHz, REFIN = 2.048V

dꢀ

IN

12.5V Range, f = 2kHz, REFꢀUF = 5V

dꢀ

IN

SFDR

6.25V Range, f = 2kHz, REFIN = 1.25V

98

96

dꢀ

IN

10.24V Range, f = 2kHz, REFIN = 2.048V

dꢀ

IN

12.5V Range, f = 2kHz, REFꢀUF = 5V

dꢀ

IN

–3dꢀ Input Linear ꢀandwidth

Aperture Delay

MHz

ps

500

4

Aperture Jitter

ps

RMS

Transient Response

Full-Scale Step

0.5

µs

232816fb

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For more information www.linear.com/LTC2328-16

LTC2328-16

inTernal reFerence characTerisTics ^Thel denotes the specifications which apply over the

full operating temperature rangeV otherwise specifications are at T_A= ꢄ.°Cꢀ ꢂIote 2x

LYMSO5

PARAMETER

COIDꢁTꢁOIL

MꢁI

TYP

2.048

2

MAX

2.053

20

UIꢁTL

V

Internal Reference Output Voltage

2.043

REFIN

l

V

REFIN

Temperature Coefficient

(Note 14)

ppm/°C

kΩ

REFIN Output Impedance

Line Regulation

15

V

REFIN

V

= 4.75V to 5.25V

DD

0.08

mV/V

V

REFIN Input Voltage Range

(REFIN Overdriven) (Note 5)

1.25

2.4

reFerence buFFer characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature rangeV otherwise specifications are at T_A= ꢄ.°Cꢀ ꢂIote 2x

LYMSO5 PARAMETER

COIDꢁTꢁOIL

= 2.048V

MꢁI

4.091

2.5

TYP

MAX

4.101

5

UIꢁTL

l

V

Reference ꢀuffer Output Voltage

REFꢀUF Input Voltage Range

REFꢀUF Output Impedance

REFꢀUF Load Current

V

4.096

V

REFꢀUF

REFIN

(REFꢀUF Overdriven) (Notes 5, 9)

V

= 0V

13

kΩ

REFIN

l

I

V

= 5V (REFꢀUF Overdriven) (Notes 9, 10)

= 5V, Nap Mode (REFꢀUF Overdriven) (Note 9)

0.89

0.39

1.2

mA

REFꢀUF

DigiTal inpuTs anD DigiTal ouTpuTs ^Thel denotes the specifications which apply over the

full operating temperature rangeV otherwise specifications are at T_A= ꢄ.°Cꢀ ꢂIote 2x

LYMSO5

PARAMETER

COIDꢁTꢁOIL

MꢁI

TYP

MAX

UIꢁTL

V

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

0.8 • OV

IH

IL

DD

0.2 • OV

V

DD

I

V

IN

= 0V to OV

DD

–10

10

μA

pF

IN

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

IN

l

I = –500µA

O

OV – 0.2

DD

V

OH

OL

I = 500µA

O

0.2

10

V

I

V

OUT

V

OUT

V

OUT

= 0V to OV

DD

–10

µA

mA

OZ

= 0V

= OV

–10

10

SOURCE

SINK

DD

power requireMenTs ^Thel denotes the specifications which apply over the full operating temperature

rangeV otherwise specifications are at T_A= ꢄ.°Cꢀ ꢂIote 2x

LYMSO5

PARAMETER

COIDꢁTꢁOIL

MꢁI

4.75

1.71

TYP

MAX

5.25

16

UIꢁTL

l

V

Supply Voltage

Supply Current

5

V

DD

OV

DD

+

–

I

1Msps Sample Rate (IN = –10.24V, IN = 0V)

14.5

10

0.4

8.4

60

mA

μA

VDD

–

1Msps Sample Rate (IN = IN = 0V)

1Msps Sample Rate (C = 20pF)

I

Supply Current

Nap Mode Current

Sleep Mode Current

OVDD

NAP

SLEEP

L

+ I

OVDD

+

–

l

Conversion Done (I

Sleep Mode (I

, IN = –10.24V, IN = 0V)

OVDD

10

225

VDD

+ I

)

VDD

–

l

P

Power Dissipation

1Msps Sample Rate (IN = –10.24V, IN = 0V)

72.5

50

42

0.3

80

mW

D

–

1Msps Sample Rate (IN = IN = 0V)

+

–

l

Nap Mode

Sleep Mode

Conversion Done (I

+ I

OVDD

, IN = –10.24V, IN = 0V)

50

1.1

VDD

+ I

OVDD

Sleep Mode (I

)

VDD

232816fb

4

For more information www.linear.com/LTC2328-16

LTC2328-16

aDc TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature rangeV otherwise specifications are at T_A= ꢄ.°Cꢀ ꢂIote 2x

LYMSO5

PARAMETER

COIDꢁTꢁOIL

MꢁI

TYP

MAX

1

UIꢁTL

Msps

ns

l

f

t

Maximum Sampling Frequency

Conversion Time

SMPL

CONV

ACQ

460

1

527

Acquisition Time

t

= t

CYC

– t

– t (Note 11)

ꢀUSYLH

ns

ACQ

CONV

Time ꢀetween Conversions

CNV High Time

µs

CYC

20

ns

CNVH

ꢀUSYLH

CNVL

CNV↑ to ꢀUSY Delay

Minimum Low Time for CNV

SCK Quiet Time from CNV↑

SCK Period

C = 20pF

L

13

ns

(Note 12)

(Note 11)

20

10

4

ns

QUIET

SCK

(Notes 12, 13)

ns

SCK High Time

ns

SCKH

SCKL

SCK Low Time

4

ns

SDI Setup Time From SCK↑

SDI Hold Time From SCK↑

SCK Period in Chain Mode

SDO Data Valid Delay from SCK↑

(Note 12)

4

ns

SSDISCK

HSDISCK

SCKCH

DSDO

1

ns

t

= t

+ t (Note 12)

DSDO

13.5

ns

SCKCH

SSDISCK

l

C = 20pF, OV = 5.25V

7.5

8

9.5

ns

L

DD

C = 20pF, OV = 2.5V

L

C = 20pF, OV = 1.71V

L

l

t

SDO Data Remains Valid Delay from SCK↑

SDO Data Valid Delay from ꢀUSY↓

ꢀus Enable Time After RDL↓

C = 20pF (Note 11)

1

ns

HSDO

DSDOꢀUSYL

EN

L

C = 20pF (Note 11)

L

5

(Note 12)

16

13

ns

ꢀus Relinquish Time After RDL↑

REFꢀUF Wake-Up Time

ns

DIS

C

= 47μF, C = 100nF

REFIN

200

ms

WAKE

REFꢀUF

Iote 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Iote 7: ꢀipolar zero error is the offset voltage measured from –0.5LSꢀ

when the output code flickers between 0000 0000 0000 0000 and 1111

1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS

untrimmed deviation from ideal first and last code transitions and includes

the effect of offset error.

Iote ꢄ: All voltage values are with respect to ground.

Iote 8: All specifications in dꢀ are referred to a full-scale 10.24V input

with REFIN = 2.048V.

Iote 3: When these pin voltages are taken below ground or above V or

OV , they will be clamped by internal diodes. This product can handle

DD

input currents up to 100mA below ground or above V or OV without

latch-up.

Iote 9: When REFꢀUF is overdriven, the internal reference buffer must be

turned off by setting REFIN = 0V.

DD

Iote 2: V = 5V, OV = 2.5V, 10.24V Range, REFIN = 2.048V,

Iote 1ꢆ: f

= 1MHz, I

varies proportionally with sample rate.

DD

SMPL

REFꢀUF

f

= 1MHz.

SMPL

Iote 11: Guaranteed by design, not subject to test.

Iote 1ꢄ: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V

Iote .: Recommended operating conditions.

DD

Iote 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

and OV = 5.25V.

DD

Iote 13: t

of 10ns maximum allows a shift clock frequency up to

SCK

100MHz for rising edge capture.

Iote 12: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

0.8 • OV

DD

t

WIDTH

0.2 • OV

DD

50%

t

DELAY

232816 F01

0.8 • OV

0.2 • OV

DD

0.2 • OV

Figure 1ꢀ ꢅoltage 5evels for Timing Lpecifications

232816fb

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For more information www.linear.com/LTC2328-16

LTC2328-16

T_A= ꢄ.°CV ꢅ_DD= .ꢅV Oꢅ_DD= ꢄꢀ.ꢅV REFꢁI = ꢄꢀꢆ28ꢅV

DC Histogram

Typical perForMance characTerisTics

f_LMP5= 1MspsV unless otherwise notedꢀ

ꢁntegral Ionlinearity

vs Output Code

Differential Ionlinearity

vs Output Code

9000

1.0

0.8

0.5

0.4

σ = 0.5

8000

0.6

0.3

7000

6000

5000

4000

3000

2000

1000

0

0.4

0.2

0.1

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–0.2

–0.3

–0.4

–0.5

–32768

–16384

0

16384

32768

–32768

–16384

0

16384

32768

–1

0

1

2

OUTPUT CODE

232816 G03

CODE

232816 G01

232616 G02

3ꢄk Point FFT f_L= 1MspsV

f_ꢁI= ꢄkHz

THDV Harmonics vs ꢁnput

Frequency

LIRV LꢁIAD vs ꢁnput Frequency

0

–20

100

90

–70

–80

SNR = 93.5dB

THD = –111dB

SINAD = 93.4dB

SFDR = –115dB

SNR

–40

–90

–60

SINAD

–100

–110

–80

80

–100

–120

–140

–160

–180

–120

–130

–140

–150

70

THD

2ND

3RD

60

0

25 50 75 100 125 150 175 200

FREQUENCY (kHz)

0

100

200

300

400

500

0

25 50 75 100 125 150 175 200

FREQUENCY (kHz)

232816 G06

232816 G04

232816 G05

LIRV LꢁIAD vs ꢁnput 5evelV

f_ꢁI= ꢄkHz

LIRV LꢁIAD vs TemperatureV

f_ꢁI= ꢄkHz

THDV Harmonics vs TemperatureV

f_ꢁI= ꢄkHz

–105

–110

–115

–120

–125

96

95

94

93

92

96

95

THD

2ND

SNR

94

93

92

SINAD

91

90

3RD

SNR

SINAD

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40

–30

–20

–10

0

–40 –25 –10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

INPUT LEVEL (dB)

TEMPERATURE (°C)

232816 G09

232816 G07

232816 G08

232816fb

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For more information www.linear.com/LTC2328-16

LTC2328-16

T_A= ꢄ.°CV ꢅ_DD= .ꢅV Oꢅ_DD= ꢄꢀ.ꢅV REFꢁI = ꢄꢀꢆ28ꢅV

Typical perForMance characTerisTics

f_LMP5= 1MspsV unless otherwise notedꢀ

ꢁI5/DI5 vs Temperature

Full-Lcale Error vs Temperature

Offset Error vs Temperature

1.0

0.8

20

15

5

4

3

0.6

10

2

0.4

MAX INL

MAX DNL

5

0.2

1

0

MIN DNL

–0.2

–0.4

–0.6

–0.8

–1.0

–1

–2

–3

–4

–5

MIN INL

–10

–15

–20

–40 –25 –10

5

20 35 50 65 80 95 110 125

80 95

110 125

–40 –25 –10

5

20 35 50 65

110 125

–40 –25 –10

5

20 35 50 65

TEMPERATURE (°C)

232816 G10

232816 G11

232816 G12

ꢁnternal Reference Output vs

Temperature

Lupply Current vs Temperature

Lleep Current vs Temperature

12

10

8

120

100

80

60

40

20

0

2.0484

2.0483

2.0482

2.0481

2.0480

2.0479

2.0478

2.0477

2.0476

V

DD

+

–

(IN = IN = 0V)

6

4

2

OV

DD

0

–40 –25 –10

5

20 35 50 65

80 95 110

125

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

232816 G13

232816 G14

232816 G15

ꢁnternal Reference Output

Temperature Coefficient

Distribution

CMRR vs ꢁnput Frequency

Lupply Current vs Lampling Rate

80

75

16

14

12

10

8

35

30

+

V

(IN = –10.24V)

DD

25

70

65

20

15

10

5

+

V

(IN = 0V)

DD

6

60

55

50

4

+

V

DD

(IN = 10.24V)

2

OV

DD

0

100

200

300

400

500

–10

–4

0

2

4

6

8

10

0

100 200 300

400 500

600 700 800 9001000

–8 –6

–2

FREQUENCY (kHz)

DRIFT (ppm/°C)

SAMPLING FREQUENCY (kHz)

232816 G17

232816 G16

232816 G18

232816fb

7

For more information www.linear.com/LTC2328-16

LTC2328-16

pin FuncTions

ꢅ

ꢂPin 1x: 2.5V Supply ꢀypass Pin. The voltage

CHAꢁI ꢂPin 1ꢆx: Chain Mode Selector Pin. When low,

the LTC2328-16 operates in normal mode and the

RDL/SDI input pin functions to enable or disable SDO.

Whenhigh,theLTC2328-16operatesinchainmodeandthe

RDL/SDI pin functions as SDI, the daisy-chain serial data

DD5SYP

on this pin is generated via an onboard regulator off of

DD

V . This pin must be bypassed with a 2.2μF ceramic

capacitor to GND.

ꢅ

ꢂPinꢄx:5VPowerSupply.TherangeofV is4.75Vto

DD

input. Logic levels are determined by OV .

DD

5.25V. ꢀypass V to GND with a 10µF ceramic capacitor.

DD

SULY ꢂPin 11x: ꢀUSY Indicator. Goes high at the start of

GID ꢂPins 3V 6 and 16x: Ground.

a new conversion and returns low when the conversion

+

–

ꢁI ꢂPin 2x: Analog Input. IN operates differential with

has finished. Logic levels are determined by OV .

DD

–

+

respect to IN with an IN -IN range of –2.5 • V

to

REFꢀUF

RD5/LDꢁ ꢂPin 1ꢄx: When CHAIN is low, the part is in nor-

mal mode and the pin is treated as a bus enabling input.

When CHAIN is high, the part is in chain mode and the

pin is treated as a serial data input pin where data from

another ADC in the daisy chain is input. Logic levels are

2.5 • V

.

REFꢀUF

–

ꢁI ꢂPin .x: Analog Ground Sense. IN has an input range

of 500mV with respect to GND and must be tied to the

ground plane or a remote sense.

determined by OV .

DD

REFSUF ꢂPin 7x: Reference ꢀuffer Output. An onboard

buffer nominally outputs 4.096V to this pin. This pin is

referredtoGNDandshouldbedecoupledcloselytothepin

with a 47μF ceramic capacitor. The internal buffer driving

this pin may be disabled by grounding its input at REFIN.

Once the buffer is disabled, an external reference may

overdrive this pin in the range of 2.5V to 5V. A resistive

load greater than 500kΩ can be placed on the reference

buffer output.

LCKꢂPin13x:SerialDataClockInput.WhenSDOisenabled,

the conversion result or daisy-chain data from another

ADC is shifted out on the rising edges of this clock MSꢀ

first. Logic levels are determined by OV .

DD

LDOꢂPin12x:SerialDataOutput. Theconversionresultor

daisy-chain data is output on this pin on each rising edge

of SCK MSꢀ first. The output data is in 2’s complement

format. Logic levels are determined by OV .

DD

REFꢁI ꢂPin 8x: Reference Output/Reference ꢀuffer Input.

An onboard bandgap reference nominally outputs 2.048V

at this pin. ꢀypass this pin with a 100nF ceramic capacitor

to GND to limit the reference output noise. If more accu-

racy is desired, this pin may be overdriven by an external

reference in the range of 1.25V to 2.4V.

Oꢅ ꢂPin 1.x: I/O Interface Digital Power. The range of

DD

OV is 1.71V to 5.25V. This supply is nominally set to

DD

the same supply as the host interface (1.8V, 2.5V, 3.3V,

or 5V). ꢀypass OV to GND with a 0.1μF capacitor.

DD

CIꢅ ꢂPin 9x: Convert Input. A rising edge on this input

powers up the part and initiates a new conversion. Logic

levels are determined by OV .

DD

232816fb

8

For more information www.linear.com/LTC2328-16

LTC2328-16

FuncTional block DiagraM

REFIN = 1.25V REFBUF = 2.5V

OV = 1.8V

DD

TO 5V

V

= 5V

V

= 2.5V

DDLBYP

TO 2.4V

TO 5V

DD

LDO

15k

2.048V

REFERENCE

2× REFERENCE

BUFFER

R

0.63× BUFFER

4R

CHAIN

SDO

RDL/SDI

SCK

+

–

IN

+

SPI

PORT

R

16-BIT SAMPLING ADC

4R

–

CNV

BUSY

CONTROL LOGIC

GND

232816 BD01

TiMing DiagraM

Conversion Timing Using the Lerial ꢁnterface

CHAIN, RDL/SDI = 0

CNV

CONVERT

NAP AND ACQUIRE

BUSY

SCK

SDO

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

232816 TD01

232816fb

9

For more information www.linear.com/LTC2328-16

LTC2328-16

applicaTions inForMaTion

OꢅERꢅꢁEꢇ

TRAILFER FUICTꢁOI

The LTC2328-16 is a low noise, high speed 16-bit suc-

cessive approximation register (SAR) ADC with pseudo-

differential inputs. Operating from a single 5V supply, the

LTC2328-16hasa 10.24Vtruebipolarinputrange,making

it ideal for high voltage applications which require a wide

dynamic range. The LTC2328-16 achieves 1.5LSꢀ INL

maximum, no missing codes at 16-bits and 93.5dꢀ SNR.

The LTC2328-16 digitizes the full-scale voltage of 2.5 •

16

REFꢀUFinto2 levels,resultinginanLSꢀsizeof312.5µV

withREFꢀUF=4.096V.Theidealtransferfunctionisshown

in Figure 2. The output data is in 2’s complement format.

AIA5OG ꢁIPUT

TheanaloginputsoftheLTC2328-16arepseudo-differen-

tialinordertoreduceanyunwantedsignalthatiscommon

to both inputs. The analog inputs can be modeled by the

equivalent circuit shown in Figure 3. The back-to-back

diodes at the inputs form clamps that provide ESD protec-

tion. Each input drives a resistor divider network that has

The LTC2328-16 has an onboard single-shot capable

reference buffer and low drift (20ppm/°C max) 2.048V

temperature-compensated reference. The LTC2328-16

also has a high speed SPI-compatible serial interface that

supports 1.8V, 2.5V, 3.3V and 5V logic while also featur-

ing a daisy-chain mode. The fast 1Msps throughput with

no cycle latency makes the LTC2328-16 ideally suited

for a wide variety of high speed applications. An internal

oscillator sets the conversion time, easing external timing

considerations. The LTC2328-16 dissipates only 50mW

and automatically naps between conversions, leading to

reduced power dissipation that scales with the sampling

rate. A sleep mode is also provided to reduce the power

consumption of the LTC2328-16 to 300μW for further

power savings during inactive periods.

011...111

BIPOLAR

ZERO

011...110

000...001

000...000

111...111

111...110

100...001

100...000

FSR = +FS – –FS

1LSB = FSR/65536

–1 0V

LSB

1

LSB

–FSR/2

FSR/2 – 1LSB

COIꢅERTER OPERATꢁOI

INPUT VOLTAGE (V)

232816 F02

The LTC2328-16 operates in two phases. During the ac-

quisition phase, the charge redistribution capacitor D/A

converter (CDAC) is connected to the outputs of the resis-

tor divider networks that pins IN and IN drive to sample

an attenuated and level-shifted version of the pseudo-

differential analog input voltage as shown in Figure 3. A

rising edge on the CNV pin initiates a conversion. During

the conversion phase, the 16-bit CDAC is sequenced

throughasuccessiveapproximationalgorithm,effectively

comparing the sampled input with binary-weighted frac-

Figure ꢄꢀ 5TCꢄ3ꢄ8-16 Transfer Function

+

–

0.63 • V

REFBUF

C

IN

45pF

R

50Ω

400Ω

ON

1.6k

+

–

IN

0.63 • V

BIAS

VOLTAGE

REFBUF

C

IN

45pF

R

50Ω

400Ω

ON

1.6k

232816 F03

IN

tions of the reference voltage (e.g. V

/2, V

/4

REFꢀUF

… V

/65536) using the differential comparator. At

REFꢀUF

the end of conversion, the CDAC output approximates the

sampledanaloginput.TheADCcontrollogicthenprepares

the 16-bit digital output code for serial transfer.

Figure 3ꢀ The Equivalent Circuit for the Differential

Analog ꢁnput of the 5TCꢄ3ꢄ8-16

232816fb

10

For more information www.linear.com/LTC2328-16

LTC2328-16

applicaTions inForMaTion

a total impedance of 2kΩ. The resistor divider network

attenuates and level shifts the 2.5 • REFꢀUF true bipolar

signal swing of each input to the 0-REFꢀUF input signal

50Ω

66nF

+

–

+

LT±468

IN

±±0ꢀ.4ꢁ

LTC.3.8-±6

swingoftheADCcore.Intheacquisitionphase,45pF(C )

IN

BW = 48kHz

–

IN

fromthesamplingCDACinserieswithapproximately50Ω

(R ) from the on-resistance of the sampling switch is

.3.8±6 F04

ON

connected to the output of the resistor divider network.

Any unwanted signal that is common to both inputs will

be reduced by the common mode rejection of the ADC

Figure 2ꢀ ꢁnput Lignal Chain

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

+

core and resistor divider network. The IN input of the

ADC core draws a current spike while charging the C

capacitor during acquisition.

IN

ꢁIPUT DRꢁꢅE CꢁRCUꢁTL

A low impedance source can directly drive the high im-

pedance input of the LTC2328-16 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

is important even for DC inputs, because the ADC input

draws a current spike when entering acquisition.

Pseudo-Differential Sipolar ꢁnputs

For most applications, we recommend the low power

LT1468 ADC driver to drive the LTC2328-16. With a low

noisedensityof5nV/√Hzandalowsupplycurrentof3mA,

the LT1468 is flexible and may be configured to convert

signals of various amplitudes to the 10.24V input range

of the LTC2328-16.

For best performance, a buffer amplifier should be used

to drive the analog input of the LTC2328-16. The amplifier

provides low output impedance to minimize gain error

and allows for fast settling of the analog signal during

the acquisition phase. It also provides isolation between

the signal source and the ADC input which draws a small

current spike during acquisition.

To achieve the full distortion performance of the

LTC2328-16, a low distortion single-ended signal source

driven through the LT1468 configured as a unity-gain

buffer as shown in Figure 4 can be used to get the full

data sheet THD specification of –111dꢀ.

ꢁnput Filtering

ADC REFEREICE

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Noisy input signals should be filtered prior

to the buffer amplifier input with a low bandwidth filter to

minimizenoise.Thesimple1-poleRClowpassfiltershown

in Figure 4 is sufficient for many applications.

There are three ways of providing the ADC reference. The

first is to use both the internal reference and reference

buffer. The second is to externally overdrive the internal

reference and use the internal reference buffer. The third

is to disable the internal reference buffer and overdrive

the REFꢀUF pin from an external source. The following

tables give examples of these cases and the resulting

bipolar input ranges.

The input resistor divider network, sampling switch on-

resistance (R ) and the sample capacitor (C ) form a

ON

IN

second lowpass filter that limits the input bandwidth to

the ADC core to 7MHz. A buffer amplifier with a low noise

density must be selected to minimize the degradation of

the SNR over this bandwidth.

232816fb

11

For more information www.linear.com/LTC2328-16

LTC2328-16

applicaTions inForMaTion

Table 1ꢀ ꢁnternal Reference with ꢁnternal Suffer

Eꢃternal Reference with ꢁnternal Suffer

REFꢁI

REFSUF

SꢁPO5AR ꢁIPUT RAIGE

If more accuracy and/or lower drift is desired, REFIN

can be easily overdriven by an external reference since

a 15k resistor is in series with the reference as shown

in Figure 5b. REFIN can be overdriven in the range from

1.25V to 2.4V. The resulting voltage at REFꢀUF will be

2 • REFIN. So the input range is 5 • REFIN, as shown

in Table 2. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

manyapplications.Withitssmallsize,lowpower,andhigh

accuracy, the LTC6655-2.048 is well suited for use with

the LTC2328-16 when overdriving the internal reference.

The LTC6655-2.048 offers 0.025% (max) initial accuracy

and 2ppm/°C (max) temperature coefficient for high pre-

cision applications. The LTC6655-2.048 is fully specified

over the H-grade temperature range and complements

the extended temperature range of the LTC2328-16 up to

125°C.ꢀypassingtheLTC6655-2.048witha2.7μFto100µF

ceramiccapacitorclosetotheREFINpinisrecommended.

2.048V

4.096V

10.24V

Table ꢄꢀ Eꢃternal Reference with ꢁnternal Suffer

REFꢁI

ꢂOꢅERDRꢁꢅEx

REFSUF

SꢁPO5AR ꢁIPUT RAIGE

1.25V (Min)

2.048V

2.5V

4.096V

4.8V

6.25V

10.24V

12V

2.4V (Max)

Table 3ꢀ Eꢃternal Reference Unbuffered

REFꢁI

REFSUF

ꢂOꢅERDRꢁꢅEx

SꢁPO5AR ꢁIPUT RAIGE

0V

2.5V (Min)

5V (Max)

6.25V

12.5V

ꢁnternal Reference with ꢁnternal Suffer

The LTC2328-16 has an on-chip, low noise, low drift

(20ppm/°C max), temperature compensated bandgap

reference that is factory trimmed to 2.048V. It is internally

connected to a reference buffer as shown in Figure 5a and

is available at REFIN (Pin 8). REFIN should be bypassed to

GNDwitha100nFceramiccapacitortominimizenoise.The

reference buffer gains the REFIN voltage by 2 to 4.096V at

REFꢀUF (Pin 7). So the input range is 10.24V, as shown

in Table 1. ꢀypass REFꢀUF to GND with at least a 47μF

ceramic capacitor (X7R, 10V, 1210 size) to compensate

the reference buffer and minimize noise.

Eꢃternal Reference Unbuffered

The internal reference buffer can also be overdriven from

2.5V to 5V with an external reference at REFꢀUF as shown

in Figure 5c. So the input ranges are 6.25V to 12.5V,

respectively, as shown in Table 3. To do so, REFIN must

be grounded to disable the reference buffer. A 13k resistor

loadstheREFꢀUFpinwhenthereferencebufferisdisabled.

To maximize the input signal swing and corresponding

SNR, the LTC6655-5 is recommended when overdriv-

ing REFꢀUF. The LTC6655-5 offers the same small size,

accuracy, drift and extended temperature range as the

LTC6655-2.048. ꢀy using this 5V reference, an SNR of

94.5dꢀ can be achieved. ꢀypassing the LTC6655-5 with

a 47μF ceramic capacitor (X5R, 0805 size) close to the

REFꢀUF pin is recommended.

15k

REFIN

BANDGAP

REFERENCE

100nF

+

REFBUF

REFERENCE

BUFFER

–

TheREFꢀUFpinoftheLTC2328-16drawsacharge(Q

)

CONV

6.5k

fromtheexternalbypasscapacitorduringeachconversion

cycle. If the internal reference buffer is overdriven, the

external reference must provide all of this charge with a

47µF

6.5k

LTC2328-16

GND

232816 F05a

DC current equivalent to I

= Q

/t . Thus, the

REFꢀUF

CONV CYC

DC current draw of REFꢀUF depends on the sampling

Figure .aꢀ 5TCꢄ3ꢄ8-16 ꢁnternal Reference Circuit

232816fb

12

For more information www.linear.com/LTC2328-16

LTC2328-16

applicaTions inForMaTion

of the output code. If an external reference is used to

overdrive REFꢀUF, the fast settling LTC6655-5 reference

is recommended.

15k

REFIN

BANDGAP

REFERENCE

2.7µF

+

REFBUF

REFERENCE

BUFFER

–

ꢁnternal Reference Suffer Transient Response

47µF

LTC6655-2.048

6.5k

Foroptimumtransientperformance,theinternalreference

buffer should be used. The internal reference buffer uses a

proprietarydesignthatresultsinanoutputvoltagechange

atREFꢀUFoflessthan0.25LSꢀwhenrespondingtoasud-

denburstofconversions.Thismakestheinternalreference

bufferoftheLTC2328-16trulysingle-shotcapablesincethe

first sample taken after idling will yield the same result as

a sample taken after the transient response of the internal

reference buffer has settled. Figure 7 shows the transient

responses of the LTC2328-16 with the internal reference

buffer and with the internal reference buffer overdriven by

the LTC6655-5, both with a bypass capacitance of 47μF.

6.5k

LTC2328-16

GND

232816 F05b

Figure .bꢀ Using the 5TC66..-ꢄꢀꢆ28 as an Eꢃternal Reference

15k

REFIN

BANDGAP

REFERENCE

+

REFBUF

REFERENCE

BUFFER

–

6.5k

47µF

LTC6655-5

0.5

6.5k

INTERNAL REFERENCE BUFFER

LTC2328-16

GND

0

232816 F05c

–0.5

Figure .cꢀ Overdriving REFSUF Using the 5TC66..-.

EXTERNAL SOURCE ON REFBUF

–1.0

rate and output code. In applications where a burst of

samples is taken after idling for long periods, as shown in

–1.5

–2.0

Figure 6, I

quickly goes from approximately 390µA

REFꢀUF

0

100 200 300 400 500 600 700 800 9001000

to a maximum of 1.2mA for REFꢀUF = 5V at 1Msps. This

step in DC current draw triggers a transient response in

the external reference that must be considered since any

deviation in the voltage at REFꢀUF will affect the accuracy

TIME (µs)

232816 F07

Figure 7ꢀ Transient Response of the 5TCꢄ3ꢄ8-16

CNV

232816 F06

IDLE

PERIOD

IDLE

PERIOD

Figure 6ꢀ CIꢅ ꢇaveform Lhowing Surst Lampling

232816fb

13

For more information www.linear.com/LTC2328-16

LTC2328-16

applicaTions inForMaTion

DYIAMꢁC PERFORMAICE

Total Harmonic Distortion ꢂTHDx

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. ꢀy applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2328-16 provides

guaranteed tested limits for both AC distortion and noise

measurements.

TotalHarmonicDistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

2

V2²+ V3²+ V4²+…+ V_N

THD=20log

V1

where V1 is the RMS amplitude of the fundamental

Lignal-to-Ioise and Distortion Ratio ꢂLꢁIADx

frequency and V2 through V are the amplitudes of the

N

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 8 shows that the LTC2328-16 achieves

a typical SINAD of 93.4dꢀ at a 1MHz sampling rate with

a 2kHz input.

second through Nth harmonics.

POꢇER COILꢁDERATꢁOIL

The LTC2328-16 provides two power supply pins: the 5V

power supply (V ), and the digital input/output interface

DD

power supply (OV ). The flexible OV supply allows

DD

the LTC2328-16 to communicate with any digital logic

operating between 1.8V and 5V, including 2.5V and 3.3V

systems.

Lignal-to-Ioise Ratio ꢂLIRx

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 8 shows

that the LTC2328-16 achieves a typical SNR of 93.5dꢀ at

a 1MHz sampling rate with a 2kHz input.

Power Lupply Lequencing

The LTC2328-16 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2328-16

has a power-on reset (POR) circuit that will reset the

LTC2328-16 at initial power-up or whenever the power

supply voltage drops below 2V. Once the supply voltage

reenters the nominal supply voltage range, the POR will

re-initialize the ADC. No conversions should be initiated

until 200μs after a POR event to ensure the re-initialization

period has ended. Any conversions initiated before this

time will produce invalid results.

0

SNR = 93.5dB

–20

–40

THD = –111dB

SINAD = 93.4dB

SFDR = –115dB

–60

–80

–100

–120

–140

–160

–180

TꢁMꢁIG AID COITRO5

CIꢅ Timing

0

100

200

300

400

500

FREQUENCY (kHz)

232816 F08

The LTC2328-16 conversion is controlled by CNV. A ris-

ing edge on CNV will start a conversion and power up

the LTC2328-16. Once a conversion has been initiated,

Figure 8ꢀ 3ꢄk Point FFT of the 5TCꢄ3ꢄ8-16

it cannot be restarted until the conversion is complete.

232816fb

14

For more information www.linear.com/LTC2328-16

LTC2328-16

applicaTions inForMaTion

For optimum performance, CNV should be driven by a

clean low jitter signal. Converter status is indicated by the

ꢀUSY output which remains high while the conversion is

in progress. To ensure that no errors occur in the digitized

results, any additional transitions on CNV should occur

within 40ns from the start of the conversion or after the

conversion has been completed. Once the conversion has

completed, the LTC2328-16 powers down and begins

acquiring the input signal.

Lleep Mode

Theautonapmodefeatureprovideslimitedpowersavings

since only the ADC core powers down. To obtain greater

power savings, the LTC2328-16 provides a sleep mode.

During sleep mode, the entire part is powered down

except for a small standby current resulting in a power

dissipation of 300μW. To enter sleep mode, toggle CNV

twice with no intervening rising edge on SCK. The part

will enter sleep mode on the falling edge of ꢀUSY from

the last conversion initiated. Once in sleep mode, a rising

edge on SCK will wake the part up. Upon emerging from

ꢁnternal Conversion Clock

The LTC2328-16 has an internal clock that is trimmed to

achieveamaximumconversiontimeof527ns.Withamini-

mum acquisition time of 460ns, throughput performance

of 1Msps is guaranteed without any external adjustments.

sleep mode, wait t

ms before initiating a conversion

WAKE

to allow the reference and reference buffer to wake up

and charge the bypass capacitors at REFIN and REFꢀUF.

(Refer to the Timing Diagrams section for more detailed

timing information about sleep mode.)

Auto Iap Mode

The LTC2328-16 automatically enters nap mode after a

conversion has been completed and completely powers

up once a new conversion is initiated on the rising edge of

CNV. During nap mode, only the ADC core powers down

and all other circuits remain active. During nap, data from

thelastconversioncanbeclockedout. Theautonapmode

featurewillreducethepowerdissipationoftheLTC2328-16

as the sampling frequency is reduced. Since full power is

consumed only during a conversion, the ADC core of the

LTC2328-16remainspowereddownforalargerfractionof

DꢁGꢁTA5 ꢁITERFACE

The LTC2328-16 has a serial digital interface. The flexible

OV supplyallowstheLTC2328-16tocommunicatewith

DD

any digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

The serial output data is clocked out on the SDO pin when

anexternalclockisappliedtotheSCKpinifSDOisenabled.

Clocking out the data after the conversion will yield the

best performance. With a shift clock frequency of at least

40MHz, a 1Msps throughput is still achieved. The serial

output data changes state on the rising edge of SCK and

can be captured on the falling edge or next rising edge of

SCK. D15 remains valid till the first rising edge of SCK.

the conversion cycle (t ) at lower sample rates, thereby

CYC

reducing the average power dissipation which scales with

the sampling rate as shown in Figure 9.

16

The serial interface on the LTC2328-16 is simple and

straightforwardtouse.Thefollowingsectionsdescribethe

operationoftheLTC2328-16. Severalmodesareprovided

depending on whether a single or multiple ADCs share the

SPI bus or are daisy-chained.

14

+

V

(IN = –10.24V)

DD

12

10

8

+

V

(IN = 0V)

DD

6

4

+

V

(IN = 10.24V)

DD

2

OV

DD

0

400 500

1

100 200 300

600 700 800 9001000

SAMPLING FREQUENCY (kHz)

232816 F09

Figure 9ꢀ Power Lupply Current of the 5TCꢄ3ꢄ8-16

ꢅersus Lampling Rate

232816fb

15

For more information www.linear.com/LTC2328-16

LTC2328-16

applicaTions inForMaTion

Iormal ModeV Lingle Device

shows a single LTC2328-16 operated in normal mode

with CHAIN and RDL/SDI tied to ground. With RDL/SDI

grounded, SDO is enabled and the MSꢀ(D15) of the new

conversion data is available at the falling edge of ꢀUSY.

This is the simplest way to operate the LTC2328-16.

When CHAIN = 0, the LTC2328-16 operates in normal

mode. In normal mode, RDL/SDI enables or disables the

serial data output pin SDO. If RDL/SDI is high, SDO is in

highimpedance.IfRDL/SDIislow,SDOisdriven.Figure10

CONVERT

DIGITAL HOST

IRQ

CNV

CHAIN

BUSY

SDO

LTC2328-16

RDL/SDI

SCK

DATA IN

CLK

NAP AND ACQUIRE

CONVERT

NAP AND ACQUIRE

CONVERT

CHAIN = 0

RDL/SDI = 0

t

CYC

t

CNVH

t

CNVL

CNV

t

= t

– t

ACQ CYC CONV BUSYLH

t

CONV

ACQ

BUSY

t

SCK

t

BUSYLH

t

QUIET

SCKH

1

2

3

14

15

16

SCK

SDO

t

SCKL

HSDO

t

DSDO

DSDOBUSYL

D15

D14

D13

D1

D0

232816 F10

Figure 1ꢆꢀ Using a Lingle 5TCꢄ3ꢄ8-16 in Iormal Mode

232816fb

16

For more information www.linear.com/LTC2328-16

LTC2328-16

applicaTions inForMaTion

Iormal ModeV Multiple Devices

be used to allow only one LTC2328-16 to drive SDO at a

timeinordertoavoidbusconflicts. AsshowninFigure11,

the RDL/SDI inputs idle high and are individually brought

low to read data out of each device between conversions.

When RDL/SDI is brought low, the MSꢀ of the selected

device is output onto SDO.

Figure 11 shows multiple LTC2328-16 devices operating

in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.

ꢀy sharing CNV, SCK and SDO, the number of required

signals to operate multiple ADCs in parallel is reduced.

Since SDO is shared, the RDL/SDI input of each ADC must

RDL

B

A

CONVERT

CNV

CHAIN

BUSY

SDO

IRQ

CHAIN

LTC2328-16

B

LTC2328-16

A

DIGITAL HOST

SDO

RDL/SDI

SCK

DATA IN

CLK

NAP AND

ACQUIRE

CONVERT

NAP AND ACQUIRE

CHAIN = 0

t

CNVL

CNV

t

CONV

BUSY

t

BUSYLH

RDL/SDI

A

B

RDL/SDI

t

SCK

t

QUIET

SCKH

SCK

SDO

1

2

3

14

15

16

17

18

19

30

31

32

t

SCKL

HSDO

t

DIS

DSDO

t

EN

Hi-Z

D15

D14

D13

D1

A

D0

A

D15

D14

D13

D1

B

D0

B

A

B

232818 F11

Figure 11ꢀ Iormal Mode with Multiple Devices Lharing CIꢅV LCKV and LDO

232816fb

17

For more information www.linear.com/LTC2328-16

LTC2328-16

applicaTions inForMaTion

Chain ModeV Multiple Devices

may limit the numberoflines needed to interface toa large

number of converters. Figure 12 shows an example with

two daisy-chained devices. The MSꢀ of converter A will

appear at SDO of converter ꢀ after 16 SCK cycles. The

MSꢀ of converter A is clocked in at the SDI/RDL pin of

converter ꢀ on the rising edge of the first SCK.

When CHAIN = OV , the LTC2328-16 operates in

DD

chain mode. In chain mode, SDO is always enabled and

RDL/SDI serves as the serial data input pin (SDI) where

daisy-chain data output from another ADC can be input.

This is useful for applications where hardware constraints

CONVERT

OV

DD

CNV

CHAIN

DIGITAL HOST

LTC2328-16

RDL/SDI

SDO

RDL/SDI

BUSY

SDO

IRQ

A

B

DATA IN

SCK

CLK

NAP AND

ACQUIRE

CONVERT

NAP AND ACQUIRE

CONVERT

CHAIN = OV

DD

RDL/SDI = 0

A

t

CYC

t

CNVL

CNV

BUSY

t

CONV

t

BUSYLH

SCK

t

SCKCH

t

QUIET

SCKH

1

2

3

14

15

16

17

18

30

31

32

t

SCKL

t

HSDO

SSDISCK

t

DSDO

HSDISCK

SDO = RDL/SDI

A

B

D15

D14

D13

D1

D0

A

t

DSDOBUSYL

D15

D14

D13

D1

B

D15

D14

D1

A

D0

A

SDO

B

A

B

232816 F12

Figure 1ꢄꢀ Chain Mode Timing Diagram

232816fb

18

For more information www.linear.com/LTC2328-16

LTC2328-16

applicaTions inForMaTion

Lleep Mode

the last conversion initiated. Once in sleep mode, a rising

edge on SCK will wake the part up. Upon emerging from

To enter sleep mode, toggle CNV twice with no interven-

ing rising edge on SCK as shown in Figure 13. The part

will enter sleep mode on the falling edge of ꢀUSY from

sleep mode, wait t

ms before initiating a conversion

WAKE

to allow the reference and reference buffer to wake up

and charge the bypass capacitors at REFIN and REFꢀUF.

NAP AND

ACQUIRE

CHAIN = DON’T CARE

ACQUIRE

RDL/SDI = DON’T CARE

CONVERT

SLEEP

CONVERT

t

CNVH

WAKE

CNV

t

CONV

BUSY

t

BUSYLH

SCK

NAP AND

ACQUIRE

CHAIN = DON’T CARE

RDL/SDI = DON’T CARE

CONVERT

SLEEP

CONVERT

t

WAKE

CNVH

CNV

t

CONV

BUSY

t

BUSYLH

SCK

232816 F13

Figure 13ꢀ Lleep Mode Timing Diagram

232816fb

19

For more information www.linear.com/LTC2328-16

LTC2328-16

boarD layouT

To obtain the best performance from the LTC2328-16 a

printed circuit board (PCꢀ) is recommended. Layout for

PCꢀ should ensure the digital and analog signal lines are

separated as much as possible. In particular, care should

be taken not to run any digital clocks or signals alongside

analog signals or underneath the ADC.

Recommended 5ayout

ThefollowingisanexampleofarecommendedPCꢀlayout.

A single solid ground plane is used. ꢀypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC1908, the

evaluation kit for the LTC2328-16.

Partial Top Lilkscreen

232816fb

20

For more information www.linear.com/LTC2328-16

LTC2328-16

boarD layouT

Partial 5ayer 1 Component Lide

Partial 5ayer ꢄ Ground Plane

232816fb

21

For more information www.linear.com/LTC2328-16

LTC2328-16

boarD layouT

Partial 5ayer 3 Power Plane

Partial 5ayer 2 Sottom 5ayer

232816fb

22

For more information www.linear.com/LTC2328-16

LTC2328-16

boarD layouT

Partial Lchematic of Demo Soard

232816fb

23

For more information www.linear.com/LTC2328-16

LTC2328-16

package DescripTion

Please refer to http://wwwꢀlinearꢀcom/product/5TCꢄ3ꢄ8-16#packaging for the most recent package drawingsꢀ

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev A)

0.889 ±0.127

(.035 ±.005)

5.10

3.20 – 3.45

(.201)

(.126 – .136)

MIN

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

0.50

(.0197)

BSC

0.305 ±0.038

(.0120 ±.0015)

TYP

0.280 ±0.076

(.011 ±.003)

REF

16151413121110

9

RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

DETAIL “A”

0.254

4.90 ±0.152

(.193 ±.006)

(.010)

0° – 6° TYP

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

1 2 3 4 5 6 7 8

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

MSOP (MS16) 0213 REV A

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

232816fb

24

For more information www.linear.com/LTC2328-16

LTC2328-16

revision hisTory

REꢅ

DATE

DELCRꢁPTꢁOI

PAGE IUMSER

A

12/14 Change t

time units to ns

5

6

ACQ

ꢀ

08/16 Updated graphs G01, G02 and G03

232816fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

25

For more information www.linear.com/LTC2328-16

LTC2328-16

Typical applicaTion

5T1268 Configured to Suffer a 1ꢆꢀꢄ2ꢅ Lingle-Ended Lignal ꢁnto the 5TCꢄ3ꢄ8-16

15V

7

LT1468

5V

+10.24V

–10.24V

3

2

+

–

V

DD

+

–

IN

6

LTC2328-16

REFBUF

47µF

REFIN

4

100nF

232816 TA02

–15V

relaTeD parTs

PART IUMSER

ADCs

DELCRꢁPTꢁOI

COMMEITL

LTC2338-18/LTC2337-18/ 18-ꢀit, 1Msps/500ksps/250ksps Serial,

LTC2336-18 Low Power ADC

5V Supply, 10.24V True ꢀipolar, Differential Input, 100dꢀ SNR, Pin-Compatible

Family in MSOP-16 Package

LTC2328-18/LTC2327-18/ 18-ꢀit, 1Msps/500ksps/250ksps Serial,

LTC2326-18 Low Power ADC

5V Supply, 10.24V True ꢀipolar, Pseudo-Differential Input, 95dꢀ SNR,

Pin-Compatible Family in MSOP-16 Package

LTC2378-20/LTC2377-20/ 20-ꢀit, 1Msps/500ksps/250ksps Serial,

LTC2376-20 Low Power ADC

2.5V Supply, Differential Input, 0.5ppm INL, 5V Input Range, DGC,

Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2379-18/LTC2378-18/ 18-ꢀit, 1.6Msps/1Msps/500ksps/250ksps

LTC2377-18/LTC2376-18 Serial, Low Power ADC

2.5V Supply, Differential Input, 101.2dꢀ SNR, 5V Input Range, DGC,

Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2380-16/LTC2378-16/ 16-ꢀit, 2Msps/1Msps/500ksps/250ksps

LTC2377-16/LTC2376-16 Serial, Low Power ADC

2.5V Supply, Differential Input, 96.2dꢀ SNR, 5V Input Range, DGC,

Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2369-18/LTC2368-18/ 18-ꢀit, 1.6Msps/1Msps/500ksps/250ksps

LTC2367-18/LTC2364-18 Serial, Low Power ADC

2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dꢀ SNR, 0V to 5V Input

Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2370-16/LTC2368-16/ 16-ꢀit, 2Msps/1Msps/500ksps/250ksps

LTC2367-16/LTC2364-16 Serial, Low Power ADC

2.5V Supply, Pseudo-Differential Unipolar Input, 94dꢀ SNR, 0V to 5V Input

Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2389-18/LTC2389-16 18-ꢀit/16-ꢀit, 2.5Msps Parallel/Serial ADC

5V Supply, Pin-Configurable Input Range, 99.8dꢀ/96dꢀ SNR, Parallel or Serial

I/O 7mm × 7mm LQFP-48 and QFN-48 Packages

DACs

LTC2756/LTC2757

18-ꢀit, Single Serial/Parallel I

SoftSpan™

OUT

1LSꢀ INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm LQFP-48

Package

DAC

LTC2641

LTC2630

References

LTC6655

16-ꢀit/14-ꢀit/12-ꢀit Single Serial V

DAC

1LSꢀ INL /DNL, MSOP-8 Package, 0V to 5V Output

OUT

12-ꢀit/10-ꢀit/8-ꢀit Single V

DACs

1LSꢀ INL (12 ꢀits), Internal Reference, SC70 6-Pin Package

OUT

Precision Low Drift Low Noise ꢀuffered

Reference

5V/2.5V/2.048V/1.2V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

5V/2.5V/2.048V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package

LTC6652

Precision Low Drift Low Noise ꢀuffered

Reference

Amplifiers

LT1468/LT1469

Single/Dual 90MHz, 22V/μs, 16-ꢀit Accurate Low Input Offset: 75μV/125µV

Op Amp

232816fb

LT 0816 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417

26

For more information www.linear.com/LTC2328-16

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2328-16

●

 LINEAR TECHNOLOGY CORPORATION 2014


型号：	LTC2328-16
厂家：	Linear
描述：	16-Bit, 1Msps, Â±10.24V True Bipolar, Pseudo-Differential Input ADC with 93.5dB SNR
文件：	总26页 (文件大小：992K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2328-16 [Linear]

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