LTC2335ILX-18#PBF [Linear]
LTC2335-18 - 18-Bit, 1Msps 8-Channel Differential ±10.24V Input SoftSpan ADC with Wide Input Common Mode Range; Package: LQFP; Pins: 48; Temperature Range: -40°C to 85°C;
| 型号： | LTC2335ILX-18#PBF |
| 厂家： | 
Linear |
| 描述： | LTC2335-18 - 18-Bit, 1Msps 8-Channel Differential ±10.24V Input SoftSpan ADC with Wide Input Common Mode Range; Package: LQFP; Pins: 48; Temperature Range: -40°C to 85°C 转换器 |
| 文件： | 总40页 (文件大小：2034K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2335-18
18-Bit, 1Msps 8-Channel
Differential 1ꢀ0.24 ꢁnpꢂt ꢃSftꢃpan ꢄDC
with Wide ꢁnpꢂt CSmmSn MSde Range
DescripTion
FeaTures
The LTC®2335-18 is an 18-bit, low noise 8-channel multi-
n
1Msps Throughput
n
plexedsuccessiveapproximationregister(SAR)ADCwith
differential, wide common mode range inputs. Operating
froma5Vlowvoltagesupply,flexiblehighvoltagesupplies,
andusingtheinternalreferenceandbuffer,thisSoftSpanTM
ADC can be configured on a conversion-by-conversion
basis to accept 1ꢀ.2ꢁV, ꢀV to 1ꢀ.2ꢁV, 5.12V, or ꢀV to
5.12V signals on any channel. Alternately, the ADC may
be programmed to cycle through a sequence of channels
and ranges without further user intervention.
±±3LS ꢀI3 ꢁMꢂaxiuim ±1ꢃꢄ0.2 VꢂRgnꢅ
GuꢂrꢂRtnnd 18-Sxtm Io MxssxRg Codns
DxffnrnRtxꢂlm Wxdn CoiioR Modn VꢂRgn ꢀRputs
8-ChꢂRRnl Multxplnanr wxth LoftLpꢂR ꢀRput VꢂRgns:
±1ꢃꢄ0.2m ꢃ2 to 1ꢃꢄ0.2m ±ꢆꢄ102m ꢃ2 to ꢆꢄ102
±10ꢄꢆ2m ꢃ2 to 10ꢄꢆ2m ±ꢇꢄ0ꢆ2m ꢃ2 to ꢇꢄ0ꢆ2
9ꢇꢄ7dS LxRgln-CoRvnrsxoR LIV ꢁTypxcꢂlꢅ
n
n
n
n
n
−1ꢃ9dS THD ꢁTypxcꢂlꢅ ꢂt f = 0kHz
ꢀI
n
n
n
n
n
n
n
n
n
118dS CMVVm 10ꢆdS Actxvn Crosstꢂlk ꢁTypxcꢂlꢅ
Vꢂxl-to-Vꢂxl ꢀRput Ovnrdrxvn TolnrꢂRcn
Programmable Sequencer with No-Latency Control
Guaranteed Operation to 125°C
Integrated Reference and Buffer (ꢁ.ꢀ96V)
SPI CMOS (1.8V to 5V) and LVDS Serial I/O
No Pipeline Delay, No Cycle Latency
The wide input common mode range and 118dB CMRR of
the LTC2335-18 analog inputs allow the ADC to directly
digitize a variety of signals, simplifying signal chain de-
sign. This input signal flexibility, combined with 3LSB
INL, no missing codes at 18 bits, and 96.7dB SNR, makes
the LTC2335-18 an ideal choice for many high voltage
applications requiring wide dynamic range.
18ꢀmW Power Dissipation (Typical)
ꢁ8-Lead (7mm × 7mm) LQFP Package
TheLTC2335-18supportspin-selectableSPICMOS(1.8V
to 5V) and LVDS serial interfaces.
applicaTions
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 77ꢀ5765, 7961132, 8319673.
Other Patents pending.
n
Programmable Logic Controllers
n
Industrial Process Control
Power Line Monitoring
Test and Measurement
n
n
Typical applicaTion
15V
0.1µF
5V
0.1µF
1.8V TO 5V
0.1µF
ꢀRtngrꢂl IoRlxRnꢂrxty vs
2.2µF
V
Output Codn ꢂRd ChꢂRRnl
CMOS OR LVDS
I/O INTERFACE
2.0
±±10.24V RANG
–
FULLY
DIFFERENTIAL
+5V
TRUE BIPOLAR DRIVE (IN = 0V)
1.5
1.0
V
V
OV
DD
LVDS/CMOS
CC
DD
DDLBYP
+
–
ARBITRARY
ALL CHANNELS
IN0
IN0
PD
+10V
LTC2335-18
0V
0V
0.5
SDO
SCKO
SCKI
SDI
CS
BUSY
CNV
–10V
–5V
0
18-BIT
MUX
SAMPLING
ADC
–0.5
–1.0
–1.5
–2.0
UNIPOLAR
TRUE BIPOLAR
+10V
+10V
SAMPLE
CLOCK
0V
0V
+
–
–10V
–10V
IN7
IN7
+
–
V
REFBUF REFIN
47µF
GND
0.1µF
EE
DIFFERENTIAL INPUTS IN /IN WITH
WIDE INPUT COMMON MODE RANGE
–131072 –65536
0
65536
131072
233518 TA01a
OUTPUT CODE
233518 TA01b
0.1µF
–15V
233518f
1
For more information www.linear.com/LTC2335-18
LTC2335-18
absoluTe MaxiMuM raTings
pin conFiguraTion
ꢁIotns 1m 0ꢅ
TOP VIEW
Supply Voltage (V ) .....................–ꢀ.3V to (V + ꢁꢀV)
CC
EE
Supply Voltage (V )................................ –17.ꢁV to ꢀ.3V
EE
Supply Voltage Difference (V – V )......................ꢁꢀV
CC
EE
Supply Voltage (V )..................................................6V
DD
Supply Voltage (OV )................................................6V
DD
–
IN6
IN6
IN5
IN5
IN4
IN4
IN3
IN3
IN2
1
2
3
4
5
6
7
8
9
36 GND
Internal Regulated Supply Bypass (V
Analog Input Voltage
) ... (Note 3)
+
–
+
–
+
–
+
–
+
–
+
DDLBYP
35 SDO
34 SDO
–
33 SCKO /SDO
+
–
+
–
+
INꢀ to IN7 ,
32 SCKO /SCKO
31 OV
DD
INꢀ to IN7 (Note ꢁ) .........(V – ꢀ.3V) to (V + ꢀ.3V)
EE
CC
30 GND
–
29 SCKI /SCKI
REFIN.................................................... –ꢀ.3V to 2.8V
+
28 SCKI
–
+
IN2 10
27 SDI
REFBUF, CNV (Note 5) ............. –ꢀ.3V to (V + ꢀ.3V)
DD
DD
DD
–
IN1 11
26 SDI
+
Digital Input Voltage (Note 5)..... –ꢀ.3V to (OV + ꢀ.3V)
IN1 12
25 GND
Digital Output Voltage (Note 5).. –ꢀ.3V to (OV + ꢀ.3V)
Power Dissipation.............................................. 5ꢀꢀmW
Operating Temperature Range
LTC2335C................................................ ꢀ°C to 7ꢀ°C
LTC2335I .............................................–ꢁꢀ°C to 85°C
LTC2335H.......................................... –ꢁꢀ°C to 125°C
Storage Temperature Range .................. –65°C to 15ꢀ°C
LX PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
T
JMAX
= 15ꢀ°C, θ = 53°C/W
JA
orDer inForMaTion
3EAD FVEE FꢀIꢀLH
LTC2335CLX-18#PBF
LTC2335ILX-18#PBF
LTC2335HLX-18#PBF
TVAY
PAVT MAVKꢀIG*
LTC2335LX-18
LTC2335LX-18
LTC2335LX-18
PACKAGE DELCVꢀPTꢀOI
TEMPEVATUVE VAIGE
ꢀ°C to 7ꢀ°C
LTC2335CLX-18#PBF
LTC2335ILX-18#PBF
LTC2335HLX-18#PBF
ꢁ8-Lead (7mm × 7mm) Plastic LQFP
ꢁ8-Lead (7mm × 7mm) Plastic LQFP
ꢁ8-Lead (7mm × 7mm) Plastic LQFP
–ꢁꢀ°C to 85°C
–ꢁꢀ°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
233518f
2
For more information www.linear.com/LTC2335-18
LTC2335-18
elecTrical characTerisTics Thn l dnRotns thn spncxfxcꢂtxoRs whxch ꢂpply ovnr thn full opnrꢂtxRg
tnipnrꢂturn rꢂRgnm othnrwxsn spncxfxcꢂtxoRs ꢂrn ꢂt TA = 0ꢆ°Cꢄ ꢁIotn ꢇꢅ
LYMSO3
V +
PAVAMETEV
COIDꢀTꢀOIL
MꢀI
TYP
MAX
UIꢀTL
l
l
Absolute Input Range
(Note 7)
V
V
CC
– ꢁ
V
IN
EE
+
+
(INꢀ to IN7 )
V –
IN
Absolute Input Range
(Note 7)
V
V
CC
– ꢁ
V
EE
–
–
(INꢀ to IN7 )
l
l
l
l
l
l
l
l
V + – V – Input Differential Voltage
SoftSpan 7: ±2.5 • V
SoftSpan 6: ±2.5 • V
Range (Note 7)
–2.5 • V
2.5 • V
REFBUF
2.5 • V
REFBUF
V
V
V
V
V
V
V
V
IN
IN
REFBUF
REFBUF
SoftSpan 5: ꢀV to 2.5 • V
SoftSpan ꢁ: ꢀV to 2.5 • V
REFBUF
REFBUF
Range
/1.ꢀ2ꢁ Range (Note 7)
–2.5 • V
/1.ꢀ2ꢁ
2.5 • V
/1.ꢀ2ꢁ
REFBUF
ꢀ
ꢀ
Range (Note 7)
REFBUF
REFBUF
REFBUF
REFBUF
/1.ꢀ2ꢁ Range (Note 7)
2.5 • V
/1.ꢀ2ꢁ
REFBUF
SoftSpan 3: ±1.25 • V
SoftSpan 2: ±1.25 • V
SoftSpan 1: ꢀV to 1.25 • V
SoftSpan ꢀ: ꢀV to 1.25 • V
Range (Note 7)
–1.25 • V
1.25 • V
REFBUF
REFBUF
/1.ꢀ2ꢁ
/1.ꢀ2ꢁ Range (Note 7)
–1.25 • V
1.25 • V
/1.ꢀ2ꢁ
REFBUF
ꢀ
ꢀ
REFBUF
Range (Note 7)
1.25 • V
REFBUF
REFBUF
REFBUF
/1.ꢀ2ꢁ Range (Note 7)
1.25 • V
/1.ꢀ2ꢁ
REFBUF
l
l
l
V
Input Common Mode Voltage (Note 7)
Range
V
V – ꢁ
CC
V
CM
EE
V + – V – Input Differential Overdrive
(Note 8)
−(V − V
)
EE
(V − V
CC
)
V
IN
IN
CC
EE
Tolerance
I
Analog Input Leakage Current
Analog Input Capacitance
–1
1
µA
IN
C
Sample Mode
Hold Mode
5ꢀ
1ꢀ
pF
pF
IN
l
CMRR
Input Common Mode
Rejection Ratio
V + = V − = 18V 2ꢀꢀHz Sine
1ꢀꢀ
1.3
118
dB
IN
IN
P-P
l
l
l
V
V
CNV High Level Input Voltage
CNV Low Level Input Voltage
CNV Input Current
V
V
IHCNV
ILCNV
INCNV
ꢀ.5
1ꢀ
I
V
= ꢀV to V
–1ꢀ
μA
IN
DD
converTer characTerisTics Thn l dnRotns thn spncxfxcꢂtxoRs whxch ꢂpply ovnr thn full opnrꢂtxRg
tnipnrꢂturn rꢂRgnm othnrwxsn spncxfxcꢂtxoRs ꢂrn ꢂt TA = 0ꢆ°Cꢄ ꢁIotn 9ꢅ
LYMSO3 PAVAMETEV
COIDꢀTꢀOIL
MꢀI
18
TYP
MAX
UIꢀTL
Bits
l
l
Resolution
No Missing Codes
18
Bits
Transition Noise
SoftSpans 7 and 6: 1ꢀ.2ꢁV and 1ꢀV Ranges
SoftSpans 5 and ꢁ: ꢀV to 1ꢀ.2ꢁV and ꢀV to 1ꢀV Ranges
SoftSpans 3 and 2: 5.12V and 5V Ranges
1.3
2.6
2.ꢀ
ꢁ.ꢀ
LSB
RMS
RMS
RMS
RMS
LSB
LSB
LSB
SoftSpans 1 and ꢀ: ꢀV to 5.12V and ꢀV to 5V Ranges
l
l
l
l
INL
Integral Linearity Error
SoftSpans 7 and 6: 1ꢀ.2ꢁV and 1ꢀV Ranges (Note 1ꢀ)
SoftSpans 5 and ꢁ: ꢀV to 1ꢀ.2ꢁV and ꢀV to 1ꢀV Ranges (Note 1ꢀ)
SoftSpans 3 and 2: 5.12V and 5V Ranges (Note 1ꢀ)
–3
–ꢁ
–2.5
–2.5
1
3
LSB
LSB
LSB
LSB
1.5
ꢁ
ꢀ.75
ꢀ.75
2.5
2.5
SoftSpans 1 and ꢀ: ꢀV to 5.12V and ꢀV to 5V Ranges (Note 1ꢀ)
l
l
DNL
ZSE
Differential Linearity Error (Note 11)
−ꢀ.9
ꢀ.2
8ꢀ
ꢀ.9
LSB
μV
Zero-Scale Error
(Note 12)
(Note 12)
−55ꢀ
55ꢀ
Zero-Scale Error Drift
Full-Scale Error
2
μV/°C
%FS
l
FSE
−ꢀ.1
ꢀ.ꢀ25
2.5
ꢀ.1
Full-Scale Error Drift
ppm/°C
233518f
3
For more information www.linear.com/LTC2335-18
LTC2335-18
DynaMic accuracy Thn l dnRotns thn spncxfxcꢂtxoRs whxch ꢂpply ovnr thn full opnrꢂtxRg tnipnrꢂturn rꢂRgnm
othnrwxsn spncxfxcꢂtxoRs ꢂrn ꢂt TA = 0ꢆ°Cꢄ AꢀI = –1dSFLꢄ ꢁIotns 9m 1±ꢅ
LYMSO3 PAVAMETEV
COIDꢀTꢀOIL
SoftSpans 7 and 6: 1ꢀ.2ꢁV and 1ꢀV Ranges, f = 2kHz
MꢀI
TYP
MAX
UIꢀTL
l
l
l
l
SINAD
SNR
Signal-to-(Noise +
93.ꢀ
87.6
9ꢀ.ꢀ
8ꢁ.2
96.5
9ꢀ.6
93.2
87.3
dB
dB
dB
dB
IN
Distortion) Ratio
SoftSpans 5 and ꢁ: ꢀV to 1ꢀ.2ꢁV and ꢀV to 1ꢀV Ranges, f = 2kHz
IN
SoftSpans 3 and 2: 5.12V and 5V Ranges, f = 2kHz
IN
SoftSpans 1 and ꢀ: ꢀV to 5.12V and ꢀV to 5V Ranges, f = 2kHz
IN
l
l
l
l
Signal-to-Noise Ratio
SoftSpans 7 and 6: 1ꢀ.2ꢁV and 1ꢀV Ranges, f = 2kHz
93.7
87.7
9ꢀ.2
8ꢁ.3
96.7
9ꢀ.7
93.2
87.3
dB
dB
dB
dB
IN
SoftSpans 5 and ꢁ: ꢀV to 1ꢀ.2ꢁV and ꢀV to 1ꢀV Ranges, f = 2kHz
IN
SoftSpans 3 and 2: 5.12V and 5V Ranges, f = 2kHz
IN
SoftSpans 1 and ꢀ: ꢀV to 5.12V and ꢀV to 5V Ranges, f = 2kHz
IN
l
l
l
l
THD
Total Harmonic Distortion
SoftSpans 7 and 6: 1ꢀ.2ꢁV and 1ꢀV Ranges, f = 2kHz
–1ꢀ9
–111
–113
–11ꢁ
–1ꢀ1
–99
–1ꢀꢁ
–1ꢀ3
dB
dB
dB
dB
IN
SoftSpans 5 and ꢁ: ꢀV to 1ꢀ.2ꢁV and ꢀV to 1ꢀV Ranges, f = 2kHz
IN
SoftSpans 3 and 2: 5.12V and 5V Ranges, f = 2kHz
IN
SoftSpans 1 and ꢀ: ꢀV to 5.12V and ꢀV to 5V Ranges, f = 2kHz
IN
l
l
l
l
SFDR
Spurious Free Dynamic
Range
SoftSpans 7 and 6: 1ꢀ.2ꢁV and 1ꢀV Ranges, f = 2kHz
1ꢀ1
99
1ꢀ5
1ꢀ5
11ꢀ
112
11ꢁ
115
dB
dB
dB
dB
IN
SoftSpans 5 and ꢁ: ꢀV to 1ꢀ.2ꢁV and ꢀV to 1ꢀV Ranges, f = 2kHz
IN
SoftSpans 3 and 2: 5.12V and 5V Ranges, f = 2kHz
IN
SoftSpans 1 and ꢀ: ꢀV to 5.12V and ꢀV to 5V Ranges, f = 2kHz
IN
Channel-to-Channel
Active Crosstalk
Alternating Conversions with 18V 2ꢀꢀHz Sine in 1ꢀ.2ꢁV
–125
dB
P-P
Range, Crosstalk to Any Other Channel
–3dB Input Bandwidth
Aperture Delay
7
1
MHz
ns
Aperture Delay Matching
Aperture Jitter
15ꢀ
3
ps
ps
RMS
Transient Response
Full-Scale Step, ꢀ.ꢀꢀ5% Settling
36ꢀ
ns
inTernal reFerence characTerisTics Thn l dnRotns thn spncxfxcꢂtxoRs whxch ꢂpply ovnr thn full
opnrꢂtxRg tnipnrꢂturn rꢂRgnm othnrwxsn spncxfxcꢂtxoRs ꢂrn ꢂt TA = 0ꢆ°Cꢄ ꢁIotn 9ꢅ
LYMSO3
PAVAMETEV
COIDꢀTꢀOIL
MꢀI
TYP
2.ꢀꢁ8
5
MAX
2.ꢀ53
2ꢀ
UIꢀTL
V
V
REFIN
Internal Reference Output Voltage
Internal Reference Temperature Coefficient
Internal Reference Line Regulation
Internal Reference Output Impedance
REFIN Voltage Range
2.ꢀꢁ3
l
(Note 1ꢁ)
ppm/°C
mV/V
kΩ
V
DD
= ꢁ.75V to 5.25V
ꢀ.1
2ꢀ
V
REFIN Overdriven (Note 7)
1.25
2.2
V
REFIN
233518f
4
For more information www.linear.com/LTC2335-18
LTC2335-18
reFerence buFFer characTerisTics
Thn l dnRotns thn spncxfxcꢂtxoRs whxch ꢂpply ovnr thn full
opnrꢂtxRg tnipnrꢂturn rꢂRgnm othnrwxsn spncxfxcꢂtxoRs ꢂrn ꢂt TA = 0ꢆ°Cꢄ ꢁIotn 9ꢅ
LYMSO3
PAVAMETEV
COIDꢀTꢀOIL
MꢀI
ꢁ.ꢀ91
2.5
TYP
MAX
ꢁ.1ꢀ1
5
UIꢀTL
l
l
V
Reference Buffer Output Voltage REFIN Overdriven, V
= 2.ꢀꢁ8V
REFIN
ꢁ.ꢀ96
V
V
REFBUF
REFBUF Voltage Range
REFBUF Input Impedance
REFBUF Load Current
REFBUF Overdriven (Notes 7, 15)
V
REFIN
= ꢀV, Buffer Disabled
13
kΩ
l
I
V
V
= 5V, (Notes 15, 16)
= 5V, Acquisition or Nap Mode (Note 15)
1.1
ꢀ.39
1.ꢁ
mA
mA
REFBUF
REFBUF
REFBUF
DigiTal inpuTs anD DigiTal ouTpuTs Thn l dnRotns thn spncxfxcꢂtxoRs whxch ꢂpply ovnr thn
full opnrꢂtxRg tnipnrꢂturn rꢂRgnm othnrwxsn spncxfxcꢂtxoRs ꢂrn ꢂt TA = 0ꢆ°Cꢄ ꢁIotn 9ꢅ
LYMSO3
PAVAMETEV
COIDꢀTꢀOIL
MꢀI
0.8 • OV
–1ꢀ
TYP
MAX
UIꢀTL
CMOL Dxgxtꢂl ꢀRputs ꢂRd Outputs
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
IH
IL
DD
0.2 • OV
DD
I
V
IN
= ꢀV to OV
DD
1ꢀ
μA
pF
V
IN
C
V
V
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
5
IN
l
l
l
I
I
= –5ꢀꢀμA
= 5ꢀꢀμA
OV – ꢀ.2
DD
OH
OL
OUT
ꢀ.2
1ꢀ
V
OUT
I
I
I
V
OUT
V
OUT
V
OUT
= ꢀV to OV
= ꢀV
–1ꢀ
μA
mA
mA
OZ
DD
–5ꢀ
5ꢀ
SOURCE
SINK
= OV
DD
32DL Dxgxtꢂl ꢀRputs ꢂRd Outputs
l
l
V
Differential Input Voltage
2ꢀꢀ
9ꢀ
35ꢀ
6ꢀꢀ
125
mV
ID
R
On-Chip Input Termination
Resistance
CS = ꢀV, V
= 1.2V
1ꢀ6
1ꢀ
Ω
MΩ
ID
ICM
DD
CS = OV
l
l
l
l
l
V
Common-Mode Input Voltage
Common-Mode Input Current
Differential Output Voltage
ꢀ.3
–1ꢀ
275
1.1
1.2
2.2
1ꢀ
V
μA
mV
V
ICM
I
V + = V – = ꢀV to OV
IN IN DD
ICM
V
V
R = 1ꢀꢀΩ Differential Termination
L
35ꢀ
1.2
ꢁ25
1.3
1ꢀ
OD
Common-Mode Output Voltage
Hi-Z Output Leakage Current
R = 1ꢀꢀΩ Differential Termination
L
OCM
I
V
OUT
= ꢀV to OV
DD
–1ꢀ
μA
OZ
233518f
5
For more information www.linear.com/LTC2335-18
LTC2335-18
power requireMenTs Thn l dnRotns thn spncxfxcꢂtxoRs whxch ꢂpply ovnr thn full opnrꢂtxRg tnipnrꢂturn
rꢂRgnm othnrwxsn spncxfxcꢂtxoRs ꢂrn ꢂt TA = 0ꢆ°Cꢄ ꢁIotn 9ꢅ
LYMSO3 PAVAMETEV
COIDꢀTꢀOIL
MꢀI
ꢀ
TYP
MAX
38
UIꢀTL
l
l
l
l
V
V
V
V
Supply Voltage
V
V
V
V
CC
EE
Supply Voltage
–16.5
1ꢀ
ꢀ
− V
Supply Voltage Difference
Supply Voltage
38
CC
EE
ꢁ.75
5.ꢀꢀ
5.25
DD
VCC
l
l
l
l
I
Supply Current
1Msps Sample Rate
Acquisition Mode
Nap Mode
3.5
3.8
ꢀ.7
1
ꢁ.3
ꢁ.5
ꢀ.9
15
mA
mA
mA
μA
Power Down Mode
l
l
l
l
I
Supply Current
1Msps Sample Rate
Acquisition Mode
Nap Mode
–5.1
–ꢁ.9
–1.1
–15
–ꢁ.ꢀ
–ꢁ.ꢀ
–ꢀ.8
–1
mA
mA
mA
μA
VEE
Power Down Mode
CMOL ꢀ/O Modn
l
OV
Supply Voltage
Supply Current
1.71
5.25
V
DD
l
l
l
l
l
l
I
1Msps Sample Rate
1Msps Sample Rate, V
Acquisition Mode
Nap Mode
12.6
11.3
1.6
1.ꢁ
65
1ꢁ.5
13.ꢀ
2.1
1.9
175
ꢁ5ꢀ
mA
mA
mA
mA
μA
VDD
= 5V (Note 15)
REFBUF
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
65
µA
l
l
l
I
Supply Current
1Msps Sample Rate (C = 25pF)
2.6
1
1
ꢁ.2
2ꢀ
2ꢀ
mA
μA
μA
OVDD
L
Acquisition or Nap Mode
Power Down Mode
l
l
l
l
l
P
Power Dissipation
1Msps Sample Rate
182
125
3ꢀ
ꢀ.36
ꢀ.36
22ꢁ
152
ꢁꢀ
1.ꢁ
2.8
mW
mW
mW
mW
mW
D
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
32DL ꢀ/O Modn
l
OV
Supply Voltage
Supply Current
2.375
5.25
V
DD
l
l
l
l
l
l
I
1Msps Sample Rate
1ꢁ.8
13.8
3.2
3.ꢀ
65
17.1
15.9
3.8
3.7
175
ꢁ5ꢀ
mA
mA
mA
mA
μA
VDD
1Msps Sample Rate, V
Acquisition Mode
Nap Mode
= 5V (Note 15)
REFBUF
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
65
µA
l
l
l
I
Supply Current
1Msps Sample Rate, (R = 1ꢀꢀΩ)
7
7
1
8.5
8.ꢀ
2ꢀ
mA
mA
μA
OVDD
L
Acquisition or Nap Mode (R = 1ꢀꢀΩ)
L
Power Down Mode
l
l
l
l
l
P
Power Dissipation
1Msps Sample Rate
2ꢀꢁ
151
55
ꢀ.36
ꢀ.36
2ꢁ8
18ꢀ
69
1.ꢁ
2.8
mW
mW
mW
mW
mW
D
Acquisition Mode
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
233518f
6
For more information www.linear.com/LTC2335-18
LTC2335-18
aDc TiMing characTerisTics Thn l dnRotns thn spncxfxcꢂtxoRs whxch ꢂpply ovnr thn full opnrꢂtxRg
tnipnrꢂturn rꢂRgnm othnrwxsn spncxfxcꢂtxoRs ꢂrn ꢂt TA = 0ꢆ°Cꢄ ꢁIotn 9ꢅ
LYMSO3
PAVAMETEV
COIDꢀTꢀOIL
MꢀI
TYP
MAX
UIꢀTL
Msps
μs
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Time Between Conversions
Conversion Time
1
SMPL
CYC
1
ꢁ5ꢀ
ꢁ2ꢀ
ꢁꢀ
5ꢀꢀ
ꢁ8ꢀ
55ꢀ
3ꢀ
ns
CONV
ACQ
Acquisition Time
(t
= t
– t
– t
)
ns
ACQ
CYC
CONV
BUSYLH
CNV High Time
ns
CNVH
CNVL
BUSYLH
QUIET
PDH
CNV Low Time
ꢁ2ꢀ
ns
C = 25pF
L
ns
CNV↑ to BUSY Delay
Digital I/O Quiet Time from CNV↑
PD High Time
2ꢀ
ꢁꢀ
ꢁꢀ
ns
ns
PD Low Time
ns
PDL
REFBUF Wake-Up Time
C
= ꢁ7μF, C
= ꢀ.1μF
2ꢀꢀ
ms
WAKE
REFBUF
REFIN
CMOL ꢀ/O Modn
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
SCKI Period
(Notes 17, 18)
1ꢀ
ꢁ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKI
SCKI High Time
SCKIH
SCKI Low Time
ꢁ
SCKIL
(Note 17)
(Note 17)
2
SDI Setup Time from SCKI↑
SDI Hold Time from SCKI↑
SDO Data Valid Delay from SCKI↑
SDO Remains Valid Delay from SCKI↑
SDO to SCKO Skew
SSDISCKI
HSDISCKI
DSDOSCKI
HSDOSCKI
SKEW
1
C = 25pF (Note 17)
L
7.5
1
C = 25pF (Note 17)
L
1.5
–1
ꢀ
(Note 17)
ꢀ
C = 25pF (Note 17)
L
SDO Data Valid Delay from BUSY↓
Bus Enable Time After CS↓
Bus Relinquish Time After CS↑
DSDOBUSYL
EN
(Note 17)
(Note 17)
15
15
DIS
32DL ꢀ/O Modn
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
SCKI Period
(Note 19)
ꢁ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKI
SCKI High Time
(Note 19)
1.5
1.5
1.2
–ꢀ.2
SCKIH
SCKI Low Time
(Note 19)
SCKIL
SDI Setup Time from SCKI
SDI Hold Time from SCKI
SDO Data Valid Delay from SCKI
SDO Remains Valid Delay from SCKI
SDO to SCKO Skew
(Notes 11, 19)
(Notes 11, 19)
(Notes 11, 19)
(Notes 11, 19)
(Note 11)
SSDISCKI
HSDISCKI
DSDOSCKI
HSDOSCKI
SKEW
6
1
–ꢀ.ꢁ
ꢀ
ꢀ
ꢀ.ꢁ
(Note 11)
SDO Data Valid Delay from BUSY↓
Bus Enable Time After CS↓
Bus Relinquish Time After CS↑
DSDOBUSYL
EN
5ꢀ
15
DIS
233518f
7
For more information www.linear.com/LTC2335-18
LTC2335-18
aDc TiMing characTerisTics
Iotn 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Iotn 11: Guaranteed by design, not subject to test.
Iotn 10: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
the offset voltage measured from –ꢀ.5LSB when the output code flickers
between ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ and 11 1111 1111 1111 1111. Full-
scale error for these SoftSpan ranges is the worst-case deviation of the
first and last code transitions from ideal and includes the effect of offset
error. For unipolar SoftSpan ranges 5, ꢁ, 1, and ꢀ, zero-scale error is
the offset voltage measured from ꢀ.5LSB when the output code flickers
between ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ and ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀ1. Full-
scale error for these SoftSpan ranges is the worst-case deviation of the
last code transition from ideal and includes the effect of offset error.
Iotn 1±: All specifications in dB are referred to a full-scale input in the
relevant SoftSpan input range, except for crosstalk, which is referred to
the crosstalk injection signal amplitude.
Iotn 1.: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Iotn 0: All voltage values are with respect to ground.
Iotn ±: V
is the output of an internal voltage regulator, and should
DDLBYP
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,
as described in the Pin Functions section. Do not connect this pin to any
external circuitry.
Iotn .: When these pin voltages are taken below V or above V , they
EE
CC
will be clamped by internal diodes. This product can handle input currents
of up to 1ꢀꢀmA below V or above V without latch-up.
EE
CC
Iotn ꢆ: When these pin voltages are taken below ground or above V or
DD
OV , they will be clamped by internal diodes. This product can handle
DD
currents of up to 1ꢀꢀmA below ground or above V or OV without
DD
DD
latch-up.
Iotn 1ꢆ: When REFBUF is overdriven, the internal reference buffer must
be disabled by setting REFIN = ꢀV.
Iotn ꢇ: –16.5V ≤ V ≤ ꢀV, ꢀV ≤ V ≤ 38V, 1ꢀV ≤ (V – V ) ≤ 38V,
EE
CC
CC
EE
V
DD
= 5V, unless otherwise specified.
Iotn 1ꢇ: I
varies proportionally with sample rate.
REFBUF
Iotn 7: Recommended operating conditions.
Iotn 17: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V,
DD
DD
Iotn 8: Refer to Absolute Maximum Ratings section for pin voltage limits
related to device reliability.
and OV = 5.25V.
DD
Iotn 18: A t
up to 1ꢀꢀMHz for rising edge capture.
period of 1ꢀns minimum allows a shift clock frequency of
SCKI
Iotn 9: V = 15V, V = –15V, V = 5V, OV = 2.5V, f = 1Msps,
CC
EE
DD
DD
SMPL
internal reference and buffer, true bipolar input signal drive in bipolar
SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless
otherwise specified.
Iotn 19: V = 1.2V, V = 35ꢀmV for LVDS differential input pairs.
ICM
ID
Iotn 1ꢃ: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
CMOL TxixRgs
0.8 • OV
DD
t
t
WIDTH
0.2 • OV
DD
50%
50%
t
DELAY
DELAY
233518 F01a
0.8 • OV
0.2 • OV
0.8 • OV
0.2 • OV
DD
DD
DD
DD
32DL TxixRgs ꢁDxffnrnRtxꢂlꢅ
+200mV
t
WIDTH
–200mV
0V
0V
t
t
DELAY
DELAY
233518 F01b
+200mV
–200mV
+200mV
–200mV
Fxgurn 1ꢄ 2oltꢂgn 3nvnls for TxixRg LpncxfxcꢂtxoRs
233518f
8
For more information www.linear.com/LTC2335-18
LTC2335-18
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
Typical perForMance characTerisTics
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 1Msps, unless otherwise noted.
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
vs Output Code and Range
vs Output Code and Channel
vs Output Code and Channel
2.0
1.5
2.0
1.5
0.5
0.4
±±10.24V RANG
±±10.24V RANG
ALL RANGES
ALL CHANNELS
–
–
+
TRUE BIPOLAR DRIVE (IN = 0V)
FULLY DIFFERENTIAL DRIVE (IN = –IN )
ALL CHANNELS
ALL CHANNELS
0.3
1.0
1.0
0.2
0.5
0.5
0.1
0
0
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
–131072 –65536
0
65536
131072
–131072 –65536
0
65536
131072
0
65536
131072
196608
262144
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
233518 G01
233518 G02
233518 G03
Integral Nonlinearity
vs Output Code and Range
Integral Nonlinearity
vs Output Code and Range
Integral Nonlinearity
vs Output Code and Range
2.0
1.5
2.0
1.5
2.0
1.5
–
–
+
–
UNIPOLAR DRIVE (IN = 0V)
FULLY DIFFERENTIAL DRIVE (IN = –IN )
TRUE BIPOLAR DRIVE (IN = 0V)
ONE CHANNEL
ONE CHANNEL
ONE CHANNEL
1.0
1.0
1.0
±±10.24, ±±14,
±±5.12, AND ±±2
RANGES
0V to 5.12V AND
0V to 5V RANGES
±±5.12V ANV±±2
RANGES
0.5
0.5
0.5
0
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
±±10.24V ANV±±14
RANGES
0V to 10.24V AND
0V to 10V RANGES
0
65536
131072
OUTPUT CODE
196608
262144
–131072 –65536
0
65536
131072
–131072 –65536
0
65536
131072
OUTPUT CODE
OUTPUT CODE
233518 G06
233518 G05
233518 G04
Integral Nonlinearity
vs Output Code
DC Histogram (Zero-Scale)
DC Histogram (Near Full-Scale)
2.0
1.5
90000
80000
70000
60000
50000
40000
30000
20000
10000
0
90000
80000
70000
60000
50000
40000
30000
20000
10000
0
±±10.24V RANG
±±10.24V RANG
±±10.24V RANG
σ = 1.3
σ = 1.4
–
TRUE BIPOLAR DRIVE (IN = 0V)
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ARBITRARY DRIVE
+
–
IN /IN COMMON MODE
SWEPT –10.24V to 10.24V
–131072 –65536
0
65536
131072
–6
–4
–2
0
2
4
6
130971
130974
130977
130980
130983
OUTPUT CODE
CODE
CODE
233518 G07
233518 G08
233518 G09
233518f
9
For more information www.linear.com/LTC2335-18
LTC2335-18
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
Typical perForMance characTerisTics
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 1Msps, unless otherwise noted.
32k Point Arbitrary Two-Tone FFT
fSMPL = 1Msps, IN+ = –7dBFS 2kHz
Sine, IN– = –7dBFS 3.1kHz Sine
32k Point FFT fSMPL = 1Msps,
fIN = 2kHz
32k Point FFT fSMPL = 1Msps,
fIN = 2kHz
0
–20
0
–20
0
–20
±±10.24V RANG
±±10.24V RANG
±±10.24V RANG
ARBITRARY DRIVE
–
–
+
TRUE BIPOLAR DRIVE (IN = 0V)
FULLY DIFFERENTIAL DRIVE (IN = –IN )
–40
–40
–40
SNR = 96.9dB
THD = –109dB
SINAD = 96.7dB
SFDR = 111dB
SNR = 96.7dB
THD = –124dB
SINAD = 96.7dB
SFDR = 119dB
SFDR = 119dB
SNR = 96.7dB
–60
–60
–60
–80
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
100
200
300
400
500
0
100
200
300
400
500
0
100
200
300
400
500
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
233518 G10
233518 G11
233518 G12
32k Point FFT fSMPL = 1Msps,
fIN = 2kHz
SNR, SINAD vs VREFBUF
,
THD, Harm onics vs VREFBUF
,
fIN = 2kHz
fIN = 2kHz
0
–20
100.0
98.0
96.0
94.0
92.0
90.0
–100
–105
–110
–115
–120
–125
–130
±±5.12V RANG
±2.5 • V
RANGE
±2.5 • V
RANGE
REFBUF
REFBUF
–
–
–
TRUE BIPOLAR DRIVE (IN = 0V)
TRUE BIPOLAR DRIVE (IN = 0V)
TRUE BIPOLAR DRIVE (IN = 0V)
–40
SNR = 93.4dB
THD = –118dB
SINAD = 93.4dB
SFDR = 120dB
SNR
THD
–60
SINAD
–80
2ND
–100
–120
–140
–160
–180
3RD
0
100
200
300
400
500
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
FREQUENCY (kHz)
REFBUF VOLTAGE (V)
REFBUF VOLTAGE (V)
233518 G13
233518 G14
233518 G15
SNR, SINAD
vs Input Frequency
THD, Harm onics
THD, Harm onics vs Input
Com m on Mode, fIN = 2kHz
vs Input Frequency
–70
–80
100.0
96.0
92.0
88.0
84.0
80.0
76.0
0
±±10.24V RANG
TRUE BIPOLAR DRIVE (IN = 0V)
±±10.24V RANG
2V FULLY DIFFERENTIAL DRIVE
–
P-P
–20
–40
SNR
–90
–60
SINAD
–100
–110
–120
–130
–80
THD
–100
–120
–140
–160
3RD
THD
2ND
±±10.24V RANG
–
3RD
TRUE BIPOLAR DRIVE (IN = 0V)
2ND
–10
10
100
1k
10k
100k
10
100
1k
10k
100k
–15
–5
0
5
10
15
FREQUENCY (Hz)
FREQUENCY (Hz)
INPUT COMMON MODE (V)
233518 G17
233518 G16
233518 G18
233518f
10
For more information www.linear.com/LTC2335-18
LTC2335-18
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
Typical perForMance characTerisTics
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 1Msps, unless otherwise noted.
SNR, SINAD vs Input Level,
fIN = 2kHz
CMRR vs Input Frequency
and Channel
Crosstalk vs Input Frequency
and Conversion Sequence
98.0
97.5
97.0
96.5
96.0
–60
–70
140
130
120
110
100
90
±±10.24V RANG
TRUE BIPOLAR DRIVE (IN = 0V)
±±10.24V RANG
±±10.24V RANG
–
+
+
–
IN0 = 0V
IN = IN = 18V SINE
P-P
–
+
IN0 = 18V SINE
ALL CHANNELS
P-P
–
+
–
IN1 , IN1 , IN2 , IN2 = 0V
CH0, CH2, CH0, CH2...
CH0, CH1, CH0, CH1...
–80
–90
SNR
–100
–110
–120
–130
–140
–150
SINAD
80
70
CH1, CH1, CH1, CH1...
10k 100k 1M
FREQUENCY (Hz)
60
–40
–30
–20
–10
0
10
100
1k
10
100
1k
10k
100k
1M
INPUT LEVEL (dBFS)
FREQUENCY (Hz)
233518 G19
233518 G21
233518 G20
SNR, SINAD vs Tem perature,
fIN = 2kHz
THD, Harm onics vs Tem perature,
fIN = 2kHz
INL, DNL vs Tem perature
2.0
1.5
–95
–100
–105
–110
–115
–120
–125
99
98
97
96
95
94
93
±±10.24V RANG
±±10.24V RANG
TRUE BIPOLAR DRIVE (IN = 0V)
±±10.24V RANG
–
–
–
TRUE BIPOLAR DRIVE (IN = 0V)
TRUE BIPOLAR DRIVE (IN = 0V)
1.0
MAX INL
0.5
MAX DNL
SNR
THD
0
SINAD
2ND
MIN DNL
–0.5
–1.0
–1.5
–2.0
3RD
MIN INL
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
233518 G24
233518 G23
233518 G22
Positive Full-Scale Error vs
Tem perature and Channel
Negative Full-Scale Error vs
Tem perature and Channel
Zero-Scale Error vs
Tem perature and Channel
0.100
0.075
0.100
0.075
5
4
±±10.24V RANG
ALL CHANNELS
±±10.24 4ꢀRANG
ALL CHANNELS
±±10.24V RANG
ALL CHANNELS
3
0.050
0.050
2
0.025
0.025
1
0.000
0.000
0
–1
–2
–3
–4
–5
–0.025
–0.050
–0.075
–0.100
–0.025
–0.050
–0.075
–0.100
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
233518 G26
233518 G25
233518 G27
233518f
11
For more information www.linear.com/LTC2335-18
LTC2335-18
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
Typical perForMance characTerisTics
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 1Msps, unless otherwise noted.
Power-Down Current
vs Tem perature
PSRR vs Frequency
Supply Current vs Tem perature
18
16
14
12
10
8
150
140
130
120
110
100
90
1000
100
10
+
–
IN = IN = 0V
OV
DD
I
I
VDD
VDD
V
CC
6
V
EE
I
VCC
4
1
2
80
I
0
OVDD
–I
VEE
70
0.1
–2
–4
–6
I
I
VEE
I
VCC
OVDD
60
V
DD
50
0.01
–55 –35 –15
5
25 45 65 85 105 125
10
100
1k
10k
100k
1M
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
FREQUENCY (Hz)
TEMPERATURE (°C)
233518 G28
233518 G30
233518 G29
Offset Error
vs Input Com m on Mode
Internal Reference Output
vs Tem perature
Supply Current vs Sam pling Rate
2.0
1.5
2.051
2.050
2.049
2.048
2.047
2.046
2.045
16
14
12
10
8
±±10.24V RANG
WITH NAP MODE
CNVL
15 UNITS
t
= 500ns
I
VDD
1.0
0.5
V
= 38V, V = 0V
CC
CM
EE
V
= 0V to 34V
6
0
I
4
VCC
–0.5
–1.0
–1.5
–2.0
2
0
I
OVDD
V
V
= 21.5V, V = –16.5V
CC
CM
EE
–2
–4
–6
= –16.5V to 17.5V
I
VEE
–17
0
17
34
–55 –35 –15
5
25 45 65 85 105 125
0
200
400
600
800
1000
INPUT COMMON MODE (V)
TEMPERATURE (°C)
SAMPLING FREQUENCY (kHz)
233518 G31
233518 G32
233518 G33
Step Response
(Large-Signal Settling)
Step Response
(Fine Settling)
250
200
150
100
50
131072
98304
65536
32768
0
±±10.24V RANG
+
IN = 249.99984kHz
SQUARE WAVE
–
IN = 0V
±±10.24V RANG
+
0
IN = 249.99984kHz SQUARE WAVE
–
IN = 0V
–50
–100
–150
–200
–250
–32768
–65536
–98304
–131072
–100
0
100 200 300 400 500 600 700 800 900
–100
0
100 200 300 400 500 600 700 800 900
SETTLING TIME (ns)
SETTLING TIME (ns)
233518 G35
233518 G34
233518f
12
For more information www.linear.com/LTC2335-18
LTC2335-18
pin FuncTions
Pins that are the Sam e for All Digital I/O Modes
buffer may be disabled by grounding its input at REFIN.
With the buffer disabled, overdrive REFBUF with an ex-
ternal reference voltage in the range of 2.5V to 5V. When
using the internal reference buffer, limit the loading of any
external circuitry connected to REFBUF to less than 10µA.
+
+
−
−
IN0 to IN7 , IN0 to IN7 (Pins 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 47, and 48): Positive and Negative
Analog Inputs, Channels 0 to 7. The converter samples
(V + – V –) and digitizes the selected channel. Wide
IN
IN
Using a high input impedance amplifier to buffer V
to any external circuits is recommended.
REFBUF
input common mode range (V ≤ V ≤ V – 4V) and
EE
CM
CC
high common mode rejection allow the inputs to accept
a wide variety of signal swings. Full-scale input range is
determined by the selected SoftSpan configuration.
PD (Pin 22): Power Down Input. When this pin is brought
high, the LTC2335-18 is powered down and subsequent
conversion requests are ignored. If this occurs during a
conversion, the device powers down once the conversion
completes. If this pin is brought high twice without an
intervening conversion, an internal global reset is initi-
ated, equivalent to a power-on-reset event. Logic levels
GND (Pins 15, 18, 20, 25, 30, 36, 41, 44, 46): Ground.
Solder all GND pins to a solid ground plane.
V
(Pin 16): Positive High Voltage Power Supply. The
CC
range of V is 0V to 38V with respect to GND and 10V to
CC
38V with respect to V . Bypass V to GND close to the
are determined by OV .
EE
CC
DD
pin with a 0.1μF ceramic capacitor. In applications where
LVDS/CMOS(Pin23):I/OModeSelect.TiethispintoOV
DD
V
CC
is shorted to GND this capacitor may be omitted.
to select LVDS I/O mode, or to ground to select CMOS I/O
V
(Pins 17, 45): Negative High Voltage Power Supply.
mode. Logic levels are determined by OV .
EE
DD
The range of V is 0V to –16.5V with respect to GND and
EE
CNV (Pin 24): Conversion Start Input. A rising edge on
this pin puts the internal sample-and-holds into the hold
mode and initiates a new conversion. CNV is not gated
by CS, allowing conversions to be initiated independent
of the state of the serial I/O bus.
–10V to –38V with respect to V . Connect Pins 17 and 45
CC
together and bypass the V network to GND close to Pin
EE
17 with a 0.1μF ceramic capacitor. In applications where
V
EE
is shorted to GND this capacitor may be omitted.
REFIN (Pin 19): Bandgap Reference Output/Reference
Buffer Input. An internal bandgap reference nominally
outputs 2.048V on this pin. An internal reference buffer
BUSY (Pin 38): Busy Output. The BUSY signal indicates
that a conversion is in progress. This pin transitions low-
to-high at the start of each conversion and stays high until
the conversion is complete. Logic levels are determined
amplifies V
to create the converter master reference
REFIN
voltage V
= 2 • V
on the REFBUF pin. When
REFBUF
REFIN
by OV .
DD
using the internal reference, bypass REFIN to GND (Pin
20) close to the pin with a 0.1μF ceramic capacitor to filter
the bandgap output noise. If more accuracy is desired,
overdrive REFIN with an external reference in the range
of 1.25V to 2.2V.
V
(Pin40):Internal2.5VRegulatorBypassPin. The
DDLBYP
voltage on this pin is generated via an internal regulator
operating off of V . This pin must be bypassed to GND
DD
close to the pin with a 2.2μF ceramic capacitor. Do not
connect this pin to any external circuitry.
REFBUF (Pin 21): Internal Reference Buffer Output. An
internal reference buffer amplifies V
convertermasterreferencevoltageV
thispin,nominally4.096Vwhenusingtheinternalbandgap
reference. Bypass REFBUF to GND (Pin 20) close to the
pin with a 47μF ceramic capacitor. The internal reference
to create the
=2•V
V
(Pins 42, 43): 5V Power Supply. The range of V
REFIN
REFBUF
DD DD
is 4.75V to 5.25V. Connect Pins 42 and 43 together and
on
REFIN
bypass the V network to GND with a shared 0.1μF
ceramic capacitor close to the pins.
DD
233518f
13
For more information www.linear.com/LTC2335-18
LTC2335-18
pin FuncTions
CMOS I/O Mode
LVDS I/O Mode
+
–
+
+
–
+
–
SDI , SDI , SCKI , SDO , SDO (Pins 26, 27, 28, 34,
and 35): LVDS Inputs and Outputs. In CMOS I/O mode
these pins are Hi-Z.
SDI , SDI (Pins 26 and 27): LVDS Positive and Nega-
+
–
tive Serial Data Input. Differentially drive SDI /SDI with
the desired MUX control words (see Table 1a), latched
+
–
on both the rising and falling edges of SCKI /SCKI . The
SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with
the serial I/O clock. SCKI rising edges latch serial data in
on SDI and clock serial data out on SDO. For standard
SPI bus operation, capture output data at the receiver on
rising edges of SCKI. SCKI is allowed to idle either high
+
–
SDI /SDI input pair is internally terminated with a 100Ω
differential resistor when CS is low.
+
–
SCKI ,SCKI (Pins28and29):LVDSPositiveandNegative
+
–
Serial Clock Input. Differentially drive SCKI /SCKI with
+
–
or low. Logic levels are determined by OV .
the serial I/O clock. SCKI /SCKI rising and falling edges
DD
+
–
latch serial data in on SDI /SDI and clock serial data out
OV (Pin 31): I/O Interface Power Supply. In CMOS I/O
DD
+
–
+
–
on SDO /SDO . Idle SCKI /SCKI low, including when
mode, the range of OV is 1.71V to 5.25V. Bypass OV
DD
DD
+
–
transitioning CS. The SCKI /SCKI input pair is internally
terminatedwitha100ΩdifferentialresistorwhenCSislow.
to GND (Pin 30) close to the pin with a 0.1μF ceramic
capacitor.
OV (Pin 31): I/O Interface Power Supply. In LVDS I/O
DD
SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising
edgestriggertransitionsonSCKOthatareskew-matchedto
the serial output data stream on SDO. The resulting SCKO
frequency is half that of SCKI. Rising and falling edges of
SCKO may be used to capture SDO data at the receiver
(FPGA) in double data rate (DDR) fashion. For standard
SPI bus operation, SCKO is not used and should be left
unconnected. SCKO is forced low at the falling edge of
mode, therangeofOV is2.375Vto5.25V. BypassOV
DD
DD
to GND (Pin 30) close to the pin with a 0.1μF ceramic
capacitor.
+
–
SCKO , SCKO (Pins 32 and 33): LVDS Positive and
+
–
Negative Serial Clock Output. SCKO /SCKO outputs a
+
–
copy of the input serial I/O clock received on SCKI /SCKI ,
+
skew-matchedwiththeserialoutputdatastreamonSDO /
–
+
–
BUSY. Logic levels are determined by OV .
SDO . Use the rising and falling edges of SCKO /SCKO
DD
+
–
to capture SDO /SDO data at the receiver (FPGA). The
SDO (Pin 33): CMOS Serial Data Output. The most recent
conversionresultalongwithchannelconfigurationinforma-
tion is clocked out onto the SDO pin on each rising edge
of SCKI. Output data formatting is described in the Digital
+
–
SCKO /SCKO outputpairmustbedifferentiallyterminated
with a 100Ω resistor at the receiver (FPGA).
+
–
SDO , SDO (Pins 34 and 35): LVDS Positive and Nega-
tive Serial Data Output. The most recent conversion result
alongwithchannelconfigurationinformationisclockedout
Interface section. Logic levels are determined by OV .
DD
SDI (Pin 37): CMOS Serial Data Input. Drive this pin with
the desired MUX control words (see Table 1a), latched
on the rising edges of SCKI. Hold SDI low while clock-
ing SCKI to configure the next conversion according to
the previously programmed sequence. Logic levels are
+
–
+
ontoSDO /SDO onbothrisingandfallingedgesofSCKI /
SCKI . The SDO /SDO output pair must be differentially
terminated with a 100Ω resistor at the receiver (FPGA).
–
+
–
SDI (Pin 37): CMOS Serial Data Input. In LVDS I/O mode
this pin is Hi-Z.
determined by OV .
DD
CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI.
CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low, and is disabled and Hi-Z when
+
CS is high. CS also gates the external shift clock, SCKI /
–
Logic levels are determined by OV .
SCKI .Theinternal100Ωdifferentialterminationresistors
DD
+
–
+
–
ontheSCKI /SCKI andSDI /SDI inputpairsaredisabled
when CS is high. Logic levels are determined by OV .
DD
233518f
14
For more information www.linear.com/LTC2335-18
LTC2335-18
conFiguraTion Tables
Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Binary SoftSpan Codes SS[2:0] Based on Desired
Analog Input Range. Com bine MUX Word Header (10) with Binary Channel Num ber and SoftSpan Code to Form MUX Control Word
C[7:0]. Use Serial Interface to Program LTC2335-18 Sequencer as Shown in Figures 17 to 20
BINARY SoftSpan CODE
SS[2:0]
BINARY FORMAT OF
CONVERSION RESULT
ANALOG INPUT RANGE
FULL SCALE RANGE
111
110
101
100
011
010
001
000
±2.5 • V
5 • V
Two’s Complement
Two’s Complement
Straight Binary
REFBUF
REFBUF
±2.5 • V
/1.024
5 • V
/1.024
REFBUF
REFBUF
0V to 2.5 • V
2.5 • V
REFBUF
REFBUF
0V to 2.5 • V
/1.024
2.5 • V
/1.024
REFBUF
Straight Binary
REFBUF
±1.25 • V
2.5 • V
Two’s Complement
Two’s Complement
Straight Binary
REFBUF
REFBUF
±1.25 • V
/1.024
2.5 • V
/1.024
REFBUF
REFBUF
0V to 1.25 • V
1.25 • V
REFBUF
REFBUF
0V to 1.25 • V
/1.024
1.25 • V
/1.024
REFBUF
Straight Binary
REFBUF
Table 1b. Reference Configuration Table. The LTC2335-18 Supports Three Reference Configurations. Analog Input Range Scales with
the Converter Master Reference Voltage, VREFBUF
BINARY SoftSpan CODE
REFERENCE CONFIGURATION
V
REFIN
V
ANALOG INPUT RANGE
REFBUF
SS[2:0]
111
110
101
100
011
010
001
000
111
110
101
100
011
010
001
000
111
110
101
100
011
010
001
000
10.24V
10V
0V to 10.24V
0V to 10V
5.12V
Internal Reference with
Internal Buffer
2.048V
4.096V
5V
0V to 5.12V
0V to 5V
6.25V
6.104V
0V to 6.25V
0V to 6.104V
3.125V
1.25V
(Min Value)
2.5V
3.052V
0V to 3.125V
0V to 3.052V
11V
Ex ternal Reference with
Internal Buffer
(REFIN Pin Ex ternally
Overdriven)
10.742V
0V to 11V
0V to 10.742V
5.5V
2.2V
(Max Value)
4.4V
5.371V
0V to 5.5V
0V to 5.371V
233518f
15
For more information www.linear.com/LTC2335-18
LTC2335-18
conFiguraTion Tables
Table 1b. Reference Configuration Table (Continued). The LTC2335-18 Supports Three Reference Configurations. Analog Input Range
Scales with the Converter Master Reference Voltage, VREFBUF
BINARY SoftSpan CODE
REFERENCE CONFIGURATION
V
REFIN
V
ANALOG INPUT RANGE
REFBUF
SS[2:0]
111
110
101
100
011
010
001
000
111
110
101
100
011
010
001
000
6.25V
6.104V
0V to 6.25V
0V to 6.104V
3.125V
2.5V
0V
(Min Value)
3.052V
Ex ternal Reference
Unbuffered
0V to 3.125V
0V to 3.052V
12.5V
(REFBUF Pin
Ex ternally Overdriven,
REFIN Pin Grounded)
12.207V
0V to 12.5V
0V to 12.207V
6.25V
5V
0V
(Max Value)
6.104V
0V to 6.25V
0V to 6.104V
233518f
16
For more information www.linear.com/LTC2335-18
LTC2335-18
FuncTional block DiagraM
CMOS I/O Mode
V
CC
V
V
OV
DD
DD
DDLBYP
LTC2335-18
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
IN0
IN0
IN1
IN1
IN2
IN2
IN3
IN3
IN4
IN4
IN5
IN5
IN6
IN6
IN7
IN7
2.5V
REGULATOR
SDO
SCKO
SDI
SEQUENCER
CMOS
SERIAL
I/O
SCKI
CS
INTERFACE
18-BIT
SAMPLING
ADC
18 BITS
REFERENCE
BUFFER
20k
BUSY
CONTROL
LOGIC
2.048V
REFERENCE
2×
V
EE
GND
REFIN
REFBUF
CNV PD LVDS/CMOS
233518 BD01
LVDS I/O Mode
V
CC
V
V
OV
DD
DD
DDLBYP
LTC2335-18
+
IN0
IN0
IN1
IN1
IN2
IN2
IN3
IN3
IN4
IN4
IN5
IN5
IN6
IN6
IN7
IN7
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
SDO
SDO
SCKO
SCKO
SDI
2.5V
REGULATOR
SEQUENCER
LVDS
SERIAL
I/O
SDI
INTERFACE
SCKI
SCKI
18-BIT
SAMPLING
ADC
18 BITS
CS
REFERENCE
BUFFER
20k
BUSY
CONTROL
LOGIC
2.048V
REFERENCE
2×
V
EE
GND
REFIN
REFBUF
CNV PD LVDS/CMOS
233518 BD02
233518f
17
For more information www.linear.com/LTC2335-18
LTC2335-18
TiMing DiagraM
CMOS I/O Mode
CS = PD = 0
SAMPLE N
CNV
SAMPLE N + 1
BUSY
CONVERT
ACQUIRE
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
SCKI
SDI
DON’T CARE
C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0
CONTROL WORD FOR
CONVERSION N + 1
CONTROL WORD FOR
CONVERSION N + 2
SCKO
SDO
DON’T CARE
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CH2 CH1 CH0 SS2 SS1 SS0 D17
CONVERSION RESULT
(REPETITION)
CONVERSION RESULT
CONVERSION N
CHANNEL ID
SoftSpan
233518 TD01
LVDS I/O Mode
CS = PD = 0
SAMPLE N
SAMPLE N + 1
CNV
(CMOS)
BUSY
(CMOS)
CONVERT
ACQUIRE
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
SCKI
(LVDS)
SDI
(LVDS)
DON’T CARE
C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0
CONTROL WORD FOR
CONVERSION N + 1
CONTROL WORD FOR
CONVERSION N + 2
SCKO
(LVDS)
SDO
(LVDS)
DON’T CARE
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CH2 CH1 CH0 SS2 SS1 SS0 D17
CONVERSION RESULT
(REPETITION)
CONVERSION RESULT
CONVERSION N
CHANNEL ID
SoftSpan
233518 TD02
233518f
18
For more information www.linear.com/LTC2335-18
LTC2335-18
applicaTions inForMaTion
OVERVIEW
an 18-bit charge redistribution capacitor D/A converter
(CDAC). TheCDACissequencedthroughasuccessiveap-
proximationalgorithm,effectivelycomparingthesampled
input voltage with binary-weighted fractions of the chan-
The LTC2335-18 is an 18-bit, low noise 8-channel multi-
plexedsuccessiveapproximationregister(SAR)ADCwith
differential, wide common mode range inputs. The ADC
operates from a 5V low voltage supply and flexible high
voltage supplies, nominally 15V. Using the integrated
nel’s SoftSpan full-scale range (e.g., V /2, V /4 …
FSR
FSR
V
FSR
/262144) using a differential comparator. At the end
of this process, the CDAC output approximates the chan-
nel’s sampled analog input. The ADC control logic then
prepares the 18-bit digital output code for serial transfer.
low-driftreferenceandbuffer(V
=4.096Vnominal),
REFBUF
this SoftSpan ADC can be configured on a conversion-by-
conversionbasistoaccept 10.24V,0Vto10.24V, 5.12V,
or 0V to 5.12V signals on any channel. Alternately, the
ADC may be programmed to cycle through a sequence of
channelsandrangeswithoutfurtheruserintervention.The
input signal range may be expanded up to 12.5V using
an external 5V reference.
TRANSFER FUNCTION
The LTC2335-18 digitizes the full-scale voltage range into
18
2
levels. In conjunction with the ADC master reference
voltage, V
, the selected SoftSpan configuration
REFBUF
The wide input common mode range and high CMRR
(118dB typical, V + = V – = 18V 200Hz Sine) of the
determines its input voltage range, full-scale range, LSB
size, and the binary format of its conversion result, as
shown in Tables 1a and 1b. For example, employing the
IN
IN
P-P
LTC2335-18analoginputsallowtheADCtodirectlydigitize
a variety of signals, simplifying signal chain design. The
absolute common mode input range is determined by
the choice of high voltage supplies, which may be biased
asymmetrically around ground and include the ability for
either the positive or negative supply to be tied directly to
ground. This input signal flexibility, combined with 3LSB
INL, no missing codes at 18-bits, and 96.7dB SNR, makes
the LTC2335-18 an ideal choice for many high voltage
applications requiring wide dynamic range.
internal reference and buffer (V
= 4.096V nominal),
REFBUF
SoftSpan 7 configures a channel to accept a 10.24V
bipolar analog input voltage range, which corresponds
to a 20.48V full-scale range with a 78.125μV LSB. Other
SoftSpan configurations and reference voltages may be
employed to convert both larger and smaller bipolar and
unipolar input ranges. Conversion results are output in
two’s complement binary format for all bipolar SoftSpan
ranges, and in straight binary format for all unipolar
SoftSpan ranges. The ideal two’s complement transfer
function is shown in Figure 2, while the ideal straight
binary transfer function is shown in Figure 3.
TheLTC2335-18supportspin-selectableSPICMOS(1.8V
to 5V) and LVDS serial interfaces, enabling it to communi-
cateequallywellwithlegacymicrocontrollersandmodern
FPGAs.TheLTC2335-18typicallydissipates180mWwhen
converting at 1Msps throughput. Optional nap and power
down modes may be employed to further reduce power
consumption during inactive periods.
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
CONVERTER OPERATION
The LTC2335-18 operates in two phases. During the ac-
quisition phase, the sampling capacitors in each channel
connect to their respective analog input pins and track
100...001
100...000
FSR = +FS – –FS
1LSB = FSR/262144
the differential analog input voltage (V + – V –). A ris-
IN
IN
–1 0V
ing edge on the CNV pin transitions the S/H circuits from
track mode to hold mode, sampling the input signals and
initiating a conversion. During the conversion phase, the
selected channel's sampling capacitors are connected to
1
LSB
–FSR/2
FSR/2 – 1LSB
LSB
INPUT VOLTAGE (V)
233518 F02
Figure 2. LTC2335-18 Two’s Com plem ent Transfer Function
233518f
19
For more information www.linear.com/LTC2335-18
LTC2335-18
applicaTions inForMaTion
the sampling switches, each of which has approximately
111...111
111...110
600Ω (R ) of on-resistance. This behavior occurs on all
IN
channels, so that the LTC2335-18 may respond instantly
to user-requested changes in multiplexer configuration
with no additional settling time required.
100...001
100...000
UNIPOLAR
ZERO
011...111
011...110
V
CC
C
IN
000...001
000...000
R
IN
FSR = +FS
40pF
600Ω
1LSB = FSR/262144
+
–
IN
IN
0V
FSR – 1LSB
V
EE
INPUT VOLTAGE (V)
233518 F03
BIAS
VOLTAGE
V
CC
C
IN
Figure 3. LTC2335-18 Straight Binary Transfer Function
R
IN
40pF
600Ω
233518 F04
ANALOG INPUTS
V
EE
The LTC2335-18 samples the voltage difference (V + –
IN
IN
Figure 4. Equivalent Circuit for Differential Analog Inputs,
Single Channel Shown
V –) between its analog input pins over a wide common
mode input range while attenuating unwanted signals
common to both input pins by the common-mode rejec-
tion ratio (CMRR) of the ADC. Wide common mode input
The initial voltage on both capacitors of the just-converted
channelwillbeapproximatelythesampledcommonmode
voltage (V + + V –)/2 from the previous conversion.
+
–
range coupled with high CMRR allows the IN /IN analog
inputs to swing with an arbitrary relationship to each
IN
IN
Other channels’ capacitors will retain approximately the
other, provided each pin remains between (V – 4V)
CC
+
–
voltage of their respective IN /IN pin at the beginning of
the previous conversion. The external circuitry connected
and V . This unique feature of the LTC2335-18 enables
EE
it to accept a wide variety of signal swings, including
traditionalclassesofanaloginputsignalssuchaspseudo-
differentialunipolar, pseudo-differentialtruebipolar, and
fully differential, simplifying signal chain design.
+
–
to IN and IN must source or sink the charge that flows
through R as the sampling capacitors settle from their
IN
initial voltages to the new input pin voltages over the
course of the acquisition interval. During conversion, nap,
and power down modes, the analog inputs draw only a
small leakage current. The diodes at the inputs provide
ESD protection.
The wide operating range of the high voltage supplies
offers further input common mode flexibility. As long as
the voltage difference limits of 10V ≤ V – V ≤ 38V
CC
EE
are observed, V and V may be independently biased
CC
EE
anywhere within their own individual allowed operating
ranges, including the ability for either of the supplies to be
tied directly to ground. This feature enables the common
mode input range of the LTC2335-18 to be tailored to the
specific application’s requirements.
Bipolar SoftSpan Input Ranges
For conversions configured in SoftSpan ranges 7, 6, 3,
or 2, the LTC2335-18 digitizes the differential analog
input voltage (V + – V –) over a bipolar span of
IN
IN
REFBUF
±2.5 • V
, ±2.5 • V
/1.024, ±1.25 • V
, or
REFBUF
REFBUF
In all SoftSpan ranges, each channel’s analog inputs can
be modeled by the equivalent circuit shown in Figure 4.
At the start of acquisition, the 40pF sampling capacitors
±1.25 • V
/1.024, respectively, as shown in Table
REFBUF
1a. These SoftSpan ranges are useful for digitizing input
+
–
signals where IN and IN swing above and below each
+
–
(C ) connect to the analog input pins IN /IN through
IN
233518f
20
For more information www.linear.com/LTC2335-18
LTC2335-18
applicaTions inForMaTion
24ns implies an 18-bit settling time to a full-scale step of
other. Traditional examples include fully differential input
+
–
approximately13•(R • C )=312ns.Theimpedanceand
signals, where IN and IN are driven 180 degrees out-of-
phasewithrespecttoeachothercenteredaroundacommon
IN IN
self-settling of external circuitry connected to the analog
input pins will increase the overall settling time required.
Low impedance sources can directly drive the inputs of
the LTC2335-18 without gain error, but high impedance
sources should be buffered to ensure sufficient settling
during acquisition and to optimize the linearity and distor-
tion performance of the ADC. Settling time is an important
considerationevenforDCinputsignals, asthevoltageson
the sampling capacitors will differ from the analog input
pin voltages at the start of acquisition.
modevoltage(V ++V –)/2,andpseudo-differentialtrue
IN
IN
+
bipolar input signals, where IN swings above and below
–
a ground reference level, driven on IN . Regardless of the
chosen SoftSpan range, the wide common mode input
+
–
range and high CMRR of the IN /IN analog inputs allow
them to swing with an arbitrary relationship to each other,
provided each pin remains between (V – 4V) and V .
CC
EE
The output data format for all bipolar SoftSpan ranges is
two’s complement.
Mostapplicationsshoulduseabufferamplifiertodrivethe
analog inputs of the LTC2335-18. The amplifier provides
low output impedance, enabling fast settling of the analog
signal during the acquisition phase. It also provides isola-
tion between the signal source and the charge flow at the
analog inputs when entering acquisition.
Unipolar SoftSpan Input Ranges
For conversions configured in SoftSpan ranges 5, 4, 1,
or 0, the LTC2335-18 digitizes the differential analog
input voltage (V + – V –) over a unipolar span of 0V
IN
IN
to 2.5 • V
REFBUF
, 0V to 2.5 • V
, or 0V to 1.25 • V
shown in Table 1a. These SoftSpan ranges are useful for
/1.024, 0V to 1.25 •
REFBUF
REFBUF
V
/1.024, respectively, as
REFBUF
Input Filtering
+
–
digitizing input signals where IN remains above IN . A
traditional example includes pseudo-differential unipolar
The noise and distortion of an input buffer amplifier and
other supporting circuitry must be considered since they
add to the ADC noise and distortion. Noisy input signals
should be filtered prior to the buffer amplifier with a low-
bandwidth filter to minimize noise. The simple one-pole
RC lowpass filter shown in Figure 5 is sufficient for many
applications.
+
input signals, where IN swings above a ground reference
–
level, driven on IN . Regardless of the chosen SoftSpan
range, the wide common mode input range and high
+
–
CMRR of the IN /IN analog inputs allow them to swing
with an arbitrary relationship to each other, provided each
pin remains between (V – 4V) and V . The output data
format for all unipolar SoftSpan ranges is straight binary.
CC
EE
At the output of the buffer, a lowpass RC filter network
formed by the 600Ω sampling switch on-resistance (R )
IN
and the 40pF sampling capacitance (C ) limits the input
IN
INPUT DRIVE CIRCUITS
bandwidth on each channel to 7MHz, which is fast enough
to allow for sufficient transient settling during acquisition
while simultaneously filtering driver wideband noise.
A buffer amplifier with low noise density should be se-
lected to minimize SNR degradation over this bandwidth.
An additional filter network may be placed between the
buffer output and ADC input to further minimize the noise
The initial voltage on each channel’s sampling capacitors
at the start of acquisition must settle to the new input
pin voltages during the acquisition interval. The external
+
–
circuitry connected to IN and IN must source or sink
the charge that flows through R as this settling occurs.
IN
The LTC2335-18 sampling network RC time constant of
233518f
21
For more information www.linear.com/LTC2335-18
LTC2335-18
applicaTions inForMaTion
TRUE BIPOLAR
INPUT SIGNAL
LOWPASS
SIGNAL FILTER
160Ω
BUFFER
0V
AMPLIFIER
+
–
IN0
IN0
10nF
LTC2335-18
BW = 100kHz
ONLY CHANNEL 0 SHOWN FOR CLARITY
233518 F05
Figure 5. True Bipolar Signal Chain with Input Filtering
contribution of the buffer. A simple one-pole lowpass RC
filter is sufficient for many applications.
a wide variety of signal swings, simplifying signal chain
+
design. In many applications, connecting a channel’s IN
–
and IN pins directly to the existing signal chain circuitry
This filter interacts with the buffer amplifier and slows
input settling. It is important that the inputs settle to
will not allow the channel’s sampling network to settle to
18-bitresolutionwithintheADCacquisitiontime(t ). In
ACQ
18-bit resolution within the ADC acquisition time (t ),
ACQ
thesecases,itisrecommendedthattwounity-gainbuffers
be inserted between the signal source and the ADC input
pins, as shown in Figure 6a. Table 2 lists several amplifier
and lowpass filter combinations recommended for use in
this circuit.
asinsufficientsettlingcanlimitINLandTHDperformance.
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion.
NPO/COG and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self-heating and from damage
thatmayoccurduringsoldering. Metalfilmsurfacemount
resistors are much less susceptible to both problems.
The LT1358 combines fast settling, high linearity, and low
input-referrednoisedensity,allowingittoapproachthefull
ADC data sheet SNR and THD specifications when used
withalowpassfilter,asshownintheFFTplotsinFigures6b
to 6e. It may be used without a filter at a loss of 0.3dB
SNR due to wideband noise. The LT1469 achieves the full
ADC specifications for DC precision, THD, and linearity,
at a cost of 0.8dB in SNR. Finally, the LT1355 provides a
good general-purpose combination of THD and SNR at a
lower power. Neither the LT1469 nor LT1355 can afford
the slowing effect of a lowpass filter if they are to be used
Buffering Arbitrary and Fully Differential Analog Input
Signals
The wide common mode input range and high CMRR of
+
–
the LTC2335-18 allow each channel’s IN and IN pins
to swing with an arbitrary relationship to each other,
provided each pin remains between (V – 4V) and V .
CC
EE
ThisuniquefeatureoftheLTC2335-18enablesittoaccept
at the minimum t
of 420ns.
ACQ
Table 2. Recom m ended Am plifier and Filter Com binations for the Buffer Circuits in Figures 6a and 9. AC Perform ance Measured
Using Circuit in Figure 6a, ±10.24V Range
R
C
SNR
(dB)
THD
(dB)
SINAD
(dB)
SFDR
(dB)
FILT
FILT
AMPLIFIER
INPUT SIGNAL DRIVE
(Ω)
100
0
(pF)
270
0
½ LT1358
½ LT1469
½ LT1358
½ LT1358
½ LT1469
½ LT1355
FULLY DIFFERENTIAL
FULLY DIFFERENTIAL
TRUE BIPOLAR
96.8
96.0
96.8
96.5
96.0
96.2
−120
−124
−107
−108
−109
−106
96.8
96.0
96.4
96.2
95.8
95.9
120
120
108
110
110
109
100
0
270
0
TRUE BIPOLAR
0
0
TRUE BIPOLAR
0
0
TRUE BIPOLAR
233518f
22
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LTC2335-18
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15V
OPTIONAL
FULLY
DIFFERENTIAL
+5V
15V
LOWPASS FILTERS
–
ARBITRARY
+10V
0.1µF
R
FILT
AMPLIFIER
+
0V
0V
+
V
C
C
+
–
IN
IN
CC
FILT
FILT
IN0
IN0
–10V
–5V
LTC2335-18
–
UNIPOLAR
TRUE BIPOLAR
+10V
+
+10V
V
REFBUF
47µF
REFIN
0.1µF
AMPLIFIER
EE
0V
R
FILT
0V
–
0.1µF
–15V
–10V
–10V
–15V
ONLY CHANNEL 0 SHOWN FOR CLARITY
233518 F06a
Figure 6a. Buffering Arbitrary, Fully Differential, True Bipolar, and Unipolar Signals.
See Table 2 for Recom m ended Am plifier and Filter Com binations
Arbitrary Drive
Fully Differential Drive
0
–20
0
–20
±±10.24V RANG
±±10.24V RANG
SFDR = 118dB
SNR = 97.0dB
SNR = 96.8dB
THD = –120dB
SINAD = 96.8dB
SFDR = 120dB
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
100
200
300
400
500
0
100
200
300
400
500
FREQUENCY (kHz)
FREQUENCY (kHz)
233518 F06b
233518 F06c
Figure 6b. Two-Tone Test. IN+ = –7dBFS 2kHz Sine, IN– = –7dBFS
3.1kHz Sine, 32k Point FFT, fSMPL = 1Msps. Circuit Shown in
Figure 6a with LT1358 Am plifiers, RFILT = 100Ω, CFILT = 270pF
Figure 6c. IN+/IN– = –1dBFS 2kHz Fully Differential Sine, VCM = 0V,
32k Point FFT, fSMPL = 1Msps. Circuit Shown in Figure 6a with
LT1358 Am plifiers, RFILT = 100Ω, CFILT = 270pF
True Bipolar Drive
Unipolar Drive
0
0
±±10.24V RANG
0V to 10.24V RANGE
–20
–20
SNR = 91.0dB
SNR = 96.8dB
THD = –107dB
SINAD = 96.4dB
SFDR = 108dB
–40
–40
–60
THD = –111dB
SINAD = 91.0dB
SFDR = 111dB
–60
–80
–100
–120
–140
–160
–180
–80
–100
–120
–140
–160
–180
0
100
200
300
400
500
0
100
200
300
400
500
FREQUENCY (kHz)
FREQUENCY (kHz)
233518 F06d
233518 F06e
Figure 6d. IN+ = –1dBFS 2kHz True Bipolar Sine, IN– = 0V, 32k
Point FFT, fSMPL = 1Msps. Circuit Shown in Figure 6a with LT1358
Am plifiers, RFILT = 100Ω, CFILT = 270pF
Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN– = 0V, 32k Point
FFT, fSMPL = 1Msps. Circuit Shown in Figure 6a with LT1358
Am plifiers, RFILT = 100Ω, CFILT = 270pF
233518f
23
For more information www.linear.com/LTC2335-18
LTC2335-18
applicaTions inForMaTion
The two-tone test shown in Figure 6b demonstrates the
many sensors produce a differential sensor voltage riding
on top of a large common mode signal. Figure 7a depicts
one way of using the LTC2335-18 to digitize signals of
this type. The amplifier stage provides a differential gain
of approximately 10V/V to the desired sensor signal while
the unwanted common mode signal is attenuated by the
ADCCMRR.Thecircuitemploysthe 5VSoftSpanrangeof
the ADC. Figure 7b shows measured CMRR performance
of this solution, which is competitive with the best com-
mercially available instrumentation amplifiers. Figure 7c
shows measured AC performance of this solution.
arbitraryinputdrivecapabilityoftheLTC2335-18.Thistest
+
simultaneouslydrivesIN witha−7dBFS2kHzsingle-ended
−
sinewaveandIN witha−7dBFS3.1kHzsingle-endedsine
wave. Together, these signals sweep the analog inputs
across a wide range of common mode and differential
mode voltage combinations, similar to the more general
arbitrary input signal case. They also have a simple spec-
tral representation. An ideal differential converter with no
common-mode sensitivity will digitize this signal as two
−7dBFS spectral tones, one at each sine wave frequency.
The FFT plot in Figure 6b demonstrates the LTC2335-18
response, which approaches this ideal with 118dB of
SFDR limited by the converter's second harmonic distor-
In Figure 8, another application circuit is shown which
uses two channels of the LTC2335-18 to sense the volt-
age on and bidirectional current through a sense resistor
over a wide common mode range. In many applications
of this type, the impedance of the external circuitry is low
enough that the ADC sampling network can fully settle
without buffering.
–
tion response to the 3.1kHz sine wave on IN .
The ability of the LTC2335-18 to accept arbitrary signal
swings over a wide input common mode range with high
CMRR can simplify application solutions. In practice,
31V
+
½ LT1124
+
IN
ARBITRARY
LOWPASS FILTERS
31V
–
18pF
49.9Ω
24V
0.1µF
2.49k
6.6nF
6.6nF
V
+
–
CC
COMMON MODE
INPUT RANGE
IN0
IN0
549Ω
2.49k
LTC2335-18
DIFFERENTIAL MODE
INPUT RANGE: 500ꢀV
18pF
49.9Ω
V
REFBUF
47µF
REFIN
EE
0V
–
+
0.1µF
0.1µF
–5V
BW ~ 500kHz
–
IN
½ LT1124
–5V
ONLY CHANNEL 0 SHOWN FOR CLARITY
233518 F07a
Figure 7a. Digitize Differential Signals Over a Wide Com m on Mode Range
233518f
24
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LTC2335-18
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120
15V
±±5V RANG
110
100
90
0.1µF
V
CC
+
–
IN0
IN0
V
S1
LTC2335-18
80
+
+
–
IN1
IN1
IN = IN = 24V SINE
R
SENSE
I
SENSE
P-P
–
OP AMPS SLEW f > 30kHz
IN
70
60
50
V
REFBUF
47µF
REFIN
EE
+
–
V
S2
IN = IN = 1V SINE
0.1µF
P-P
0.1µF
–15V
233518 F08
10
100
1k
10k
100k
FREQUENCY (Hz)
ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY
– V –10.24V ≤ V ≤ 10.24V
233518 F07b
V
S1
S2
S1
I
=
Figure 7b. CMRR vs Input Frequency. Circuit Shown in Figure 7a
SENSE
R
–10.24V ≤ V ≤ 10.24V
SENSE
S2
Figure 8. Sense Voltage (CH0) and Current (CH1)
Over a Wide Com m on Mode Range
0
±±5V RANG
FULLYVDIFFG GATIRLVD I5GV(IA V=V+IA )
–
+
–20
–40
Buffering Single-Ended Analog Input Signals
SNR = 90.0dB
THD = –113dB
SINAD = 90.0dB
SFDR = 117dB
–60
While the circuit shown in Figure 6a is capable of buffering
single-ended input signals, the circuit shown in Figure 9 is
preferable when the single-ended signal reference level is
inherently low impedance and doesn't require buffering.
Thiscircuiteliminatesonedriverandlowpassfilter,reduc-
ing part count, power dissipation, and SNR degradation
due to driver noise. Using the recommended driver and
filter combinations in Table 2, the performance of this
circuit with single-ended input signals is on par with the
performance of the circuit in Figure 6a.
–80
–100
–120
–140
–160
–180
0
20
40
60
80
100
FREQUENCY (kHz)
233518 F07c
Figure 7c. IN+/IN– = 450m V 2kHz Fully Differential Sine,
0V ≤ VCM ≤ 24V, 32k Point FFT, fSMPL = 200ksps. Circuit
Shown in Figure 7a
TRUE BIPOLAR
+10V
15V
OPTIONAL
LOWPASS FILTER
15V
+
–
+
IN
IN
0V
0.1µF
R
FILT
AMPLIFIER
–10V
V
CC
–
+
–
C
FILT
IN0
IN0
–15V
UNIPOLAR
+10V
LTC2335-18
0V
V
REFBUF
47µF
REFIN
EE
–10V
0.1µF
0.1µF
–15V
ONLY CHANNEL 0 SHOWN FOR CLARITY
233518 F09
Figure 9. Buffering Single-Ended Input Signals. See Table 2 For Recom m ended Am plifier and Filter Com binations
233518f
25
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LTC2335-18
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ADC REFERENCE
LTC2335-18
REFIN
AsshownpreviouslyinTable1b,theLTC2335-18supports
three reference configurations. The first uses both the in-
ternalbandgapreferenceandreferencebuffer.Thesecond
externally overdrives the internal reference but retains the
internal buffer, which isolates the external reference from
ADC conversion transients. This configuration is ideal
for sharing a single precision external reference across
multiple ADCs. The third disables the internal buffer and
overdrives the REFBUF pin externally.
20k
BANDGAP
REFERENCE
0.1µF
REFBUF
REFERENCE
BUFFER
6.5k
47µF
6.5k
GND
233518 F10a
Internal Reference with Internal Buffer
Figure 10a. Internal Reference with Internal Buffer Configuration
The LTC2335-18 has an on-chip, low noise, low drift
(20ppm/°C maximum), temperature compensated band-
gap reference that is factory trimmed to 2.048V. The
reference output connects through a 20kΩ resistor to
the REFIN pin, which serves as the input to the on-chip
referencebuffer, asshowninFigure10a. Whenemploying
the internal bandgap reference, the REFIN pin should be
bypassed to GND (Pin 20) close to the pin with a 0.1μF
ceramic capacitor to filter wideband noise. The reference
Ex ternal Reference with Internal Buffer
If more accuracy and/or lower drift is desired, REFIN can
be easily overdriven by an external reference since 20kΩ
of resistance separates the internal bandgap reference
output from the REFIN pin, as shown in Figure 10b. The
valid range of external reference voltage overdrive on the
REFIN pin is 1.25V to 2.2V, resulting in converter mas-
buffer amplifies V
to create the converter master
ter reference voltages V
between 2.5V and 4.4V,
REFIN
REFBUF
reference voltage V
= 2 • V
on the REFBUF pin,
respectively. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
manyapplications.Withitssmallsize,lowpower,andhigh
accuracy,theLTC6655-2.048iswellsuitedforusewiththe
LTC2335-18 when overdriving the internal reference. The
LTC6655-2.048offers0.025%(maximum)initialaccuracy
REFBUF
REFIN
nominally 4.096V when using the internal bandgap refer-
ence. BypassREFBUFtoGND(Pin20)closetothepinwith
at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or
X5R, 10V, 0805 size) to compensate the reference buffer,
absorbtransientconversioncurrents,andminimizenoise.
LTC2335-18
20k
REFIN
BANDGAP
REFERENCE
2.7µF
REFBUF
REFERENCE
BUFFER
6.5k
LTC6655-2.048
47µF
6.5k
GND
233518 F10b
Figure 10b. Ex ternal Reference with Internal Buffer Configuration
233518f
26
For more information www.linear.com/LTC2335-18
LTC2335-18
applicaTions inForMaTion
and2ppm/°C(maximum)temperaturecoefficientforhigh
precision applications. The LTC6655-2.048 is fully speci-
fied over the H-grade temperature range, complementing
the extended temperature range of the LTC2335-18 up to
125°C.BypassingtheLTC6655-2.048witha2.7µFto100µF
ceramiccapacitorclosetotheREFINpinisrecommended.
LTC2335-18
REFIN
20k
BANDGAP
REFERENCE
REFBUF
REFERENCE
BUFFER
6.5k
LTC6655-5
47µF
Ex ternal Reference with Disabled Internal Buffer
6.5k
The internal reference buffer supports V
= 4.4V
REFBUF
GND
233518 F10c
maximum. Grounding REFIN disables the internal buffer,
allowing REFBUF to be overdriven with an external refer-
ence voltage between 2.5V and 5V, as shown in Figure
10c. Maximum input signal swing and SNR are achieved
byoverdrivingREFBUFusinganexternal5Vreference.The
buffer feedback resistors load the REFBUF pin with 13kΩ
evenwhenthereferencebufferisdisabled.TheLTC6655-5
offers the same small size, accuracy, drift, and extended
temperature range as the LTC6655-2.048, and achieves
a typical SNR of 98.3dB when paired with the LTC2335-
18. Bypass the LTC6655-5 to GND (Pin 20) close to the
REFBUF pin with at least a 47μF ceramic capacitor (X7R,
10V, 1210sizeorX5R, 10V, 0805size)toabsorbtransient
conversion currents and minimize noise.
Figure 10c. Ex ternal Reference with Disabled Internal
Buffer Configuration
to sample rate. In applications where a burst of samples
is taken after idling for long periods of time, as shown in
Figure 11, I
quickly transitions from approximately
REFBUF
0.4mA to 1.1mA (V
= 5V, f
= 1Msps). This
REFBUF
SMPL
current step triggers a transient response in the external
reference that must be considered, since any deviation in
V
affectsconverteraccuracy.Ifanexternalreference
REFBUF
is used to overdrive REFBUF, the fast settling LTC6655
family of references is recommended.
The LTC2335-18 converter draws a charge (Q
) from
CONV
the REFBUF pin during each conversion cycle. On short
time scales most of this charge is supplied by the external
REFBUF bypass capacitor, but on longer time scales all of
the charge is supplied by either the reference buffer, or
when the internal reference buffer is disabled, the external
reference. This charge draw corresponds to a DC current
Internal Reference Buffer Transient Response
Foroptimumperformanceinapplicationsemployingburst
sampling, the external reference with internal reference
bufferconfigurationshouldbeused.Theinternalreference
buffer incorporates a proprietary design that minimizes
movements in V
when responding to a burst of
equivalentofI
=Q
• f
,whichisproportional
REFBUF
REFBUF
CONV SMPL
CNV
233518 F11
IDLE
PERIOD
IDLE
PERIOD
Figure 11. CNV Waveform Showing Burst Sam pling
233518f
27
For more information www.linear.com/LTC2335-18
LTC2335-18
applicaTions inForMaTion
0
–20
conversions following an idle period. Figure 12 compares
the burst conversion response of the LTC2335-18 with an
input near full scale for two reference configurations. The
first configuration employs the internal reference buffer
with REFIN externally overdriven by an LTC6655-2.048,
while the second configuration disables the internal ref-
erence buffer and overdrives REFBUF with an external
LTC6655-4.096. In both cases REFBUF is bypassed to
GND with a 47µF ceramic capacitor.
±±10.24V RANG
–
T UGVBIPOLR VD I4GV(IA V=V14)
–40
SNR = 96.9dB
THD = –109dB
SINAD = 96.7dB
SFDR = 111dB
–60
–80
–100
–120
–140
–160
–180
15
0
100
200
300
400
500
±±10.24V RANG
+
FREQUENCY (kHz)
VIA V=V±14
233518 F13
–
VIA V=V14
10
Figure 13. 32k Point FFT fSMPL = 1Msps, fIN = 2kHz
EXTERNAL REFERENCE ON REFBUF
5
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 13 shows
that the LTC2335-18 achieves a typical SNR of 96.9dB in
the 10.24V range at a 1Msps sampling rate with a true
bipolar 2kHz input signal.
0
INTERNAL REFERENCE BUFFER
–5
0
100
200
300
400
500
TIME (µs)
233518 F12
Figure 12. Burst Conversion Response of the
LTC2335-18, fSMPL = 1Msps
Total Harm onic Distortion (THD)
DYNAMIC PERFORMANCE
Totalharmonicdistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion, and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2335-18 provides
guaranteed tested limits for both AC distortion and noise
measurements.
between DC and half the sampling frequency (f
THD is expressed as:
/2).
SMPL
V22 + V32 + V42...VN2
THD = 20log
V1
where V is the RMS amplitude of the fundamental fre-
1
Signal-to-Noise and Distortion Ratio (SINAD)
quencyandV throughV aretheamplitudesofthesecond
2
N
throughNthharmonics,respectively.Figure13showsthat
the LTC2335-18 achieves a typical THD of –109dB (N = 6)
in the 10.24V range at a 1Msps sampling rate with a true
bipolar 2kHz input signal.
The signal-to-noise and distortion ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies below half the sampling frequency, exclud-
ing DC. Figure 13 shows that the LTC2335-18 achieves a
typical SINAD of 96.7dB in the 10.24V range at a 1Msps
sampling rate with a true bipolar 2kHz input signal.
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POWER CONSIDERATIONS
TIMING AND CONTROL
CNV Tim ing
The LTC2335-18 provides four power supply pins: the
positive and negative high voltage power supplies (V
CC
The LTC2335-18 sampling and conversion is controlled
by CNV. A rising edge on CNV transitions the S/H circuits
from track mode to hold mode, sampling the input signals
and initiating a conversion. Once a conversion has been
started, it cannot be terminated early except by resetting
the ADC, as discussed in the Reset Timing section. For
optimum performance, drive CNV with a clean, low jitter
signal and avoid transitions on data I/O lines leading up
to the rising edge of CNV. Additionally, for best crosstalk
performance,avoidhighslewratesontheanaloginputsfor
100ns before and after the rising edge of CNV. Converter
status is indicated by the BUSY output, which transitions
low-to-high at the start of each conversion and stays high
untiltheconversioniscomplete.OnceCNVisbroughthigh
to begin a conversion, it should be returned low between
40ns and 60ns later or after the falling edge of BUSY to
minimizeexternaldisturbancesduringtheinternalconver-
sion process. The CNV timing required to take advantage
of the reduced power nap mode of operation is described
in the Nap Mode section.
and V ), the 5V core power supply (V ) and the digital
EE
DD
input/output (I/O) interface power supply (OV ). As long
DD
as the voltage difference limits of 10V ≤ V – V ≤ 38V
CC
EE
are observed, V and V may be independently biased
CC
EE
anywhere within their own individual allowed operating
ranges, including the ability for either of the supplies to be
tied directly to ground. This feature enables the common
mode input range of the LTC2335-18 to be tailored to the
specificapplication’srequirements.TheflexibleOV sup-
DD
ply allows the LTC2335-18 to communicate with CMOS
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems. When using LVDS I/O mode, the range of
OV is 2.375V to 5.25V.
DD
Power Supply Sequencing
The LTC2335-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2335-18 has
an internal power-on-reset (POR) circuit which resets the
Internal Conversion Clock
converter on initial power-up and whenever V drops
DD
below 2V. Once the supply voltage re-enters the nominal
supply voltage range, the POR reinitializes the ADC. No
conversions should be initiated until at least 10ms after
a POR event to ensure the initialization period has ended.
Whenemployingtheinternalreferencebuffer,allow200ms
forthebuffertopowerupandrechargetheREFBUFbypass
capacitor. Any conversion initiated before these times will
produce invalid results.
The LTC2335-18 has an internal clock that is trimmed
to achieve a maximum conversion time of 550ns. With
a minimum acquisition time of 420ns, throughput per-
formance of 1Msps is guaranteed without any external
adjustments. The LTC2335-18 is a multiplexed ADC and
converts one channel per CNV edge, taking a minimum
of 1μs per conversion. Thus, while scanning N channels
(N = 1 to 8), a complete scan takes at least N μs and the
maximum per-channel throughput is 1/N Msps/ch.
Nap Mode
The LTC2335-18 can be placed into nap mode after a con-
versionhasbeencompletedtoreducepowerconsumption
between conversions. In this mode a portion of the device
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circuitry is turned off, including circuits associated with
sampling the analog input signals. Nap mode is enabled
by keeping CNV high between conversions, as shown in
Figure 14. To initiate a new conversion after entering nap
mode, bring CNV low and hold for at least 420ns before
Reset Tim ing
A global reset of the LTC2335-18, equivalent to a power-
on-reset event, may be executed without needing to cycle
the supplies. This feature is useful when recovering from
system-level events that require the state of the entire sys-
tem to be reset to a known synchronized value. To initiate
a global reset, bring PD high twice without an intervening
conversion, as shown in Figure 15. The reset event is trig-
geredonthesecondrisingedgeofPD,andasynchronously
ends based on an internal timer. Reset clears all serial data
outputregistersandrestorestheinternalsequencerdefault
state of converting channels 0 through 7 sequentially, all
in SoftSpan 7. If reset is triggered during a conversion, the
conversion is immediately halted. The normal power down
behavior associated with PD going high is not affected by
reset. Once PD is brought low, wait at least 10ms before
initiating a conversion. When employing the internal refer-
ence buffer, allow 200ms for the buffer to power up and
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.
bringingithighagain.Theconverteracquisitiontime(t
)
ACQ
is set by the CNV low time (t
) when using nap mode.
CNVL
Power Down Mode
When PD is brought high, the LTC2335-18 is powered
down and subsequent conversion requests are ignored. If
this occurs during a conversion, the device powers down
once the conversion completes. In this mode, the device
draws only a small regulator standby current resulting in a
typical power dissipation of 0.36mW. To exit power down
mode, bring the PD pin low and wait at least 10ms before
initiatingaconversion. When employing theinternal refer-
ence buffer, allow 200ms for the buffer to power up and
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.
t
CNVL
CNV
t
CONV
BUSY
NAP
t
ACQ
NAP MODE
233518 F14
Figure 14. Nap Mode Tim ing for the LTC2335-18
t
PDH
t
PD
CNV
WAKE
t
t
PDL
CNVH
SECOND RISING EDGE OF
PD TRIGGERS RESET
BUSY
t
CONV
RESET TIME
SET INTERNALLY
RESET
233518 F15
Figure 15. Reset Tim ing for the LTC2335-18
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Power Dissipation vs Sam pling Frequency
DIGITAL INTERFACE
TheLTC2335-18featuresCMOSandLVDSserialinterfaces,
selectable using the LVDS/CMOS pin. The flexible OV
supply allows the LTC2335-18 to communicate with any
CMOSlogicoperatingbetween1.8Vand5V,including2.5V
and 3.3V systems, while the LVDS interface supports low
noisedigitaldesigns. Together, theseI/Ointerfaceoptions
enable the LTC2335-18 to communicate equally well with
legacy microcontrollers and modern FPGAs.
When nap mode is employed, the power dissipation of
the LTC2335-18 decreases as the sampling frequency is
reduced, as shown in Figure 16. This decrease in aver-
age power dissipation occurs because a portion of the
LTC2335-18 circuitry is turned off during nap mode, and
DD
the fraction of the conversion cycle (t ) spent napping
CYC
increasesasthesamplingfrequency(f
)isdecreased.
SMPL
16
WITH NAP MODE
CNVL
14
12
10
8
t
= 500ns
Serial CMOS I/O Mode
I
VDD
As shown in Figure 17, in CMOS I/O mode the serial data
bus consists of a serial clock input, SCKI, serial data input,
SDI, serial clock output, SCKO, and serial data output,
SDO. Communication with the LTC2335-18 across this
bus occurs during predefined data transaction windows.
Within a window, the device accepts control words on SDI
to configure the SoftSpan range and channel for the next
conversionandprogramthesequencer,andoutputs24-bit
packetscontainingtheconversionresultandconfiguration
information from the previous conversion on SDO.
6
4
I
VCC
2
I
0
OVDD
–2
–4
–6
I
VEE
0
200
400
600
800
1000
SAMPLING FREQUENCY (kHz)
233518 F16
Figure 16. Power Dissipation of the LTC2335-18
Decreases with Decreasing Sam pling Frequency
CS = PD = 0
SAMPLE N
SAMPLE N + 1
t
CYC
t
CNVH
t
CNVL
CNV
t
BUSY
CONV
t
ACQ
t
RECOMMENDED DATA TRANSACTION WINDOW
BUSYLH
t
QUIET
t
t
t
SCKIH
SSDISCKI
SCKI
SCKI
SDI
1
2
3
4
5
6
7
8
t
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
t
HSDISCKI
SCKIL
C7
C6 C5 C4 C3 C2 C1 C0
DON’T CARE
DON’T CARE
CONTROL WORD FOR CONVERSION N + 1
t
t
SKEW
t
DSDOBUSYL
HSDOSCKI
SCKO
SDO
t
DSDOSCKI
DON’T CARE
D17
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CH2 CH1 CH0 SS2 SS1 SS0 D17
CONVERSION RESULT CHANNEL ID SoftSpan
24-BIT PACKET CONVERSION N
CONVERSION RESULT
24-BIT PACKET CONVERSION N
(REPETITION)
233518 F17
Figure 17. Serial CMOS I/O Mode, Direct Per-Conversion Configuration
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New data transaction windows open 10ms after power-
ing up or resetting the LTC2335-18, and at the end of
each conversion on the falling edge of BUSY. The data
The LTC2335-18 guarantees a minimum data transfer
window(t –t )of400nswhileconvertingat1Msps.
ACQ QUIET
Thus, if an application needs to read the full 24-bit packet
of conversion result plus channel ID and SoftSpan, the
minimum usable SCKI frequency is 60MHz. Applications
needing to read only the conversion result may send only
18 SCKI pulses and thus have a minimum SCKI frequency
of45MHz.TheLTC2335-18supportsCMOSSCKIfrequen-
cies up to 100MHz.
transaction should be completed with a minimum t
QUIET
time of 20ns prior to the start of the next conversion, as
shown in Figure 17. New control words are only accepted
within this recommended data transaction window, but
configuration changes take effect immediately with no ad-
ditional analog input settling time required before starting
the next conversion.
Configuring the Multiplex er and SoftSpan Range in
CMOS I/O Mode
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SCKO is forced low and
SDO is updated with the latest conversion result from the
just-completed conversion. Rising edges on SCKI serially
clock the conversion result and analog input channel con-
figuration information out on SDO and trigger transitions
on SCKO that are skew-matched to the data on SDO. The
resulting SCKO frequency is half that of SCKI.
On power-up and after a reset, the LTC2335-18 defaults
to converting channels 0 through 7 sequentially, all in
SoftSpan 7. If this configuration does not need to be
changed, simply hold SDI low.
The LTC2335-18 multiplexer and SoftSpan range may
be controlled in two ways, depending on the needs of
the application. If the desired sequence of channels and
SoftSpan ranges are known ahead of time, the LTC2335-
18’s internal sequencer may be programmed with a se-
quence of up to 16 configurations, and will cycle through
those configurations on subsequent conversions without
further user intervention. Alternately, if ultimate flexibility
is desired, the LTC2335-18 may be directly controlled by
overwriting the sequencer each conversion with the chan-
nel and SoftSpan range for the following conversion. This
reconfiguration has no latency and requires no additional
settling time or digital I/O overhead.
SCKI rising edges also latch control words provided on
SDI, which are used to set the SoftSpan range and chan-
nel for the next conversion, and program the sequencer.
See the section Configuring the Multiplexer and SoftSpan
Range for further details. SCKI is allowed to idle either
high or low in CMOS I/O mode. As shown in Figure 18,
the CMOS bus is enabled when CS is low and is disabled
and Hi-Z when CS is high, allowing the bus to be shared
across multiple devices.
ThedataonSDOareformattedasa24-bitpacketconsisting
ofan18-bitconversionresult,3-bitanalogchannelID,and
3-bitSoftSpancode,allpresentedMSBfirst.Assuggested
in Figures 17 and 18, if more than 24 SCKI clocks are
applied, the 24-bit packet is repeated indefinitely on SDO.
Using the Sequencer
To use the internal sequencer of the LTC2335-18, first
program it as described below with the desired sequence
of up to 16 configurations. Each of these configurations
specifies the desired channel number and SoftSpan range
for one conversion. The LTC2335-18 will then apply the
first configuration to the first conversion, the second
configuration to the second conversion, and so on until
the end of the programmed sequence is reached, at which
point the cycle will start again from the beginning.
When interfacing the LTC2335-18 with a standard SPI
bus, capture output data at the receiver on rising edges
of SCKI. SCKO is not used in this case. In other applica-
tions, such as interfacing the LTC2335-18 with an FPGA
or CPLD, rising and falling edges of SCKO may be used
to capture serial output data on SDO in double data rate
(DDR) fashion. Capturing data using SCKO adds robust-
ness to delay variations over temperature and supply.
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Eachdatatransactionwindowisanopportunitytoprogram
thesequencerbyclockinginaseriesof8-bitcontrolwords
on SDI, each specifying a channel number and SoftSpan
range, as shown in Figures 17 and 18. To program the
sequencer with a series of up to 16 conversion configu-
rations, write in the corresponding control words in the
desired conversion order during a single data transaction.
Words beyond the 16th valid word will be ignored.
Direct Per-Conversion Configuration
As a special case of the sequencer, the LTC2335-18
multiplexer and SoftSpan range can be directly controlled
every conversion with no latency and no additional set-
tling time or digital I/O overhead. To use the part in this
direct fashion, simply supply one control word on SDI
during a data transaction to specify the desired channel
number and SoftSpan range for the following conversion,
as shown in Figure 17.
The control word format is as follows:
If the desired channel and SoftSpan range for conversion
N+1 are known before seeing the result of conversion N,
specifytheconfigurationbyclockinginthecorresponding
control word on SDI while clocking out the first 8 bits,
then hold SDI low. This particular use case is illustrated in
Figure 17. If the desired configuration is not known until
after the conversion data has been read, clock in 24 zeros
on SDI while the 24 bits of data are being read out; since
the V bits of those words are then 0, they are ignored.
Once the configuration has been determined, clock in 8
more bits on SDI which specify the desired configuration
for conversion N+1.
C[7]
V
C[6]
0
C[5]
C[4]
C[3]
C[2] C[1]
C[0]
CH[2] CH[1] CH[0] SS[2] SS[1] SS[0]
The V bit (C[7]) controls whether the LTC2335-18 should
consider this a valid word. Any words which have V =
0 are considered invalid and are ignored (though valid
words will still be accepted after an invalid word). Words
which have V = 1 will be added to the sequencer in the
order provided. The C[6] bit is reserved for future use and
should be set to 0. The CH[2:0] (C[5:3]) bits are a binary
value 0 to 7 controlling the channel to be converted. The
SS[2:0] (C[2:0]) bits specify the desired SoftSpan range
for the conversion, as described in Table 1.
Serial LVDS I/O Mode
In LVDS I/O mode, information is transmitted using
Sequencer programming is completed when the next
conversion is started. At this time, any incomplete words
are considered invalid and discarded. If one or more
valid words were provided, the sequencer is completely
overwritten with the new sequence, and the just-initiated
conversion employs the first provided configuration.
+
−
positiveandnegativesignalpairs(LVDS /LVDS )withbits
+
−
differentially encoded as (LVDS − LVDS ). These signals
are typically routed using differential transmission lines
with 100Ω characteristic impedance. Logical 1s and 0s
are nominally represented by differential +350mV and
−350mV,respectively.Forclarity,allLVDStimingdiagrams
and interface discussions adopt the logical rather than
physical convention.
If no valid words were provided during the data transac-
tion window, the sequencer program is unchanged, and
the pointer advances to the next entry in the previously
programmed cycle to configure the next conversion.
As shown in Figure 19, in LVDS I/O mode the serial data
busconsistsofaserialclockdifferentialinput, SCKI, serial
data differential input, SDI, serial clock differential output,
SCKO, and serial data differential output, SDO. Communi-
cation with the LTC2335-18 across this bus occurs during
predefined data transaction windows. Within a window,
the device accepts control words on SDI to configure the
SoftSpan range and channel for the next conversion and
Thus, once the sequencer has been programmed, simply
hold SDI low during subsequent data transactions to
cycle continually through the programmed sequence of
configurations.
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CS = PD = 0
SAMPLE N
SAMPLE N + 1
t
CYC
t
CNVH
CNV
(CMOS)
t
CNVL
BUSY
(CMOS)
t
t
CONV
ACQ
t
RECOMMENDED DATA TRANSACTION WINDOW
BUSYLH
t
QUIET
t
t
SCKI
t
SSDISCKI
SCKIH
SCKI
(LVDS)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
t
t
SCKIL
HSDISCKI
SDI
(LVDS)
C7
C6 C5 C4 C3 C2 C1 C0
DON’T CARE
DON’T CARE
CONTROL WORD FOR CONVERSION N + 1
t
t
SKEW
t
DSDOBUSYL
HSDOSCKI
SCKO
(LVDS)
t
DSDOSCKI
SDO
(LVDS)
DON’T CARE
D17
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CH2 CH1 CH0 SS2 SS1 SS0 D17
CONVERSION RESULT CHANNEL ID SoftSpan
24-BIT PACKET CONVERSION N
CONVERSION RESULT
24-BIT PACKET CONVERSION N
(REPETITION)
233518 F19
Figure 19. Serial LVDS I/O Mode, Direct Per-Conversion Configuration
it is recommend that rising and falling edges of SCKO be
usedtocaptureDDRserialoutputdataonSDO, asthiswill
yield the best robustness to delay variations over supply
and temperature.
program the sequencer, and outputs 24-bit packets con-
tainingtheconversionresultandconfigurationinformation
from the previous conversion on SDO.
New data transaction windows open 10ms after power-
ing up or resetting the LTC2335-18, and at the end of
each conversion on the falling edge of BUSY. The data
SCKI rising and falling edges also latch control words
provided on SDI, which are used to set the SoftSpan range
and channel for the next conversion, and program the
sequencer. See the section Configuring the Multiplexer
and SoftSpan Range in LVDS I/O Mode for further details.
As shown in Figure 20, the LVDS bus is enabled when CS
is low and is disabled and Hi-Z when CS is high, allow-
ing the bus to be shared across multiple devices. Due to
the high speeds often involved in LVDS signaling, LVDS
bus sharing must be carefully considered. Transmission
line limitations imposed by the shared bus may limit the
maximum achievable bus clock speed. LVDS inputs are
internallyterminatedwitha100Ωdifferentialresistorwhen
CS is low, while outputs must be differentially terminated
with a 100Ω resistor at the receiver (FPGA). SCKI must
idle in the low state in LVDS I/O mode, including when
transitioning CS.
transaction should be completed with a minimum t
QUIET
time of 20ns prior to the start of the next conversion, as
shown in Figure 19. New control words are only accepted
within this recommended data transaction window, but
configuration changes take effect immediately with no ad-
ditional analog input settling time required before starting
the next conversion.
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SDO is updated with the
latest conversion result from the just-completed conver-
sion.BothrisingandfallingedgesonSCKIseriallyclockthe
conversion result and analog input channel configuration
information out on SDO. SCKI is also echoed on SCKO,
skew-matched to the data on SDO. Whenever possible,
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for one conversion. The LTC2335-18 will then apply the
first configuration to the first conversion, the second
configuration to the second conversion, and so on until
the end of the programmed sequence is reached, at which
point the cycle will start again from the beginning.
ThedataonSDOareformattedasa24-bitpacketconsisting
ofan18-bitconversionresult,3-bitanalogchannelID,and
3-bitSoftSpancode,allpresentedMSBfirst.Assuggested
in Figures 19 and 20, if more than 24 SCKI clocks are
applied, the 24-bit packet is repeated indefinitely on SDO.
Eachdatatransactionwindowisanopportunitytoprogram
thesequencerbyclockinginaseriesof8-bitcontrolwords
on SDI, each specifying a channel number and SoftSpan
range, as shown in Figures 19 and 20. To program the
sequencer with a series of up to 16 conversion configu-
rations, write in the corresponding control words in the
desired conversion order during a single data transaction.
Words beyond the 16th valid word will be ignored.
The LTC2335-18 guarantees a minimum data transfer
window(t –t
)of400nswhileconvertingat1Msps.
ACQ QUIET
Thus, if an application needs to read the full 24-bit packet
of conversion result plus channel ID and SoftSpan, the
minimum usable SCKI frequency is 30MHz (60Mbps).
Applications needing to read only the conversion result
may send only 18 SCKI edges and thus have a minimum
SCKI frequency of 22.5MHz (45Mbps). The LTC2335-18
supportsLVDSSCKIfrequenciesupto250MHz(500Mbps).
The control word format is as follows:
Configuring the Multiplex er and SoftSpan Range in
LVDS I/O Mode
C[7]
V
C[6]
0
C[5]
C[4]
C[3]
C[2] C[1]
C[0]
CH[2] CH[1] CH[0] SS[2] SS[1] SS[0]
On power-up and after a reset, the LTC2335-18 defaults
to converting channels 0 through 7 sequentially, all in
SoftSpan 7. If this configuration does not need to be
changed, simply hold SDI at an LVDS low level.
The V bit (C[7]) controls whether the LTC2335-18 should
consider this a valid word. Any words which have V =
0 are considered invalid and are ignored (though valid
words will still be accepted after an invalid word). Words
which have V = 1 will be added to the sequencer in the
order provided. The C[6] bit is reserved for future use and
should be set to 0. The CH[2:0] (C[5:3]) bits are a binary
value 0 to 7 controlling the channel to be converted. The
SS[2:0] (C[2:0]) bits specify the desired SoftSpan range
for the conversion, as described in Table 1.
The LTC2335-18 multiplexer and SoftSpan range may be
controlled in two ways, depending on the needs of the ap-
plication.IfthedesiredsequenceofchannelsandSoftSpan
rangesareknownaheadoftime,theLTC2335-18’sinternal
sequencer may be programmed with a sequence of up to
16 configurations, and will cycle through those configu-
rations on subsequent conversions without further user
intervention.Alternatelyifultimateflexibilityisdesired,the
LTC2335-18 may be directly controlled by overwriting the
sequencereachconversionwiththechannelandSoftSpan
range for the following conversion. This reconfiguration
has no latency and requires no additional settling time or
digital I/O overhead.
Sequencer programming is completed when the next
conversion is started. At this time, any incomplete words
are considered invalid and discarded. If one or more
valid words were provided, the sequencer is completely
overwritten with the new sequence, and the just-initiated
conversion employs the first provided configuration.
If no valid words were provided during the data transac-
tion window, the sequencer program is unchanged, and
the pointer advances to the next entry in the previously
programmed cycle to configure the next conversion.
Using the Sequencer
To use the internal sequencer of the LTC2335-18, first
program it as described below with the desired sequence
of up to 16 configurations. Each of these configurations
specifies the desired channel number and SoftSpan range
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Thus, once the sequencer has been programmed, simply
hold SDI at an LVDS low level during subsequent data
transactionstocyclecontinuallythroughtheprogrammed
sequence of configurations.
If the desired channel and SoftSpan range for conversion
N+1 are known before seeing the result of conversion N,
specifytheconfigurationbyclockinginthecorresponding
control word on SDI while clocking out the first 8 bits,
then hold SDI at an LVDS low level. This particular use
case is illustrated in Figure 19. If the desired configura-
tion is not known until after the conversion data has been
read, clock in 24 zeros on SDI while the 24 bits of data
are being read out; since the V bits of those words are
then 0, they are ignored. Once the configuration has been
determined, clock in 8 more bits on SDI which specify the
desired configuration for conversion N+1.
Direct Per-Conversion Configuration
As a special case of the sequencer, the LTC2335-18
multiplexer and SoftSpan range can be directly controlled
every conversion with no latency and no additional set-
tling time or digital I/O overhead. To use the part in this
direct fashion, simply supply one control word on SDI
during a data transaction to specify the desired channel
number and SoftSpan range for the following conversion,
as shown in Figure 19.
boarD layouT
To obtain the best performance from the LTC2335-18, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Also minimize the length of the REFBUF to GND (Pin 20)
bypass capacitor return loop, and avoid routing CNV near
signals which could potentially disturb its rising edge.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common re-
turns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this con-
verter, including schematics and PCB layout, please refer
to DC2412A, the evaluation kit for the LTC2335-18.
233518f
38
For more information www.linear.com/LTC2335-18
LTC2335-18
package DescripTion
Please refer to http://www.linear.com /product/LTC2335-18#packaging for the m ost recent package drawings.
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1760 Rev A)
7.15 – 7.25
5.50 REF
9.00 BSC
7.00 BSC
48
48
SEE NOTE: 4
1
2
1
2
0.50 BSC
9.00 BSC
7.00 BSC
5.50 REF
7.15 – 7.25
0.20 – 0.30
A
A
PACKAGE OUTLINE
C0.30 – 0.50
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.60
1.35 – 1.45 MAX
11° – 13°
R0.08 – 0.20
GAUGE PLANE
0.25
0° – 7°
11° – 13°
1.00 REF
0.50
BSC
0.09 – 0.20
0.17 – 0.27
0.05 – 0.15
0.45 – 0.75
SECTION A – A
e 3
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
COMPONENT
PIN “A1”
LX48 LQFP 0113 REV A
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
233518f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
39
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2335-18
Typical applicaTion
Digitize Differential Signals Over a Wide Com m on Mode Range
31V
+
½ LT1124
+
–
IN
ARBITRARY
LOWPASS FILTERS
49.9Ω
31V
18pF
24V
0.1µF
2.49k
6.6nF
V
+
–
CC
COMMON MODE
INPUT RANGE
IN0
IN0
549Ω
2.49k
LTC2335-18
6.6nF
DIFFERENTIAL MODE
INPUT RANGE: 500ꢀV
18pF
49.9Ω
V
REFBUF
47µF
REFIN
EE
0V
–
+
0.1µF
0.1µF
–5V
BW ~ 500kHz
–
IN
½ LT1124
–5V
ONLY CHANNEL 0 SHOWN FOR CLARITY
233518 TA02
relaTeD parTs
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2348-18/LTC2348-16 18-/16-Bit, 200ksps, 8-Channel Simultaneous
Sampling, 3/ 1LSB INL, Serial ADC
10.24V SoftSpan Inputs with Wide Common Mode Range, 97/94dB SNR,
Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
LTC2378-20/LTC2377-20/ 20-Bit, 1Msps/500ksps/250ksps,
2.5V Supply, 5V Fully Differential Input, 104dB SNR, MSOP-16 and
4mm × 3mm DFN-16 Packages
LTC2376-20
0.5ppm INL Serial, Low Power ADC
LTC2338-18/LTC2337-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial,
LTC2336-18 Low Power ADC
LTC2328-18/LTC2327-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial,
LTC2326-18 Low Power ADC
LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC
5V Supply, 10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package
5V Supply, 10.24V Pseudo-Differential Input, 95dB SNR,
MSOP-16 Package
5V Supply, 8 Channel Multiplexed, Configurable Input Range, 100dB SNR,
DGC, 5mm × 5mm QFN-32 Package
LTC2379-18/LTC2378-18/ 18-Bit,1.6Msps/1Msps/500ksps/250ksps, Serial, 2.5V Supply, Differential Input, 101.2dB SNR, 5V Input Range, DGC, Pin
LTC2377-18/LTC2376-18 Low Power ADC Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps, Serial, 2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC, Pin
LTC2377-16/LTC2376-16 Low Power ADC
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2387-18
18-Bit, 15Msps, 3LSB INL, Serial SAR ADC
4.096V Fully Differential Input, 96dB SNR, Serial LVDS I/O, 5mm × 5mm
QFN-32 Package
LTC1859/LTC1858/
LTC1857
LTC1609
16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC
16-Bit, 200ksps Serial ADC
10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,
SSOP-28 Package
10V, Configurable Unipolar/Bipolar Input, Single 5V Supply, SSOP-28 and
SO-20 Packages
LTC1606/LTC1605
DACs
16-Bit, 250ksps/100ksps, Parallel ADC
10V Input, 5V Supply, 75mW/55mW, SSOP-28 and SO-28 Packages
LTC2756/LTC2757
18-Bit, Serial/Parallel I
SoftSpan DAC
1LSB INL/DNL, Software-Selectable Ranges,
SSOP-28/7mm × 7mm LQFP-48 Package
OUT
LTC2668
16-Channel 16-/12-Bit 10V V
SoftSpan DACs 4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package
OUT
References
LTC6655
LTC6652
Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
Am plifiers
LT1468/LT1469
LT1354/LT1355/LT1356
LT1357/LT1358/LT1359
Single/Dual 90MHz, 22V/µs, 16-Bit Accurate Op Amp Low Input Offset: 75µV/125µV
Single/Dual/Quad 1mA, 12MHz, 400V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads
Single/Dual/Quad 2mA, 25MHz, 800V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads
233518f
LT 0116 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
40
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2335-18
●
●
LINEAR TECHNOLOGY CORPORATION 2016
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