LTC2336CMS-18#PBF_技术文档

LTC2336-18

18-Bit, 250ksps, 10ꢀ2ꢁ4

True Bipolar, Fully Differential

Input ADC with 100dB SNR

DescripTion

FeaTures

TheLTC^®2336-18isalownoise,highspeed18-bitsucces-

siveapproximationregister(SAR)ADCwithfullydifferential

inputs.Operatingfromasingle5Vsupply,theLTC2336-18

has a 1ꢀ.2ꢁV true bipolar input range, making it ideal for

high voltage applications which require a wide dynamic

range. The LTC2336-18 achieves ꢁLSB INL maximum,

no missing codes at 18-bits with 1ꢀꢀdB SNR.

n

250ksps Throughput Rate

n

±±LSB INL (Max)

n

Guaranteed 18-Bit No Missing Codes

Fully Differential Inputs

n

True Bipolar Input Ranges ±ꢀ625V, ±1062±V, ±1265V

n

100dB SNR (Typ) at f = 2kHz

IN

n

–115dB THD (Typ) at f = 2kHz

Guaranteed Operation to 125°C

The LTC2336-18 has an onboard single-shot capable

reference buffer and low drift (2ꢀppm/°C max) 2.ꢀꢁ8V

temperature compensated reference. The LTC2336-18

also has a high speed SPI-compatible serial interface that

supports1.8V,2.5V,3.3Vand5Vlogicwhilealsofeaturing

a daisy-chain mode. The fast 25ꢀksps throughput with

no cycle latency makes the LTC2336-18 ideally suited

for a wide variety of high speed applications. An internal

oscillator sets the conversion time, easing external timing

considerations. The LTC2336-18 dissipates only 28mW

and automatically naps between conversions, leading to

reduced power dissipation that scales with the sampling

rate. A sleep mode is also provided to reduce the power

consumption of the LTC2336-18 to 3ꢀꢀμW for further

power savings during inactive periods.

Single 5V Supply

Low Drift (2ꢀppm/°C Max) 2.ꢀꢁ8V Internal Reference

Onboard Single-Shot Capable Reference Buffer

No Pipeline Delay, No Cycle Latency

1.8V to 5V I/O Voltages

SPI-Compatible Serial I/O with Daisy-Chain Mode

Internal Conversion Clock

Power Dissipation 28mW (Typ)

16-Lead MSOP Package

applicaTions

n

Programmable Logic Controllers

n

Industrial Process Control

n

High Speed Data Acquisition

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 77ꢀ5765 and 7961132

n

Portable or Compact Instrumentation

n

ATE

Typical applicaTion

32k Point FFT f_S= 250ksps,

f_IN= 2kHz

5V

1.8V TO 5V

0

SNR = 100.3dB

–20

–40

THD = –117dB

SINAD = 100.2dB

SFDR = –118dB

10µF

2.2µF

0.1µF

V

OV

DD

DDLBYP DD

+10.24V

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

–60

+

–

IN

+

–

–80

–10.24V

+10.24V

LTC2336-18

–100

–120

–140

–160

–180

IN

SAMPLE CLOCK

–10.24V

REF

REFBUF

REFIN

100nF

GND

233618 TA01

47µF

0

25

50

75

100

125

FREQUENCY (kHz)

233618 TA01b

233618f

1

For more information www.linear.com/LTC2336-18

LTC2336-18

absoluTe MaxiMuM raTings

pin conFiguraTion

(Notes 1, 2)

TOP VIEW

Supply Voltage (V )..................................................6V

DD

V

1

2

16 GND

DDLBYP

V

15 OV

DD

Supply Voltage (OV )................................................6V

DD

GND 3

14 SDO

13 SCK

+

–

IN

4

5

Supply Bypass Voltage (V

Analog Input Voltage

) ...........................3.2V

DDLBYP

12 RDL/SDI

11 BUSY

10 CHAIN

GND 6

REFBUF 7

REFIN 8

+

–

IN , IN ..............................................–16.5V to 16.5V

REFBUF...................................................................6V

REFIN ..................................................................2.8V

Digital Input Voltage

9

CNV

MS PACKAGE

16-LEAD PLASTIC MSOP

= 15ꢀ°C, θ = 11ꢀ°C/W

T

JMAX

JA

(Note 3)........................... (GND –ꢀ.3V) to (OV + ꢀ.3V)

DD

Digital Output Voltage

(Note 3)........................... (GND –ꢀ.3V) to (OV + ꢀ.3V)

DD

Power Dissipation.............................................. 5ꢀꢀmW

Operating Temperature Range

LTC2336C................................................ ꢀ°C to 7ꢀ°C

LTC2336I .............................................–ꢁꢀ°C to 85°C

LTC2336H.......................................... –ꢁꢀ°C to 125°C

Storage Temperature Range .................. –65°C to 15ꢀ°C

orDer inForMaTion

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

16-Lead Plastic MSOP

TEMPERATURE RANGE

ꢀ°C to 7ꢀ°C

LTC2336CMS-18#PBF

LTC2336IMS-18#PBF

LTC2336HMS-18#PBF

LTC2336CMS-18#TRPBF 233618

LTC2336IMS-18#TRPBF 233618

LTC2336HMS-18#TRPBF 233618

–ꢁꢀ°C to 85°C

–ꢁꢀ°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

233618f

2

For more information www.linear.com/LTC2336-18

LTC2336-18

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C6 (Note ±)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

+

l

V

Absolute Input Range (IN )

(Note 5)

–2.5 • V

– ꢀ.25

2.5 • V

+ ꢀ.25

IN

REFBUF

–

+

–

Absolute Input Range (IN )

(Note 5)

V

–

+

–

– V

Input Differential Voltage Range

Common Mode Input Range

Analog Input Current

V

= V – V

–5 • V

5 • V

REFBUF

V

IN

REFBUF

(Note 11)

–ꢀ.5

–7.8

ꢀ

ꢀ.5

ꢁ.8

V

CM

I

IN

mA

pF

kΩ

dB

C

Analog Input Capacitance

5

IN

R

Analog Input Resistance

2.ꢀ83

67

IN

CMRR

Input Common Mode Rejection Ratio

f = 125kHz

IN

converTer characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C6 (Note ±)

SYMBOL

PARAMETER

CONDITIONS

MIN

18

TYP

MAX

UNITS

Bits

l

Resolution

No Missing Codes

18

Bits

Transition Noise

ꢀ.8

1

LSB

RMS

l

INL

Integral Linearity Error

Differential Linearity Error

Bipolar Zero-Scale Error

Bipolar Zero-Scale Error Drift

Bipolar Full-Scale Error

(Note 6)

(Note 7)

–ꢁ

–1

ꢁ

1

LSB

DNL

BZE

ꢀ.1

ꢀ

LSB

–15

15

ꢀ.ꢀ1

LSB/°C

LSB

l

FSE

V

= ꢁ.ꢀ96V (REFBUF Overdriven)

–1ꢀꢀ

–15ꢀ

1ꢀꢀ

15ꢀ

REFBUF

(Notes 7, 9)

REFIN = 2.ꢀꢁ8V (Note 7)

LSB

Bipolar Full-Scale Error Drift

ꢀ.5

ppm/°C

DynaMic accuracy ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –1dBFS6 (Notes ±, 8)

SYMBOL PARAMETER

CONDITIONS

6.25V Range, f = 2kHz, REFIN = 1.25V

MIN

93

TYP

97

MAX

UNITS

dB

l

SINAD

Signal-to-(Noise + Distortion) Ratio

IN

1ꢀ.2ꢁV Range, f = 2kHz, REFIN = 2.ꢀꢁ8V

95

1ꢀꢀ

1ꢀ1

97

dB

IN

12.5V Range, f = 2kHz, REFBUF = 5V

96

dB

IN

SNR

Signal-to-Noise Ratio

6.25V Range, f = 2kHz, REFIN = 1.25V

93.5

96

dB

IN

1ꢀ.2ꢁV Range, f = 2kHz, REFIN = 2.ꢀꢁ8V

1ꢀꢀ

1ꢀ2

–111

–115

–112

113

117

11ꢁ

7

dB

IN

12.5V Range, f = 2kHz, REFBUF = 5V

98

dB

IN

THD

Total Harmonic Distortion

Spurious Free Dynamic Range

6.25V Range, f = 2kHz, REFIN = 1.25V

–1ꢀ2

–1ꢀꢀ

dB

IN

1ꢀ.2ꢁV Range, f = 2kHz, REFIN = 2.ꢀꢁ8V

dB

IN

12.5V Range, f = 2kHz, REFBUF = 5V

dB

IN

SFDR

6.25V Range, f = 2kHz, REFIN = 1.25V

1ꢀ2

1ꢀꢀ

dB

IN

1ꢀ.2ꢁV Range, f = 2kHz, REFIN = 2.ꢀꢁ8V

dB

IN

12.5V Range, f = 2kHz, REFBUF = 5V

dB

IN

–3dB Input Linear Bandwidth

Aperture Delay

MHz

ps

5ꢀꢀ

ꢁ

Aperture Jitter

ps

Transient Response

Full-Scale Step

1

µs

233618f

3

For more information www.linear.com/LTC2336-18

LTC2336-18

inTernal reFerence characTerisTics ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C6 (Note ±)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

2.ꢀꢁ8

2

MAX

2.ꢀ53

2ꢀ

UNITS

V

Internal Reference Output Voltage

2.ꢀꢁ3

REFIN

l

V

REFIN

Temperature Coefficient

(Note 1ꢁ)

ppm/°C

kΩ

REFIN Output Impedance

Line Regulation

15

V

REFIN

V

= ꢁ.75V to 5.25V

DD

ꢀ.ꢀ8

mV/V

V

REFIN Input Voltage Range

(REFIN Overdriven) (Note 5)

1.25

2.ꢁ

reFerence buFFer characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C6 (Note ±)

SYMBOL PARAMETER

CONDITIONS

= 2.ꢀꢁ8V

MIN

ꢁ.ꢀ91

2.5

TYP

MAX

ꢁ.1ꢀ1

5

UNITS

l

V

Reference Buffer Output Voltage

REFBUF Input Voltage Range

REFBUF Output Impedance

REFBUF Load Current

V

ꢁ.ꢀ96

V

REFBUF

REFIN

(REFBUF Overdriven) (Notes 5, 9)

V

= ꢀV

13

kΩ

REFIN

l

I

V

= 5V (REFBUF Overdriven) (Notes 9, 1ꢀ)

= 5V, Nap Mode (REFBUF Overdriven) (Note 9)

ꢀ.56

ꢀ.39

ꢀ.6

mA

REFBUF

DigiTal inpuTs anD DigiTal ouTpuTs ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C6 (Note ±)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

0.8 • OV

IH

IL

DD

0.2 • OV

V

DD

I

V

IN

= ꢀV to OV

DD

–1ꢀ

1ꢀ

μA

pF

IN

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

IN

l

I = –5ꢀꢀµA

O

OV – ꢀ.2

DD

V

OH

OL

I = 5ꢀꢀµA

O

ꢀ.2

1ꢀ

V

I

V

OUT

V

OUT

V

OUT

= ꢀV to OV

DD

–1ꢀ

µA

mA

OZ

= ꢀV

= OV

–1ꢀ

1ꢀ

SOURCE

SINK

DD

power requireMenTs ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C6 (Note ±)

SYMBOL

PARAMETER

Supply Voltage

CONDITIONS

MIN

ꢁ.75

1.71

TYP

MAX

5.25

6.5

UNITS

l

V

5

V

DD

OV

DD

+

–

I

Supply Current

Nap Mode Current

Sleep Mode Current

25ꢀksps Sample Rate (IN = IN = ꢀV)

25ꢀksps Sample Rate (C = 2ꢀpF)

Conversion Done (I

Sleep Mode (I

5.5

ꢀ.ꢀ5

3.9

6ꢀ

mA

μA

VDD

OVDD

NAP

L

+ I

l

)

OVDD

ꢁ.6

225

VDD

+ I )

OVDD

SLEEP

VDD

+

–

l

P

Power Dissipation

Nap Mode

Sleep Mode

25ꢀksps Sample Rate (IN = IN = ꢀV)

Conversion Done (I + I

27.5

19.5

ꢀ.3

32.5

23

1.1

mW

D

)

OVDD

VDD

Sleep Mode (I

+ I

)

VDD

OVDD

233618f

4

For more information www.linear.com/LTC2336-18

LTC2336-18

aDc TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C6 (Note ±)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

25ꢀ

3

UNITS

ksps

µs

l

f

t

Maximum Sampling Frequency

Conversion Time

SMPL

CONV

ACQ

1.9

Acquisition Time

t

= t

CYC

– t (Note 11)

HOLD

3.ꢁ6ꢀ

µs

ACQ

Maximum Time between Acquisitions

Time Between Conversions

CNV High Time

5ꢁꢀ

13

ns

HOLD

CYC

ꢁ

µs

2ꢀ

ns

CNVH

BUSYLH

CNVL

C = 2ꢀpF

L

ns

CNV↑ to BUSY Delay

Minimum Low Time for CNV

SCK Quiet Time from CNV↑

SCK Period

(Note 12)

(Note 11)

2ꢀ

1ꢀ

ꢁ

ns

QUIET

SCK

(Notes 12, 13)

ns

SCK High Time

ns

SCKH

SCKL

SCK Low Time

ꢁ

ns

(Note 12)

ꢁ

ns

SDI Setup Time From SCK↑

SDI Hold Time From SCK↑

SCK Period in Chain Mode

SDO Data Valid Delay from SCK↑

SSDISCK

HSDISCK

SCKCH

DSDO

1

ns

t

= t

+ t (Note 12)

DSDO

13.5

ns

SCKCH

SSDISCK

l

C = 2ꢀpF, OV = 5.25V

7.5

8

9.5

ns

L

DD

C = 2ꢀpF, OV = 2.5V

L

C = 2ꢀpF, OV = 1.71V

L

l

t

C = 2ꢀpF (Note 11)

1

ns

SDO Data Remains Valid Delay from SCK↑

SDO Data Valid Delay from BUSY↓

Bus Enable Time After RDL↓

HSDO

DSDOBUSYL

EN

L

C = 2ꢀpF (Note 11)

L

5

(Note 12)

16

13

ns

Bus Relinquish Time After RDL↑

REFBUF Wakeup Time

DIS

C

= ꢁ7μF, C = 1ꢀꢀnF

REFIN

2ꢀꢀ

ms

WAKE

REFBUF

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

when the output code flickers between ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ and 11

1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS

or +FS untrimmed deviation from ideal first and last code transitions and

includes the effect of offset error.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground or above V or

Note 8: All specifications in dB are referred to a full-scale 2ꢀ.ꢁ8V input

with REFIN = 2.ꢀꢁ8V.

DD

OV , they will be clamped by internal diodes. This product can handle

Note 9: When REFBUF is overdriven, the internal reference buffer must be

turned off by setting REFIN = ꢀV.

DD

input currents up to 1ꢀꢀmA below ground or above V or OV without

DD

latch-up.

Note 10: f

= 25ꢀkHz, I

varies proportionally with sample rate.

SMPL

REFBUF

Note ±: V = 5V, OV = 2.5V, 1ꢀ.2ꢁV Range, REFIN = 2.ꢀꢁ8V,

DD

Note 11: Guaranteed by design, not subject to test.

Note 12: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V

f

= 25ꢀkHz.

SMPL

DD

Note 5: Recommended operating conditions.

and OV = 5.25V.

DD

Note ꢀ: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 13: t

1ꢀꢀMHz for rising edge capture.

Note 1±: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

of 1ꢀns maximum allows a shift clock frequency up to

SCK

Note 7: Bipolar zero error is the offset voltage measured from –ꢀ.5LSB

0.8 • OV

DD

t

WIDTH

0.2 • OV

DD

50%

t

DELAY

233618 F01

0.8 • OV

0.2 • OV

DD

0.2 • OV

Figure 16 Voltage Levels for Timing Specifications

233618f

5

For more information www.linear.com/LTC2336-18

LTC2336-18

T_A= 25°C, V_DD= 5V, OV_DD= 265V, REFIN = 260±8V,

DC Histogram

Typical perForMance characTerisTics

f_SMPL= 250ksps, unless otherwise noted6

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

3.0

2.5

0.5

0.4

5000

σ = 0.8

4500

2.0

0.3

4000

3500

3000

2500

2000

1500

1000

500

1.5

0.2

1.0

0.1

0.5

0

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–0.1

–0.2

–0.3

–0.4

–0.5

0

65536

131072

196608

262144

0

65536

131072

196608

262144

131067 131069 131071 131073 131075

CODE

OUTPUT CODE

233618 G03

233618 G01

233618 G02

32k Point FFT f_S= 250ksps,

f_IN= 2kHz

THD, Harmonics

SNR, SINAD vs Input Frequency

vs Input Frequency

0

–20

110

100

90

–70

–80

SNR = 100.3dB

THD

2ND

3RD

THD = –117dB

SINAD = 100.2dB

SFDR = –118dB

SNR

–40

–90

SINAD

–60

–100

–110

–120

–130

–140

–150

–80

–100

–120

–140

–160

–180

80

70

60

0

25

50

75

100

125

0

25

50

75

100

125

0

25

50

75

100

125

FREQUENCY (kHz)

233618 G05

233618 G06

233618 G04

SNR, SINAD vs Input Level,

f_IN= 2kHz

SNR, SINAD vs Temperature,

f_IN= 2kHz

THD, Harmonics vs Temperature,

f_IN= 2kHz

102.0

101.5

101.0

100.5

100.0

102.0

101.5

101.0

100.5

100.0

99.5

–105

–110

–115

–120

–125

–130

–135

THD

3RD

SNR

SINAD

2ND

99.0

98.5

98.0

–40

–30

–20

–10

0

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

INPUT LEVEL (dB)

TEMPERATURE (°C)

233618 G07

233618 G08

233618 G09

233618f

6

For more information www.linear.com/LTC2336-18

LTC2336-18

T_A= 25°C, V_DD= 5V, OV_DD= 265V, REFIN = 260±8V,

Typical perForMance characTerisTics

f_SMPL= 250ksps, unless otherwise noted6

INL/DNL vs Temperature

Full-Scale Error vs Temperature

Offset Error vs Temperature

2.0

1.5

20

15

5

4

3

1.0

10

MAX INL

MAX DNL

2

0.5

5

1

0

MIN DNL

MIN INL

–1

–2

–3

–4

–5

–0.5

–1.0

–1.5

–2.0

–5

–10

–15

–20

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

233618 G11

233618 G12

233618 G10

Internal Reference Output vs

Temperature

Supply Current vs Temperature

Sleep Current vs Temperature

6

5

4

3

2

1

0

120

100

80

60

40

20

0

2.0484

2.0483

2.0482

2.0481

2.0480

2.0479

2.0478

2.0477

2.0476

V

DD

OV

DD

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

233618 G15

233618 G13

233618 G14

Internal Reference Output

Temperature Coefficient

Distribution

CMRR vs Input Frequency

Supply Current vs Sampling Rate

35

30

25

20

15

10

5

80

75

70

65

60

55

50

6

5

4

3

2

1

0

V

DD

OV

DD

0

25

50

75

100

125

0

50

100

150

200

250

–10 –8 –6 –4 –2

0

2

4

6

8 10

FREQUENCY (kHz)

DRIFT (ppm/°C)

SAMPLING FREQUENCY (kHz)

233618 G16

233618 G18

233618 G17

233618f

7

For more information www.linear.com/LTC2336-18

LTC2336-18

pin FuncTions

V

(Pin 1): 2.5V Supply Bypass Pin. The voltage

CHAIN (Pin 10): Chain Mode Selector Pin. When low,

the LTC2336-18 operates in normal mode and the

RDL/SDI input pin functions to enable or disable SDO.

Whenhigh,theLTC2336-18operatesinchainmodeandthe

RDL/SDI pin functions as SDI, the daisy-chain serial data

DDLBYP

on this pin is generated via an onboard regulator off of

DD

V . This pin must be bypassed with a 2.2μF ceramic

capacitor to GND.

V

(Pin2):5VPowerSupply.TherangeofV isꢁ.75Vto

DD

input. Logic levels are determined by OV .

DD

5.25V. Bypass V to GND with a 1ꢀµF ceramic capacitor.

DD

BUSY (Pin 11): BUSY Indicator. Goes high at the start of

GND (Pins 3, ꢀ and 1ꢀ): Ground.

a new conversion and returns low when the conversion

+

–

IN , IN (Pins ±, 5): Positive and Negative Differential

has finished. Logic levels are determined by OV .

DD

Analog Inputs. Typical input range 1ꢀ.2ꢁV.

RDL/SDI (Pin 12): When CHAIN is low, the part is in nor-

mal mode and the pin is treated as a bus enabling input.

When CHAIN is high, the part is in chain mode and the

pin is treated as a serial data input pin where data from

another ADC in the daisy chain is input. Logic levels are

REFBUF (Pin 7): Reference Buffer Output. An onboard

buffer nominally outputs ꢁ.ꢀ96V to this pin. This pin is

referred to GND and should be decoupled closely to the

pin with a ꢁ7μF ceramic capacitor. The internal buffer

driving this pin may be disabled by grounding its input

at REFIN. Once the buffer is disabled, an external refer-

ence may overdrive this pin in the range of 2.5V to 5V. A

resistive load greater than 5ꢀꢀkΩ can be placed on the

reference buffer output.

determined by OV .

DD

SCK(Pin13):SerialDataClockInput.WhenSDOisenabled,

the conversion result or daisy-chain data from another

ADC is shifted out on the rising edges of this clock MSB

first. Logic levels are determined by OV .

DD

REFIN (Pin 8): Reference Output/Reference Buffer Input.

An onboard bandgap reference nominally outputs 2.ꢀꢁ8V

at this pin. Bypass this pin with a 1ꢀꢀnF ceramic capacitor

to GND to limit the reference output noise. If more accu-

racy is desired, this pin may be overdriven by an external

reference in the range of 1.25V to 2.ꢁV.

SDO(Pin1±):SerialDataOutput. Theconversionresultor

daisy-chain data is output on this pin on each rising edge

of SCK MSB first. The output data is in 2’s complement

format. Logic levels are determined by OV .

DD

OV (Pin 15): I/O Interface Digital Power. The range of

DD

OV is 1.71V to 5.25V. This supply is nominally set to

DD

CNV (Pin 9): Convert Input. A rising edge on this input

the same supply as the host interface (1.8V, 2.5V, 3.3V,

powers up the part and initiates a new conversion. Logic

or 5V). Bypass OV to GND with a ꢀ.1μF capacitor.

DD

levels are determined by OV .

DD

233618f

8

For more information www.linear.com/LTC2336-18

LTC2336-18

FuncTional block DiagraM

REFIN = 1.25V REFBUF = 2.5V

OV = 1.8V

DD

TO 5V

V

DD

= 5V

V

= 2.5V

DDLBYP

TO 2.4V

TO 5V

LDO

15k

2.048V

REFERENCE

2× REFERENCE

BUFFER

R

0.63× BUFFER

4R

CHAIN

SDO

RDL/SDI

SCK

+

–

IN

+

SPI

PORT

R

18-BIT SAMPLING ADC

4R

–

CNV

BUSY

CONTROL LOGIC

GND

233618 BD01

TiMing DiagraM

Conversion Timing Using the Serial Interface

CHAIN, RDL/SDI = 0

CNV

CONVERT

NAP

BUSY

SCK

HOLD

ACQUIRE

D17 D16 D15 D2 D1 D0

SDO

233618 TD01

233618f

9

For more information www.linear.com/LTC2336-18

LTC2336-18

applicaTions inForMaTion

OVERVIEꢁ

withREFBUF=ꢁ.ꢀ96V.Theidealtransferfunctionisshown

in Figure 2. The output data is in 2’s complement format.

The LTC2336-18 is a low noise, high speed 18-bit succes-

siveapproximationregister(SAR)ADCwithfullydifferential

inputs.Operatingfromasingle5Vsupply,theLTC2336-18

has a 1ꢀ.2ꢁV true bipolar input range, making it ideal for

high voltage applications which require a wide dynamic

range. The LTC2336-18 achieves ꢁLSB INL maximum,

no missing codes at 18-bits and 1ꢀꢀdB SNR.

ANALOG INPUT

The analog inputs of the LTC2336-18 are fully differential

to maximize the signal swing that can be digitized. The

analog inputs can be modeled by the equivalent circuit

shown in Figure 3. The back-to-back diodes at the inputs

form clamps that provide ESD protection. Each input

drives a resistor divider network that has a total imped-

ance of 2kΩ. The resistor divider network attenuates and

level shifts the ±2.5 • REFBUF true bipolar signal swing of

each input to the ꢀ-REFBUF input signal swing of the ADC

TheLTC2336-18hasanonboardsingle-shotcapablereference

buffer and low drift (2ꢀppm/°C max) 2.ꢀꢁ8V temperature-

compensated reference. The LTC2336-18 also has a high

speed SPI-compatible serial interface that supports 1.8V,

2.5V, 3.3V and 5V logic while also featuring a daisy-chain

mode. The fast 25ꢀksps throughput with no cycle latency

makes the LTC2336-18 ideally suited for a wide variety

of high speed applications. An internal oscillator sets the

conversion time, easing external timing considerations. The

LTC2336-18 dissipates only 28mW and automatically naps

between conversions, leading to reduced power dissipation

that scales with the sampling rate. A sleep mode is also pro-

vided to reduce the power consumption of the LTC2336-18

to 3ꢀꢀμW for further power savings during inactive periods.

core. In the acquisition phase, ꢁ5pF (C ) from the sam-

IN

pling CDAC in series with approximately 5ꢀΩ (R ) from

ON

the on-resistance of the sampling switch is connected to

011...111

BIPOLAR

ZERO

011...110

000...001

000...000

111...111

111...110

CONVERTER OPERATION

100...001

100...000

FSR = +FS – –FS

1LSB = FSR/262144

The LTC2336-18 operates in two phases. During the

acquisition phase, the charge redistribution capacitor

D/A converter (CDAC) is connected to the outputs of

–1 0V

LSB

1

LSB

–FSR/2

FSR/2 – 1LSB

+

–

the resistor divider networks that pins IN and IN drive

to sample an attenuated and level-shifted version of the

differential analog input voltage as shown in Figure 3. A

rising edge on the CNV pin initiates a conversion. Dur-

ing the conversion phase, the 18-bit CDAC is sequenced

throughasuccessiveapproximationalgorithm,effectively

comparing the sampled input with binary-weighted frac-

INPUT VOLTAGE (V)

233618 F02

Figure 26 LTC233ꢀ-18 Transfer Function

0.63 • V

REFBUF

C

45pF

IN

R

50Ω

400Ω

ON

1.6k

+

–

IN

tions of the reference voltage (e.g. V

/2, V

/ꢁ

REFBUF

… V

/2621ꢁꢁ) using the differential comparator. At

REFBUF

0.63 • V

BIAS

REFBUF

the end of conversion, the CDAC output approximates the

sampledanaloginput.TheADCcontrollogicthenprepares

the 18-bit digital output code for serial transfer.

VOLTAGE

C

45pF

IN

R

50Ω

400Ω

ON

1.6k

IN

TRANSFER FUNCTION

233618 F03

The LTC2336-18 digitizes the full-scale voltage of ±5 •

Figure 36 The Equivalent Circuit for the Differential

Analog Input of the LTC233ꢀ-18

18

REFBUF into 2 levels, resulting in an LSB size of 156µV

233618f

10

For more information www.linear.com/LTC2336-18

LTC2336-18

applicaTions inForMaTion

the output of the resistor divider network. Any unwanted

signal that is common to both inputs will be reduced by

the common mode rejection of the ADC core and resistor

divider network. The inputs of the ADC core draw a current

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

spike while charging the C capacitors during acquisition.

IN

INPUT DRIVE CIRCUITS

A low impedance source can directly drive the high im-

pedance inputs of the LTC2336-18 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

is important even for DC inputs, because the ADC inputs

draw a current spike when entering acquisition.

Single-Ended-to-Differential Conversion

Forsingle-endedinputsignals,asingle-ended-to-differen-

tialconversioncircuitmustbeusedtoproduceadifferential

signal at the inputs of the LTC2336-18. The LT1ꢁ69 high

speed dual operational amplifier is recommended for per-

formingsingle-ended-to-differentialconversionsasshown

in Figure 5a. In this case, the first amplifier is configured

as a unity gain buffer and the single-ended input signal

directly drives the high impedance input of this amplifier.

Figure5bshowstheresultingFFT whentheLT1ꢁ69isused

to drive the LTC2336-18 in this configuration.

For best performance, a buffer amplifier should be used to

drive the analog inputs of the LTC2336-18. The amplifier

provides low output impedance to minimize gain error

and allows for fast settling of the analog signal during

the acquisition phase. It also provides isolation between

the signal source and the ADC inputs which draw a small

current spike during acquisition.

LT1469

OUT1

OUT2

1

7

3

2

+

–

Input Filtering

10ꢀ24ꢁ

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Noisy input signals should be filtered prior

to the buffer amplifier input with a low bandwidth filter to

minimizenoise.Thesimple1-poleRClowpassfiltershown

in Figure ꢁ is sufficient for many applications.

5

6

+

–

10ꢀ24ꢁ

4ꢀ99k

233618 F05a

Figure 5a6 LT1±ꢀ9 Converting a ±1062±V Single-Ended

Signal to a ±206±8V Differential Input Signal

The input resistor divider network, sampling switch on-

0

SNR = 100dB

resistance (R ) and the sample capacitor (C ) form a

ON

IN

–20

–40

THD = –115dB

SINAD = 99.9dB

SFDR = –118dB

second lowpass filter that limits the input bandwidth to

the ADC core to 7MHz. A buffer amplifier with a low noise

density must be selected to minimize the degradation of

the SNR over this bandwidth.

–60

–80

–100

–120

–140

–160

–180

SINGLE-ENDED

INPUT SIGNAL

+

IN

500Ω

LTC2336-18

–

6600pF

0

25

50

75

100

125

233618 F04

SINGLE-ENDED-

TO-DIFFERENTIAL

DRIVER

FREQUENCY (kHz)

233618 F05b

BW = 48kHz

Figure 5b6 128k Point FFT Plot with f_IN= 2kHz

for Circuit Shown in Figure 5a

Figure ±6 Input Signal Chain

233618f

11

For more information www.linear.com/LTC2336-18

LTC2336-18

applicaTions inForMaTion

Fully Differential Inputs

Internal Reference with Internal Buffer

The LTC2336-18 has an on-chip, low noise, low drift

(2ꢀppm/°C max), temperature compensated bandgap

reference that is factory trimmed to 2.ꢀꢁ8V. It is internally

connected to a reference buffer as shown in Figure 7a and

is available at REFIN (Pin 8). REFIN should be bypassed to

GNDwitha1ꢀꢀnFceramiccapacitortominimizenoise.The

reference buffer gains the REFIN voltage by 2 to ꢁ.ꢀ96V at

REFBUF (Pin 7). So the input range is 1ꢀ.2ꢁV, as shown

in Table 1. Bypass REFBUF to GND with at least a ꢁ7μF

ceramic capacitor (X7R, 1ꢀV, 121ꢀ size) to compensate

the reference buffer and minimize noise.

To achieve the full distortion performance of the

LTC2336-18,alowdistortionfullydifferentialsignalsource

driven through the LT1ꢁ69 configured as two unity gain

buffers as shown in Figure 6 can be used to get the full

data sheet THD specification of –115dB.

LT1469

3

2

+

–

1

7

10ꢀ24ꢁ

5

6

+

–

10ꢀ24ꢁ

233618 F06

15k

REFIN

BANDGAP

Figure ꢀ6 LT1±ꢀ9 Buffering a Fully Differential Signal Source

REFERENCE

100nF

REFBUF

ADC REFERENCE

REFERENCE

BUFFER

There are three ways of providing the ADC reference. The

first is to use both the internal reference and reference

buffer. The second is to externally overdrive the internal

reference and use the internal reference buffer. The third

is to disable the internal reference buffer and overdrive

the REFBUF pin from an external source. The following

tables give examples of these cases and the resulting

bipolar input ranges.

6.5k

47µF

6.5k

LTC2336-18

GND

233618 F07a

Figure 7a6LTC233ꢀ-18 Internal Reference Circuit

External Reference with Internal Buffer

Table 16 Internal Reference with Internal Buffer

If more accuracy and/or lower drift is desired, REFIN

can be easily overdriven by an external reference since

a 15k resistor is in series with the reference as shown

in Figure 7b. REFIN can be overdriven in the range from

1.25V to 2.ꢁV. The resulting voltage at REFBUF will be

2 • REFIN. So the input range is ±5 • REFIN, as shown

in Table 2. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

manyapplications.Withitssmallsize,lowpower,andhigh

accuracy, the LTC6655-2.ꢀꢁ8 is well suited for use with

the LTC2336-18 when overdriving the internal reference.

The LTC6655-2.ꢀꢁ8 offers ꢀ.ꢀ25% (max) initial accuracy

and 2ppm/°C (max) temperature coefficient for high pre-

cision applications. The LTC6655-2.ꢀꢁ8 is fully specified

over the H-grade temperature range and complements

the extended temperature range of the LTC2336-18 up to

125°C.BypassingtheLTC6655-2.ꢀꢁ8witha2.7μFto1ꢀꢀμF

ceramiccapacitorclosetotheREFINpinisrecommended.

233618f

REFIN

REFBUF

BIPOLAR INPUT RANGE

2.ꢀꢁ8V

ꢁ.ꢀ96V

1ꢀ.2ꢁV

Table 26 External Reference with Internal Buffer

REFIN

(OVERDRIVE)

REFBUF

BIPOLAR INPUT RANGE

1.25V (Min)

2.ꢀꢁ8V

2.5V

ꢁ.ꢀ96V

ꢁ.8V

6.25V

1ꢀ.2ꢁV

12V

2.ꢁV (Max)

Table 36 External Reference Unbuffered

REFIN

REFBUF

(OVERDRIVE)

BIPOLAR INPUT RANGE

ꢀV

2.5V (Min)

5V (Max)

6.25V

12.5V

12

For more information www.linear.com/LTC2336-18

LTC2336-18

applicaTions inForMaTion

15k

REFIN

BANDGAP

REFERENCE

2.7µF

REFBUF

REFERENCE

BUFFER

REFERENCE

BUFFER

47µF

LTC6655-2.048

6.5k

47µF

LTC6655-5

6.5k

LTC2336-18

GND

233618 F07b

233618 F07c

Figure7b6 Using the LTCꢀꢀ55-260±8 as an External Reference

Figure 7c6 Overdriving REFBUF Using the LTCꢀꢀ55-5

External Reference Unbuffered

reference that must be considered since any deviation in

the voltage at REFBUF will affect the accuracy of the output

code. If an external reference is used to overdrive REFBUF,

the fast settling LTC6655-5 reference is recommended.

The internal reference buffer can also be overdriven from

2.5V to 5V with an external reference at REFBUF as shown

in Figure 7c. So the input ranges are 6.25V to 12.5V,

respectively, as shown in Table 3. To do so, REFIN must

be grounded to disable the reference buffer. A 13k resis-

tor loads the REFBUF pin when the reference buffer is

disabled. To maximize the input signal swing and cor-

responding SNR, the LTC6655-5 is recommended when

overdrivingREFBUF.TheLTC6655-5offersthesamesmall

size, accuracy, drift and extended temperature range as

the LTC6655-2.ꢀꢁ8. By using a 5V reference, an SNR of

1ꢀ2dB can be achieved. Bypassing the LTC6655-5 with

a ꢁ7μF ceramic capacitor (X5R, ꢀ8ꢀ5 size) close to the

REFBUF pin is recommended.

Internal Reference Buffer Transient Response

Foroptimumtransientperformance,theinternalreference

buffer should be used. The internal reference buffer uses a

proprietarydesignthatresultsinanoutputvoltagechange

atREFBUFoflessthan1LSBwhenrespondingtoasudden

burst of conversions. This makes the internal reference

bufferoftheLTC2336-18trulysingle-shotcapablesincethe

first sample taken after idling will yield the same result as

a sample taken after the transient response of the internal

reference buffer has settled. Figure 9 shows the transient

responses of the LTC2336-18 with the internal reference

buffer and with the internal reference buffer overdriven by

the LTC6655-5, both with a bypass capacitance of ꢁ7μF.

TheREFBUFpinoftheLTC2336-18drawsacharge(Q

)

CONV

fromtheexternalbypasscapacitorduringeachconversion

cycle. If the internal reference buffer is overdriven, the

external reference must provide all of this charge with a

DYNAMIC PERFORMANCE

DC current equivalent to I

= Q

/t . Thus, the

REFBUF

CONV CYC

DC current draw of REFBUF depends on the sampling rate

and output code. In applications where a burst of samples

is taken after idling for long periods, as shown in Figure 8,

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

ratedthroughput.Byapplyingalowdistortionsinewaveand

analyzingthedigitaloutputusinganFFT algorithm,theADC’s

spectralcontentcanbeexaminedforfrequenciesoutsidethe

I

quickly goes from approximately 39ꢀµA to a maxi-

REFBUF

mumofꢀ.6mAforREFBUF=5Vat25ꢀksps.ThisstepinDC

current draw triggers a transient response in the external

CNV

IDLE

PERIOD

IDLE

PERIOD

233618 F08

Figure 86 CNV ꢁaveform Showing Burst Sampling

233618f

13

For more information www.linear.com/LTC2336-18

LTC2336-18

applicaTions inForMaTion

2

that the LTC2336-18 achieves a typical SNR of 1ꢀꢀdB at

a 25ꢀkHz sampling rate with a 2kHz input.

INTERNAL REFERENCE BUFFER

0

Total Harmonic Distortion (THD)

–2

TotalHarmonicDistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

EXTERNAL SOURCE ON REFBUF

–4

–6

–8

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

0

100 200 300 400 500 600 700 800 9001000

TIME (µs)

2

V2²+ V3²+ Vꢁ²+…+ V_N

233618 F09

THD= 2ꢀlog

Figure 96 Transient Response of the LTC233ꢀ-18

V1

fundamental. The LTC2336-18 provides guaranteed tested

limits for both AC distortion and noise measurements.

where V1 is the RMS amplitude of the fundamental

frequency and V2 through V are the amplitudes of the

N

second through Nth harmonics.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure1ꢀshowsthattheLTC2336-18achieves

a typical SINAD of 1ꢀꢀdB at a 25ꢀkHz sampling rate with

a 2kHz input.

POꢁER CONSIDERATIONS

The LTC2336-18 provides two power supply pins: the 5V

power supply (V ), and the digital input/output interface

DD

power supply (OV ). The flexible OV supply allows the

DD

LTC2336-18tocommunicatewithanydigitallogicoperat-

ingbetween1.8Vand5V,including2.5Vand3.3Vsystems.

Power Supply Sequencing

The LTC2336-18 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2336-18

has a power-on reset (POR) circuit that will reset the

LTC2336-18 at initial power-up or whenever the power

supply voltage drops below 2V. Once the supply voltage

reenters the nominal supply voltage range, the POR will

re-initialize the ADC. No conversions should be initiated

until 2ꢀꢀμs after a POR event to ensure the re-initialization

period has ended. Any conversions initiated before this

time will produce invalid results.

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 1ꢀ shows

0

SNR = 100.3dB

–20

–40

THD = –117dB

SINAD = 100.2dB

SFDR = –118dB

–60

–80

–100

–120

–140

–160

–180

TIMING AND CONTROL

CNV Timing

0

25

50

75

100

125

FREQUENCY (kHz)

233618 F10

The LTC2336-18 conversion is controlled by CNV. A ris-

ing edge on CNV will start a conversion and power up

233618f

Figure 106 32k Point FFT of the LTC233ꢀ-18

14

For more information www.linear.com/LTC2336-18

LTC2336-18

applicaTions inForMaTion

6

5

4

3

2

1

0

the LTC2336-18. Once a conversion has been initiated,

it cannot be restarted until the conversion is complete.

For optimum performance, CNV should be driven by a

clean low jitter signal. Converter status is indicated by the

BUSY output which remains high while the conversion is

in progress. To ensure that no errors occur in the digitized

results, any additional transitions on CNV should occur

within ꢁꢀns from the start of the conversion or after the

conversion has been completed. Once the conversion has

completed, the LTC2336-18 powers down.

V

DD

OV

DD

0

50

100

150

200

250

SAMPLING FREQUENCY (kHz)

233618 F11

Acquisition

Figure 116 Power Supply Current of the LTC233ꢀ-18

Versus Sampling Rate6

AproprietarysamplingarchitectureallowstheLTC2336-18

to begin acquiring the input signal for the next conver-

sion 527ns after the start of the current conversion. This

extends the acquisition time to 3.ꢁ6ꢀµs, easing settling

requirementsandallowingtheuseofextremelylowpower

ADC drivers. (Refer to the Timing Diagram.)

standby current resulting in a power dissipation of 3ꢀꢀμW.

To enter sleep mode, toggle CNV twice with no intervening

rising edge on SCK. The part will enter sleep mode on the

falling edge of BUSY from the last conversion initiated. Once

in sleep mode, a rising edge on SCK will wake the part up.

Uponemergingfromsleepmode,waitt

secondsbefore

WAKE

Internal Conversion Clock

initiating a conversion to allow the reference and reference

buffertowakeupandchargethebypasscapacitorsatREFIN

andREFBUF.(RefertotheTimingDiagramssectionformore

detailed timing information about sleep mode.)

The LTC2336-18 has an internal clock that is trimmed to

achieve a maximum conversion time of 3µs.

Auto Nap Mode

The LTC2336-18 automatically enters nap mode after a

conversion has been completed and completely powers

up once a new conversion is initiated on the rising edge of

CNV. During nap mode, only the ADC core powers down

and all other circuits remain active. During nap, data from

thelastconversioncanbeclockedout. Theautonapmode

featurewillreducethepowerdissipationoftheLTC2336-18

as the sampling frequency is reduced. Since full power is

consumed only during a conversion, the ADC core of the

LTC2336-18remainspowereddownforalargerfractionof

DIGITAL INTERFACE

The LTC2336-18 has a serial digital interface. The flexible

OV supplyallowstheLTC2336-18tocommunicatewith

DD

any digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

The serial output data is clocked out on the SDO pin when

anexternalclockisappliedtotheSCKpinifSDOisenabled.

Clocking out the data after the conversion will yield the

best performance. With a shift clock frequency of at least

2ꢀMHz, a 25ꢀksps throughput is still achieved. The serial

output data changes state on the rising edge of SCK and

can be captured on the falling edge or next rising edge of

SCK. D17 remains valid till the first rising edge of SCK.

the conversion cycle (t ) at lower sample rates, thereby

CYC

reducing the average power dissipation which scales with

the sampling rate as shown in Figure 11.

Sleep Mode

The serial interface on the LTC2336-18 is simple and

straightforwardtouse.Thefollowingsectionsdescribethe

operationoftheLTC2336-18. Severalmodesareprovided

depending on whether a single or multiple ADCs share the

SPI bus or are daisy-chained.

The auto nap mode feature provides limited power savings

sinceonlytheADCcorepowersdown.To obtaingreaterpower

savings,theLTC2336-18providesasleepmode.Duringsleep

mode, the entire part is powered down except for a small

233618f

15

For more information www.linear.com/LTC2336-18

LTC2336-18

TiMing DiagraMs

Normal Mode, Single Device

shows a single LTC2336-18 operated in normal mode

with CHAIN and RDL/SDI tied to ground. With RDL/SDI

grounded, SDO is enabled and the MSB(D17) of the new

conversion data is available at the falling edge of BUSY.

This is the simplest way to operate the LTC2336-18.

When CHAIN = ꢀ, the LTC2336-18 operates in normal

mode. In normal mode, RDL/SDI enables or disables the

serial data output pin SDO. If RDL/SDI is high, SDO is in

highimpedance.IfRDL/SDIislow,SDOisdriven.Figure12

CONVERT

DIGITAL HOST

IRQ

CNV

CHAIN

BUSY

SDO

LTC2336-18

RDL/SDI

SCK

DATA IN

CLK

233618 F12a

NAP

CONVERT

NAP

CONVERT

ACQUIRE

CHAIN = 0

RDL/SDI = 0

t

CYC

t

CNVH

t

CNVL

CNV

t

HOLD

ACQ

t

= t

– t

ACQ CYC HOLD

t

CONV

BUSY

t

SCK

t

BUSYLH

t

QUIET

SCKH

1

2

3

16

17

18

SCK

SDO

t

SCKL

HSDO

t

DSDO

DSDOBUSYL

D17

D16

D15

D1

D0

233618 F12

Figure 126 Using a Single LTC233ꢀ-18 in Normal Mode

233618f

16

For more information www.linear.com/LTC2336-18

LTC2336-18

TiMing DiagraMs

Normal Mode, Multiple Devices

be used to allow only one LTC2336-18 to drive SDO at a

timeinordertoavoidbusconflicts. AsshowninFigure13,

the RDL/SDI inputs idle high and are individually brought

low to read data out of each device between conversions.

When RDL/SDI is brought low, the MSB of the selected

device is output onto SDO.

Figure 13 shows multiple LTC2336-18 devices operating

in normal mode (CHAIN = ꢀ) sharing CNV, SCK and SDO.

By sharing CNV, SCK and SDO, the number of required

signals to operate multiple ADCs in parallel is reduced.

Since SDO is shared, the RDL/SDI input of each ADC must

RDL

B

A

CONVERT

CNV

CHAIN

BUSY

SDO

IRQ

CHAIN

LTC2336-18

B

LTC2336-18

A

DIGITAL HOST

SDO

RDL/SDI

SCK

DATA IN

CLK

233618 F13a

NAP

CONVERT

NAP

CONVERT

ACQUIRE

CHAIN = 0

t

CNVL

CNV

t

HOLD

BUSY

t

CONV

t

BUSYLH

RDL/SDI

A

B

RDL/SDI

t

SCK

t

QUIET

SCKH

SCK

SDO

1

2

3

16

17

18

19

20

21

34

35

36

t

SCKL

HSDO

t

DIS

DSDO

t

EN

Hi-Z

D17

D16

D15

D1

A

D0

A

D17

D16

D15

D1

B

D0

B

A

B

233618 F13

Figure 136 Normal Mode with Multiple Devices Sharing CNV, SCK, and SDO

233618f

17

For more information www.linear.com/LTC2336-18

LTC2336-18

TiMing DiagraMs

Chain Mode, Multiple Devices

may limitthe numberoflinesneeded to interface to a large

number of converters. Figure 1ꢁ shows an example with

two daisy-chained devices. The MSB of converter A will

appear at SDO of converter B after 18 SCK cycles. The

MSB of converter A is clocked in at the SDI/RDL pin of

converter B on the rising edge of the first SCK.

When CHAIN = OV , the LTC2336-18 operates in

DD

chain mode. In chain mode, SDO is always enabled and

RDL/SDI serves as the serial data input pin (SDI) where

daisy-chain data output from another ADC can be input.

This is useful for applications where hardware constraints

CONVERT

OV

DD

CNV

CHAIN

DIGITAL HOST

LTC2336-18

RDL/SDI

SDO

RDL/SDI

BUSY

SDO

IRQ

A

B

DATA IN

SCK

CLK

233618 F14a

NAP

ACQUIRE

CONVERT

NAP

ACQUIRE

CONVERT

CHAIN = OV

DD

RDL/SDI = 0

A

t

CYC

t

CNVL

CNV

t

HOLD

BUSY

t

CONV

t

BUSYLH

SCK

t

SCKCH

t

QUIET

SCKH

1

2

3

16

17

18

19

20

34

35

36

t

SCKL

t

HSDO

SSDISCK

t

DSDO

HSDISCK

SDO = RDL/SDI

A

B

D17

D16

D15

D1

D0

A

t

DSDOBUSYL

D17

D15

D1

B

D17

D16

D1

D0

A

SDO

B

A

B

233618 F14

Figure 1±6 Chain Mode Timing Diagram

233618f

18

For more information www.linear.com/LTC2336-18

LTC2336-18

TiMing DiagraMs

Sleep Mode

lastconversioninitiated.Onceinsleepmode,arisingedge

on SCK will wake the part up. Upon emerging from sleep

To entersleepmode, toggleCNVtwicewithnointervening

rising edge on SCK as shown in Figure 15. The part will

enter sleep mode on the falling edge of BUSY from the

mode, wait t

seconds before initiating a conversion

WAKE

to allow the reference and reference buffer to wake up

and charge the bypass capacitors at REFIN and REFBUF.

NAP AND

ACQUIRE

CHAIN = DON’T CARE

NAP

RDL/SDI = DON’T CARE

CONVERT

SLEEP

CONVERT

ACQUIRE

t

WAKE

t

CNVH

ACQ

CNV

t

HOLD

t

CONV

BUSY

t

BUSYLH

SCK

NAP AND

ACQUIRE

CHAIN = DON’T CARE

RDL/SDI = DON’T CARE

CONVERT

SLEEP

CONVERT

t

WAKE

CNVH

CNV

t

CONV

BUSY

t

BUSYLH

SCK

233618 F15

Figure 156 Sleep Mode Timing Diagram

233618f

19

For more information www.linear.com/LTC2336-18

LTC2336-18

boarD layouT

To obtain the best performance from the LTC2336-18 a

printedcircuitboard(PCB)isrecommended.Layoutforthe

PCB should ensure the digital and analog signal lines are

separated as much as possible. In particular, care should

be taken not to run any digital clocks or signals alongside

analog signals or underneath the ADC.

Recommended Layout

ThefollowingisanexampleofarecommendedPCBlayout.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC19ꢀ8, the

evaluation kit for the LTC2336-18.

Partial Top Silkscreen

Partial Layer 1 Component Side

233618f

20

For more information www.linear.com/LTC2336-18

LTC2336-18

boarD layouT

Partial Layer 2 Ground Plane

Partial Layer 3 Power Plane

Partial Layer ± Bottom Layer

233618f

21

For more information www.linear.com/LTC2336-18

LTC2336-18

boarD layouT

Partial Schematic of Demoboard

5

3

1

3

C V C

S S V

4

5

3

8

1

3

N I F R E

P

B Y D V D L ₁

C H A I

8

7

B F U F R E

N

0 1

D V D O

D V D

5 1

2

N D G

6 1

6

N D G

3

5

3

8

4

233618f

22

For more information www.linear.com/LTC2336-18

LTC2336-18

package DescripTion

Please refer to http://www6linear6com/designtools/packaging/ for the most recent package drawings6

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev A)

0.889 ±0.127

(.035 ±.005)

5.10

3.20 – 3.45

(.201)

(.126 – .136)

MIN

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

0.50

(.0197)

BSC

0.305 ±0.038

(.0120 ±.0015)

TYP

0.280 ±0.076

(.011 ±.003)

REF

16151413121110

9

RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

DETAIL “A”

0.254

4.90 ±0.152

(.193 ±.006)

(.010)

0° – 6° TYP

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

1 2 3 4 5 6 7 8

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

MSOP (MS16) 0213 REV A

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

233618f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

23

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC2336-18

LTC2336-18

Typical applicaTion

LT1±ꢀ9 Configured to Convert a ±1062±V Single-Ended Signal to a ±206±8V Differential Signal

15V

10.24V

0V

8

5V

2

3

–

+

–10.24V

V

10.24V

0V

–10.24V

DD

1

7

+

–

IN

LTC2336-18

LT1469

4.99k

6

5

–

+

REFBUF

47µF

REFIN

10.24V

0V

–10.24V

100nF

4

4.99k

–15V

233618 TA02

relaTeD parTs

PART NUMBER

ADCs

DESCRIPTION

COMMENTS

LTC2379-18/LTC2378-18/ 18-Bit, 1.6Msps/1Msps/5ꢀꢀksps/25ꢀksps

LTC2377-18/LTC2376-18 Serial, Low Power ADC

2.5V Supply, Differential Input, 1ꢀ1.2dB SNR, 5V Input Range, DGC,

Pin-Compatible Family in MSOP-16 and ꢁmm × 3mm DFN-16 Packages

LTC238ꢀ-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/5ꢀꢀksps/25ꢀksps

LTC2377-16/LTC2376-16 Serial, Low Power ADC

2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC,

Pin-Compatible Family in MSOP-16 and ꢁmm × 3mm DFN-16 Packages

LTC2369-18/LTC2368-18/ 18-Bit, 1.6Msps/1Msps/5ꢀꢀksps/25ꢀksps

LTC2367-18/LTC236ꢁ-18 Serial, Low Power ADC

2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dB SNR, ꢀV to 5V Input

Range, Pin-Compatible Family in MSOP-16 and ꢁmm × 3mm DFN-16 Packages

LTC237ꢀ-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/5ꢀꢀksps/25ꢀksps

LTC2367-16/LTC236ꢁ-16 Serial, Low Power ADC

2.5V Supply, Pseudo-Differential Unipolar Input, 9ꢁdB SNR, ꢀV to 5V Input

Range, Pin-Compatible Family in MSOP-16 and ꢁmm × 3mm DFN-16 Packages

LTC2389-18/LTC2389-16 18-Bit/16-Bit, 2.5Msps Parallel/Serial ADC

5V Supply, Pin-Configurable Input Range, 99.8dB/96dB SNR, Parallel or Serial

I/O 7mm × 7mm LQFP-ꢁ8 and QFN-ꢁ8 Packages

LTC16ꢀ9

16-Bit, 2ꢀꢀksps Serial ADC

1ꢀV, Configurable Unipolar/Bipolar Input, Single 5V Supply, SSOP-28 and

SO-2ꢀ Packages

LTC16ꢀ6/LTC16ꢀ5

16-Bit, 2ꢀꢀksps/1ꢀꢀksps Parallel ADCs

1ꢀV, 75mW/55mW 5V Pin Compatible ADCs

LTC1859/LTC1858/

LTC1857

16-/1ꢁ-/12-Bit, 8-Channel 1ꢀꢀksps Serial

ADCs

1ꢀV, SoftSpanꢂ, Single-Ended or Differential Inputs, Single 5V Supply,

SSOP-28 Package

DACs

LTC2756/LTC2757

18-Bit, Single Serial/Parallel I

SoftSpan

OUT

1LSB INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm LQFP-ꢁ8

Package

DAC

LTC26ꢁ1

LTC263ꢀ

References

LTC6655

16-Bit/1ꢁ-Bit/12-Bit Single Serial V

DAC

1LSB INL /DNL, MSOP-8 Package, ꢀV to 5V Output

OUT

12-Bit/1ꢀ-Bit/8-Bit Single V

DACs

1LSB INL (12 Bits), Internal Reference, SC7ꢀ 6-Pin Package

OUT

Precision Low Drift Low Noise Buffered

Reference

5V/2.5V/2.ꢀꢁ8V/1.2V, 2ppm/°C, ꢀ.25ppm Peak-to-Peak Noise, MSOP-8 Package

5V/2.5V/2.ꢀꢁ8V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package

LTC6652

Precision Low Drift Low Noise Buffered

Reference

Amplifiers

LT1ꢁ68/LT1ꢁ69

Single/Dual 9ꢀMHz, 22V/μs, 16-Bit Accurate Low Input Offset: 75μV/125µV

Op Amp

233618f

LT 0913 • PRINTED IN USA

LinearTechnology Corporation

163ꢀ McCarthy Blvd., Milpitas, CA 95ꢀ35-7ꢁ17

24

For more information www.linear.com/LTC2336-18

(ꢁꢀ8)ꢁ32-19ꢀꢀ FAX: (ꢁꢀ8) ꢁ3ꢁ-ꢀ5ꢀ7 www.linear.com/LTC2336-18

●

 LINEAR TECHNOLOGY CORPORATION 2013


型号：	LTC2336CMS-18#PBF
厂家：	Linear
描述：	LTC2336-18 - 18-Bit, 250ksps, ±10.24V True Bipolar, Fully Differential Input ADC with 100dB SNR; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管转换器
文件：	总24页 (文件大小：750K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2336CMS-18#PBF [Linear]

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