LTC2335-16 [Linear]
Buffered Octal, 16-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range;
| 型号： | LTC2335-16 |
| 厂家： | 
Linear |
| 描述： | Buffered Octal, 16-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range |
| 文件： | 总40页 (文件大小：3268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2358-16
Buffered Octal, 16-Bit, 200ksps/Ch
Differential 10.24V ADC with
30V Common Mode Range
P-P
FEATURES
DESCRIPTION
TheLTC®2358-16isa16-bit, lownoise8-channelsimulta-
neous sampling successive approximation register (SAR)
ADC with buffered differential, wide common mode range
picoamp inputs. Operating from a 5V low voltage supply,
flexible high voltage supplies, and using the internal refer-
enceandbuffer,eachchannelofthisSoftSpanTM ADCcanbe
independently configured on a conversion-by-conversion
basis to accept 10.24V, 0V to 10.24V, 5.12V, or 0V to
5.12V signals. Individual channels may also be disabled
to increase throughput on the remaining channels.
n
200ksps per Channel Throughput
n
Eight Buffered Simultaneous Sampling Channels
n
500pA/12nA Max Input Leakage at 85°C/125°C
n
1LSB INL (Maximum, 10.24V Range)
n
Guaranteed 16-Bit, No Missing Codes
n
Differential, Wide Common Mode Range Inputs
n
Per-Channel SoftSpan Input Ranges:
10.24V, 0V to 10.24V, 5.12V, 0V to 5.12V
12.5V, 0V to 12.5V, 6.25V, 0V to 6.25V
n
94.2dB Single-Conversion SNR (Typical)
n
−111dB THD (Typical) at f = 2kHz
128dB CMRR (Typical) at f = 200Hz
IN
IN
The integrated picoamp-input analog buffers, wide input
commonmoderangeand128dB CMRRoftheLTC2358-16
allow the ADC to directly digitize a variety of signals us-
ing minimal board space and power. This input signal
flexibility, combined with 1LSB INL, no missing codes
at 16 bits, and 94.2dB SNR, makes the LTC2358-16 an
ideal choice for many high voltage applications requiring
wide dynamic range.
n
n
n
n
n
n
n
Rail-to-Rail Input Overdrive Tolerance
Integrated Reference and Buffer (4.096V)
SPI CMOS (1.8V to 5V) and LVDS Serial I/O
Internal Conversion Clock, No Cycle Latency
219mW Power Dissipation (27mW/Ch Typical)
48-Lead (7mm x 7mm) LQFP Package
TheLTC2358-16supportspin-selectableSPICMOS(1.8V
to 5V) and LVDS serial interfaces. Between one and eight
lanes of data output may be employed in CMOS mode,
allowing the user to optimize bus width and throughput.
APPLICATIONS
n
Programmable Logic Controllers
Industrial Process Control
Power Line Monitoring
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 7705765, 7961132, 8319673, 9197235.
n
n
Test and Measurement
TYPICAL APPLICATION
ꢂꢊꢇ
ꢀꢁꢂꢃꢄ
ꢊꢇ
ꢀꢁꢂꢃꢄ
ꢂꢁꢆꢇ ꢈꢉ ꢊꢇ
ꢀꢁꢂꢃꢄ
Integral Nonlinearity vs
Output Code and Channel
ꢅꢁꢅꢃꢄ
ꢇ
ꢑꢍꢉꢌ ꢉR ꢏꢇꢚꢌ
ꢝꢖꢉ ꢝꢟꢈꢐRꢄAꢑꢐ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢇ
ꢇ
ꢉꢇ
ꢚꢚ
ꢛꢘꢄꢄꢐRꢌ
ꢠ
ꢋ
ꢄꢘꢏꢏꢜ
ꢚꢝꢄꢄꢐRꢐꢟꢈꢝAꢏ
ꢠꢊꢇ
ꢏꢇꢚꢌꢖCMOS
ꢑꢑ
ꢚꢚ
ꢚꢚꢏꢛꢜꢎ
ꢀ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
ARꢛꢝꢈRARꢜ
ꢎꢚ
ꢝꢟꢀ
ꢝꢟꢀ
Aꢀꢀ ꢁꢂAꢃꢃꢄꢀꢅ
ꢌꢖꢗ
ꢌꢖꢗ
ꢌꢖꢗ
ꢌꢖꢗ
ꢌꢖꢗ
ꢌꢖꢗ
ꢌꢖꢗ
ꢌꢖꢗ
ꢠꢂꢀꢇ
ꢏꢈꢑꢅꢓꢊꢆꢣꢂꢔ
ꢀꢇ
ꢀꢇ
ꢌꢚꢉꢀ
ꢋꢂꢀꢇ
ꢋꢊꢇ
ꢂꢔꢣꢛꢝꢈ
ꢍꢘꢙ
ꢌꢚꢉꢢ
ꢌꢑꢒꢉ
ꢌꢑꢒꢝ
ꢌꢚꢝ
CS
ꢛꢘꢌꢜ
ꢑꢟꢇ
ꢌAR Aꢚꢑ
ꢘꢟꢝꢎꢉꢏAR
ꢈRꢘꢐ ꢛꢝꢎꢉꢏAR
ꢠꢂꢀꢇ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃ
ꢠꢂꢀꢇ
ꢀꢇ
ꢀꢇ
ꢌAꢍꢎꢏꢐ
ꢑꢏꢉꢑꢒ
ꢋꢂꢀꢇ
ꢋꢂꢀꢇ
ꢠ
ꢋ
ꢝꢟꢢ
ꢝꢟꢢ
ꢠ
ꢋ
ꢇ
Rꢐꢄꢛꢘꢄ
Rꢐꢄꢝꢟ
ꢞꢟꢚ
ꢐꢐ
ꢚꢝꢄꢄꢐRꢐꢟꢈꢝAꢏ ꢝꢟꢎꢘꢈꢌ ꢝꢟ ꢖꢝꢟ ꢡꢝꢈꢗ
ꢡꢝꢚꢐ ꢝꢟꢎꢘꢈ ꢑꢉꢍꢍꢉꢟ ꢍꢉꢚꢐ RAꢟꢞꢐ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢅꢓꢊꢆꢂꢔ ꢈAꢀꢂꢕ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢆ
ꢤꢢꢃꢄ
ꢀꢁꢂꢃꢄ
ꢐꢝꢞꢗꢈ ꢛꢘꢄꢄꢐRꢐꢚ
ꢌꢝꢍꢘꢏꢈAꢟꢐꢉꢘꢌ
ꢌAꢍꢎꢏꢝꢟꢞ ꢑꢗAꢟꢟꢐꢏꢌ
ꢀꢁꢂꢃꢄꢅ ꢆAꢇꢄꢈ
ꢀꢁꢂꢃꢄ
ꢋꢂꢊꢇ
Rev A
1
Document Feedback
For more information www.analog.com
LTC2358-16
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
ꢝꢛꢖ ꢐꢊꢒꢞ
Supply Voltage (V ) .....................–0.3V to (V + 40V)
CC
EE
Supply Voltage (V )................................ –17.4V to 0.3V
EE
Supply Voltage Difference (V – V )......................40V
CC
EE
Supply Voltage (V )..................................................6V
DD
Supply Voltage (OV )................................................6V
DD
ꢌ
ꢊꢋꢅ
ꢊꢋꢅ
ꢊꢋꢄ
ꢊꢋꢄ
ꢊꢋꢃ
ꢊꢋꢃ
ꢊꢋꢂ
ꢊꢋꢂ
ꢊꢋꢁ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢂꢅ ꢘꢏꢛꢆ
Internal Regulated Supply Bypass (V
Analog Input Voltage
) ... (Note 3)
ꢍ
ꢌ
ꢍ
ꢌ
ꢍ
ꢌ
ꢍ
ꢌ
ꢍ
ꢌ
DDLBYP
ꢂꢄ ꢘꢏꢛ ꢙꢘꢏꢛꢅ
ꢍ
ꢂꢃ ꢘꢏꢛ ꢙꢘꢏꢛꢄ
ꢌ
ꢂꢂ ꢘꢑꢜꢛ ꢙꢘꢏꢛꢃ
ꢂꢁ ꢘꢑꢜꢛ ꢙꢘꢑꢜꢛ
+
–
+
–
ꢍ
IN0 to IN7 ,
ꢂꢀ ꢛꢐ
ꢏꢏ
IN0 to IN7 (Note 4) .........(V – 0.3V) to (V + 0.3V)
EE
CC
ꢂꢉ ꢎꢋꢏ
ꢌ
ꢁꢈ ꢘꢑꢜꢊ ꢙꢘꢑꢜꢊ
REFIN.................................................... –0.3V to 2.8V
ꢍ
ꢁꢇ ꢘꢑꢜꢊ ꢙꢘꢏꢛꢂ
ꢌ
ꢊꢋꢁ ꢀꢉ
ꢁꢆ ꢘꢏꢊ ꢙꢘꢏꢛꢁ
REFBUF, CNV (Note 5) ............. –0.3V to (V + 0.3V)
DD
DD
DD
ꢌ
ꢍ
ꢊꢋꢀ ꢀꢀ
ꢁꢅ ꢘꢏꢊ ꢙꢘꢏꢛꢀ
ꢍ
Digital Input Voltage (Note 5)..... –0.3V to (OV + 0.3V)
ꢊꢋꢀ ꢀꢁ
ꢁꢄ ꢘꢏꢛꢉ
Digital Output Voltage (Note 5).. –0.3V to (OV + 0.3V)
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC2358C................................................ 0°C to 70°C
LTC2358I .............................................–40°C to 85°C
LTC2358H.......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
ꢗꢟ ꢖAꢑꢜAꢎꢒ
ꢃꢇꢠꢗꢒAꢏ ꢡꢆꢢꢢ × ꢆꢢꢢꢣ ꢖꢗAꢘꢝꢊꢑ ꢗꢤꢓꢖ
T
JMAX
= 150°C, θ = 53°C/W
JA
ORDER INFORMATION http://www.linear.com/product/LTC2358-16#orderinfo
TRAY
PART MARKING*
LTC2358LX-16
LTC2358LX-16
LTC2358LX-16
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2358CLX-16#PBF
LTC2358ILX-16#PBF
LTC2358HLX-16#PBF
48-Lead (7mm × 7mm) Plastic LQFP
48-Lead (7mm × 7mm) Plastic LQFP
48-Lead (7mm × 7mm) Plastic LQFP
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
Rev A
2
For more information www.analog.com
LTC2358-16
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 6)
SYMBOL
V +
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Absolute Input Range
(Note 7)
V
V
+ 4
V
CC
– 4
V
IN
EE
+
+
(IN0 to IN7 )
V –
IN
Absolute Input Range
(Note 7)
+ 4
V
CC
– 4
V
EE
–
–
(IN0 to IN7 )
l
l
l
l
l
l
l
V + – V – Input Differential Voltage
SoftSpan 7: 2.5 • V
SoftSpan 6: 2.5 • V
Range (Note 7)
–2.5 •V
2.5 •V
REFBUF
2.5 •V
REFBUF
V
V
V
V
V
V
V
IN
IN
REFBUF
REFBUF
SoftSpan 5: 0V to 2.5 • V
SoftSpan 4: 0V to 2.5 • V
REFBUF
REFBUF
Range
/1.024 Range (Note 7)
–2.5 •V
/1.024
2.5 •V
/1.024
REFBUF
0
0
Range (Note 7)
REFBUF
REFBUF
REFBUF
REFBUF
/1.024 Range (Note 7)
2.5 •V
/1.024
REFBUF
SoftSpan 3: 1.25 • V
SoftSpan 2: 1.25 • V
SoftSpan 1: 0V to 1.25 • V
Range (Note 7)
–1.25 •V
1.25 •V
REFBUF
REFBUF
/1.024
/1.024 Range (Note 7)
–1.25 •V
1.25 •V
1.25 •V
REFBUF
/1.024
REFBUF
0
REFBUF
Range (Note 7)
REFBUF
l
V
Input Common Mode Voltage (Note 7)
Range
V
EE
+ 4
V – 4
CC
V
CM
l
V + – V – Input Differential Overdrive
(Note 8)
−(V − V
)
EE
(V − V
CC
)
V
IN
IN
CC
EE
Tolerance
l
l
I
Input Overdrive
V + > V , V – > V (Note 8)
10
mA
mA
OVERDRIVE
IN
IN
CC IN
CC
Current Tolerance
V + < V , V – < V (Note 8)
0
IN
EE IN
EE
I
Analog Input Leakage Current
5
pA
pA
nA
l
l
C-Grade and I-Grade
H-Grade
500
12
R
Analog Input Resistance
Analog Input Capacitance
For Each Pin
>1000
3
GΩ
pF
IN
C
IN
l
CMRR
Input Common Mode
Rejection Ratio
V + = V − = 18V 200Hz Sine
100
1.3
128
dB
IN
IN
P-P
l
l
l
V
V
CNV High Level Input Voltage
CNV Low Level Input Voltage
CNV Input Current
V
V
IHCNV
ILCNV
INCNV
0.5
10
I
V
= 0V to V
–10
μA
IN
DD
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN
16
TYP
MAX
UNITS
Bits
l
l
Resolution
No Missing Codes
16
Bits
Transition Noise
SoftSpans 7 and 6: 10.24V and 10V Ranges
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges
SoftSpans 3 and 2: 5.12V and 5V Ranges
SoftSpan 1: 0V to 5.12V Range
0.35
0.7
0.5
1.1
LSB
RMS
RMS
RMS
RMS
LSB
LSB
LSB
l
l
l
l
INL
Integral Linearity Error
SoftSpans 7 and 6: 10.24V and 10V Ranges (Note 10)
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges (Note 10)
SoftSpans 3 and 2: 5.12V and 5V Ranges (Note 10)
SoftSpan 1: 0V to 5.12V Range (Note 10)
–1
–1.25
–1
0.3
0.4
0.4
0.5
1
1.25
1
LSB
LSB
LSB
LSB
–1.5
1.5
l
l
DNL
ZSE
Differential Linearity Error (Note 11)
–0.9
0.1
160
4
0.9
LSB
μV
Zero-Scale Error
(Note 12)
–700
700
Zero-Scale Error Drift
Full-Scale Error
μV/°C
%FS
l
FSE
V
V
= 4.096V (REFBUF Overdriven) (Note 12)
= 4.096V (REFBUF Overdriven) (Note 12)
−0.1
0.025
2.5
0.1
REFBUF
Full-Scale Error Drift
ppm/°C
REFBUF
Rev A
3
For more information www.analog.com
LTC2358-16
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 9, 13)
SYMBOL PARAMETER
CONDITIONS
SoftSpans 7 and 6: 10.24V and 10V Ranges, f = 2kHz
MIN
TYP
MAX
UNITS
l
l
l
l
SINAD
SNR
Signal-to-(Noise +
91.5
86.7
88.8
83.5
94.1
89.6
91.6
86.5
dB
dB
dB
dB
IN
Distortion) Ratio
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, f = 2kHz
IN
SoftSpans 3 and 2: 5.12V and 5V Ranges, f = 2kHz
IN
SoftSpan 1: 0V to 5.12V Range, f = 2kHz
IN
l
l
l
l
Signal-to-Noise Ratio
SoftSpans 7 and 6: 10.24V and 10V Ranges, f = 2kHz
91.7
86.8
88.9
83.6
94.2
89.7
91.6
86.5
dB
dB
dB
dB
IN
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, f = 2kHz
IN
SoftSpans 3 and 2: 5.12V and 5V Ranges, f = 2kHz
IN
SoftSpan 1: 0V to 5.12V Range, f = 2kHz
IN
l
l
l
l
THD
Total Harmonic Distortion
SoftSpans 7 and 6: 10.24V and 10V Ranges, f = 2kHz
–111
–107
–113
–113
–101
–99
–101
–100
dB
dB
dB
dB
IN
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, f = 2kHz
IN
SoftSpans 3 and 2: 5.12V and 5V Ranges, f = 2kHz
IN
SoftSpan 1: 0V to 5.12V Range, f = 2kHz
IN
l
l
l
l
SFDR
Spurious Free Dynamic
Range
SoftSpans 7 and 6: 10.24V and 10V Ranges, f = 2kHz
101
99
102
102
113
107
113
113
dB
dB
dB
dB
IN
SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, f = 2kHz
IN
SoftSpans 3 and 2: 5.12V and 5V Ranges, f = 2kHz
IN
SoftSpan 1: 0V to 5.12V Range, f = 2kHz
IN
Channel-to-Channel
Crosstalk
One Channel Converting 18V 200Hz Sine in 10.24V Range,
−109
dB
P-P
Crosstalk to All Other Channels
–3dB Input Bandwidth
Aperture Delay
6
1
MHz
ns
Aperture Delay Matching
Aperture Jitter
150
3
ps
ps
RMS
Transient Response
Full-Scale Step, 0.005% Settling
420
ns
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
2.048
5
MAX
2.053
20
UNITS
V
V
REFIN
Internal Reference Output Voltage
Internal Reference Temperature Coefficient
Internal Reference Line Regulation
Internal Reference Output Impedance
REFIN Voltage Range
2.043
l
(Note 14)
ppm/°C
mV/V
kΩ
V
DD
= 4.75V to 5.25V
0.1
20
V
REFIN Overdriven (Note 7)
1.25
2.2
V
REFIN
REFERENCE BUFFER CHARACTERISTICS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
4.091
2.5
TYP
MAX
4.101
5
UNITS
l
l
V
Reference Buffer Output Voltage REFIN Overdriven, V
= 2.048V
REFIN
4.096
V
V
REFBUF
REFBUF Voltage Range
REFBUF Input Impedance
REFBUF Load Current
REFBUF Overdriven (Notes 7, 15)
V
REFIN
= 0V, Buffer Disabled
13
kΩ
l
I
V
V
= 5V, 8 Channels Enabled (Notes 15, 16)
= 5V, Acquisition or Nap Mode (Note 15)
1.5
0.39
1.9
mA
mA
REFBUF
REFBUF
REFBUF
Rev A
4
For more information www.analog.com
LTC2358-16
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
0.8 • OV
–10
TYP
MAX
UNITS
CMOS Digital Inputs and Outputs
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
IH
IL
DD
0.2 • OV
10
DD
I
V
IN
= 0V to OV
DD
μA
pF
V
IN
C
V
V
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
5
IN
l
l
l
I
I
= –500μA
= 500μA
OV – 0.2
DD
OH
OL
OUT
0.2
10
V
OUT
I
I
I
V
OUT
V
OUT
V
OUT
= 0V to OV
= 0V
–10
μA
mA
mA
OZ
DD
–50
50
SOURCE
SINK
= OV
DD
LVDS Digital Inputs and Outputs
l
l
V
Differential Input Voltage
200
90
350
600
125
mV
ID
R
On-Chip Input Termination
Resistance
CS = 0V, V
= 1.2V
106
10
Ω
MΩ
ID
ICM
DD
CS = OV
l
l
l
l
l
V
Common-Mode Input Voltage
Common-Mode Input Current
Differential Output Voltage
0.3
–10
275
1.1
1.2
2.2
10
V
μA
mV
V
ICM
I
V + = V – = 0V to OV
IN IN DD
ICM
V
V
R = 100Ω Differential Termination
L
350
1.2
425
1.3
10
OD
Common-Mode Output Voltage
Hi-Z Output Leakage Current
R = 100Ω Differential Termination
L
OCM
I
V
OUT
= 0V to OV
DD
–10
μA
OZ
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN
7.5
TYP
MAX UNITS
l
l
l
l
V
V
V
V
Supply Voltage
38
0
V
V
V
V
CC
EE
Supply Voltage
–16.5
10
− V
Supply Voltage Difference
Supply Voltage
38
CC
EE
4.75
5.00
5.25
DD
VCC
l
l
l
l
I
Supply Current
200ksps Sample Rate, 8 Channels Enabled (Note 17)
Acquisition Mode (Note 17)
Nap Mode
4.6
8.5
2.9
6
5.3
9.8
3.3
15
mA
mA
mA
μA
Power Down Mode
l
l
l
l
I
Supply Current
200ksps Sample Rate, 8 Channels Enabled (Note 17)
Acquisition Mode (Note 17)
Nap Mode
–5.5
–9.8
–3.5
–15
–4.5
–8
–2.8
–4
mA
mA
mA
μA
VEE
Power Down Mode
CMOS I/O Mode
l
OV
Supply Voltage
Supply Current
1.71
5.25
V
DD
l
l
l
l
l
l
I
200ksps Sample Rate, 8 Channels Enabled
15.6
13.8
2.1
18
16
2.7
2.4
275
500
mA
mA
mA
mA
μA
VDD
200ksps Sample Rate, 8 Channels Enabled, V
Acquisition Mode
= 5V (Note 15)
REFBUF
Nap Mode
1.7
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
106
106
µA
Rev A
5
For more information www.analog.com
LTC2358-16
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
l
l
l
I
Supply Current
200ksps Sample Rate, 8 Channels Enabled (C = 25pF)
1.7
1
1
2.6
20
20
mA
μA
μA
OVDD
L
Acquisition or Nap Mode
Power Down Mode
l
l
l
l
l
P
D
Power Dissipation
200ksps Sample Rate, 8 Channels Enabled
Acquisition Mode
219
258
94
0.68
0.68
259
308
114
1.9
3
mW
mW
mW
mW
mW
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
LVDS I/O Mode
l
OV
Supply Voltage
Supply Current
2.375
5.25
V
DD
l
l
l
l
l
l
I
200ksps Sample Rate, 8 Channels Enabled
18.4
16.8
3.7
20.7
19.2
4.5
4.1
275
500
mA
mA
mA
mA
μA
VDD
200ksps Sample Rate, 8 Channels Enabled, V
Acquisition Mode
= 5V (Note 15)
REFBUF
Nap Mode
3.4
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
106
106
µA
l
l
l
I
Supply Current
200ksps Sample Rate, 8 Channels Enabled (R = 100Ω)
7
7
1
8.5
8.0
20
mA
mA
μA
OVDD
L
Acquisition or Nap Mode (R = 100Ω)
L
Power Down Mode
l
l
l
l
l
P
D
Power Dissipation
200ksps Sample Rate, 8 Channels Enabled
Acquisition Mode
245
284
120
0.68
0.68
287
337
143
1.9
3
mW
mW
mW
mW
mW
Nap Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
l
l
l
f
Maximum Sampling Frequency
8 Channels Enabled
7 Channels Enabled
6 Channels Enabled
5 Channels Enabled
4 Channels Enabled
3 Channels Enabled
2 Channels Enabled
1 Channel Enabled
200
225
250
300
350
425
550
800
ksps
ksps
ksps
ksps
ksps
ksps
ksps
ksps
SMPL
l
l
l
l
l
l
l
l
t
Time Between Conversions
8 Channels Enabled, f
7 Channels Enabled, f
6 Channels Enabled, f
5 Channels Enabled, f
4 Channels Enabled, f
3 Channels Enabled, f
2 Channels Enabled, f
= 200ksps
= 225ksps
= 250ksps
= 300ksps
= 350ksps
= 425ksps
= 550ksps
5000
4444
4000
3333
2855
2350
1815
1250
ns
ns
ns
ns
ns
ns
ns
ns
CYC
SMPL
SMPL
SMPL
SMPL
SMPL
SMPL
SMPL
1 Channel Enabled, f
= 800ksps
SMPL
l
t
t
Conversion Time
Acquisition Time
N Channels Enabled, 1 ≤ N ≤ 8
450•N
500•N
550•N
ns
CONV
ACQ
l
l
l
l
l
l
l
l
8 Channels Enabled, f
7 Channels Enabled, f
6 Channels Enabled, f
5 Channels Enabled, f
4 Channels Enabled, f
3 Channels Enabled, f
2 Channels Enabled, f
= 200ksps
= 225ksps
= 250ksps
= 300ksps
= 350ksps
= 425ksps
= 550ksps
570
564
670
553
625
670
685
670
980
924
980
813
835
830
795
730
ns
ns
ns
ns
ns
ns
ns
SMPL
SMPL
SMPL
SMPL
SMPL
SMPL
SMPL
(t
= t
– t
– t
)
BUSYLH
ACQ
CYC
CONV
1 Channel Enabled, f
= 800ksps
ns
SMPL
Rev A
6
For more information www.analog.com
LTC2358-16
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
40
TYP
MAX
UNITS
ns
l
l
l
l
l
l
t
t
t
t
t
t
t
CNV High Time
CNVH
CNVL
BUSYLH
QUIET
PDH
CNV Low Time
750
ns
CNV to BUSY Delay
Digital I/O Quiet Time from CNV
PD High Time
C = 25pF
L
30
ns
20
40
40
ns
ns
PD Low Time
ns
PDL
REFBUF Wake-Up Time
C
= 47μF, C = 0.1μF
REFIN
200
ms
WAKE
REFBUF
CMOS I/O Mode
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
SCKI Period
(Notes 18, 19)
10
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKI
SCKI High Time
SCKIH
SCKI Low Time
4
SCKIL
SDI Setup Time from SCKI
SDI Hold Time from SCKI
SDO Data Valid Delay from SCKI
SDO Remains Valid Delay from SCKI
SDO to SCKO Skew
(Note 18)
(Note 18)
2
SSDISCKI
HSDISCKI
DSDOSCKI
HSDOSCKI
SKEW
1
C = 25pF (Note 18)
L
7.5
1
C = 25pF (Note 18)
L
1.5
–1
0
(Note 18)
0
SDO Data Valid Delay from BUSY
Bus Enable Time After CS
Bus Relinquish Time After CS
C = 25pF (Note 18)
L
DSDOBUSYL
EN
(Note 18)
(Note 18)
15
15
DIS
LVDS I/O Mode
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
SCKI Period
(Note 20)
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKI
SCKI High Time
(Note 20)
1.5
1.5
1.2
–0.2
SCKIH
SCKI Low Time
(Note 20)
SCKIL
SDI Setup Time from SCKI
SDI Hold Time from SCKI
SDO Data Valid Delay from SCKI
SDO Remains Valid Delay from SCKI
SDO to SCKO Skew
(Notes 11, 20)
(Notes 11, 20)
(Notes 11, 20)
(Notes 11, 20)
(Note 11)
SSDISCKI
HSDISCKI
DSDOSCKI
HSDOSCKI
SKEW
6
1
–0.4
0
0
0.4
SDO Data Valid Delay from BUSY
Bus Enable Time After CS
Bus Relinquish Time After CS
(Note 11)
DSDOBUSYL
EN
50
15
DIS
Rev A
7
For more information www.analog.com
LTC2358-16
ADC TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 11: Guaranteed by design, not subject to test.
Note 12: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
the offset voltage measured from –0.5LSB when the output code flickers
between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
error for these SoftSpan ranges is the worst-case deviation of the first and
last code transitions from ideal and includes the effect of offset error. For
unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage
measured from 0.5LSB when the output code flickers between 0000 0000
0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan
ranges is the worst-case deviation of the last code transition from ideal
and includes the effect of offset error.
Note 13: All specifications in dB are referred to a full-scale input in the
relevant SoftSpan input range, except for crosstalk, which is referred to
the crosstalk injection signal amplitude.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 2: All voltage values are with respect to GND.
Note 3: V
is the output of an internal voltage regulator, and should
DDLBYP
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,
as described in the Pin Functions section. Do not connect this pin to any
external circuitry.
Note 4: When these pin voltages are taken below V or above V , they
EE
CC
will be clamped by internal diodes. This product can handle input currents
of up to 100mA below V or above V without latchup.
EE
CC
Note 5: When these pin voltages are taken below GND or above V or
DD
OV , they will be clamped by internal diodes. This product can handle
DD
currents of up to 100mA below ground or above V or OV without
DD
DD
latchup.
Note 15: When REFBUF is overdriven, the internal reference buffer must
be disabled by setting REFIN = 0V.
Note 6: –16.5V ≤ V ≤ 0V, 7.5V ≤ V ≤ 38V, 10V ≤ (V – V ) ≤ 38V,
EE
CC
CC
EE
V
DD
= 5V, unless otherwise specified.
Note 16: I
active channels.
varies proportionally with sample rate and the number of
REFBUF
Note 7: Recommended operating conditions.
Note 8: Exceeding these limits on any channel may corrupt conversion
Note 17: Analog input buffer supply currents from I
reduced outside the acquisition period. Refer to nap mode in Applications
Information section.
and I are
VCC
VEE
results on other channels. Driving an analog input above V on any
CC
channel up to 10mA will not affect conversion results on other channels.
Driving an analog input below V may corrupt conversion results on other
EE
channels. Refer to Applications Information section for further details.
Refer to Absolute Maximum Ratings section for pin voltage limits related
to device reliability.
Note 18: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V,
DD DD
and OV = 5.25V.
DD
Note 19: A t
period of 10ns minimum allows a shift clock frequency of
SCKI
Note 9: V = 15V, V = –15V, V = 5V, OV = 2.5V, f = 200ksps,
up to 100MHz for rising edge capture.
CC
EE
DD
DD
SMPL
internal reference and buffer, true bipolar input signal drive in bipolar
SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless
otherwise specified.
Note 20: V = 1.2V, V = 350mV for LVDS differential input pairs.
ICM
ID
Note 10: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
CMOS Timings
0.8 • OV
ꢀꢀ
ꢊ
ꢊ
ꢎꢏꢀꢐꢑ
0.2 • OV
ꢀꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢊ
ꢀꢋꢌAꢍ
ꢀꢋꢌAꢍ
ꢄꢅꢁꢆꢇꢈ ꢉꢂꢇ
0.8 • OV
0.2 • OV
0.8 • OV
0.2 • OV
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
LVDS Timings (Differential)
ꢀꢁꢂꢂꢃꢄ
ꢍ
ꢒꢓꢎꢔꢕ
ꢅꢁꢂꢂꢃꢄ
ꢂꢄ
ꢂꢄ
ꢍ
ꢍ
ꢎꢏꢐAꢑ
ꢎꢏꢐAꢑ
ꢁꢆꢇꢈꢉꢊ ꢋꢂꢉꢌ
ꢀꢁꢂꢂꢃꢄ
ꢅꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢅꢁꢂꢂꢃꢄ
Figure 1. Voltage Levels for Timing Specifications
Rev A
8
For more information www.analog.com
LTC2358-16
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
TYPICAL PERFORMANCE CHARACTERISTICS
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
vs Output Code and Channel
vs Output Code and Channel
vs Output Code and Channel
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
Aꢀꢀ RAꢁꢂꢃꢄ
Aꢀꢀ ꢁꢂAꢃꢃꢄꢀꢅ
ꢀ
ꢀ
ꢀ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
ꢀꢁꢂꢂꢃ ꢄꢅꢀꢀꢆRꢆꢇꢈꢅAꢂ ꢄRꢅꢉꢆ ꢊꢅꢇ ꢀ ꢁꢂꢃ ꢀ
Aꢀꢀ ꢁꢂAꢃꢃꢄꢀꢅ
Aꢀꢀ ꢁꢂAꢃꢃꢄꢀꢅ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢀ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢆ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢆ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢆ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢄ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢀ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢁ
Integral Nonlinearity
vs Output Code and Range
Integral Nonlinearity
vs Output Code and Range
Integral Nonlinearity
vs Output Code and Range
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
ꢀꢁꢂꢂꢃ ꢄꢅꢀꢀꢆRꢆꢇꢈꢅAꢂ ꢄRꢅꢉꢆ ꢊꢅꢇ ꢀ ꢁꢂꢃ ꢀ
ꢀꢁꢂꢃꢄꢅAR ꢆRꢂꢇꢈ ꢉꢂꢁ ꢀ ꢁꢂꢃ
ꢀꢁꢂ ꢃꢄAꢁꢁꢂꢅ
ꢀꢁꢂ ꢃꢄAꢁꢁꢂꢅ
ꢀꢁꢂ ꢃꢄAꢁꢁꢂꢅ
ꢀꢁꢂꢃꢄꢅꢆ Aꢇꢆ ꢀꢁꢅ
RAꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ Aꢆꢅ ꢀꢄ
ꢀꢁ ꢂꢃ ꢄꢅꢆꢇꢁ RAꢈꢉꢊ
RAꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂꢃꢄꢅ Aꢆꢅ ꢀꢄ
ꢀꢁꢂꢃꢄꢅꢆ Aꢇꢆ ꢀꢁꢅ
ꢀꢁ ꢂꢃ ꢄꢀꢅꢆꢇꢁ Aꢈꢉ
RAꢀꢁꢂꢃ
RAꢀꢁꢂꢃ
ꢀꢁ ꢂꢃ ꢄꢀꢁ RAꢅꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢀ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢆ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢆ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢆ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢂ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢅ
Integral Nonlinearity
vs Output Code
DC Histogram (Zero-Scale)
DC Histogram (Near Full-Scale)
ꢀꢁꢂꢂꢂꢂ
ꢀꢁꢂꢂꢂꢂ
ꢀꢁꢂꢂꢂꢂ
ꢀꢁꢂꢂꢂꢂ
ꢀꢁꢁꢁꢁꢁ
ꢀꢁꢁꢁꢁ
ꢀꢁꢁꢁꢁ
ꢀꢁꢁꢁꢁ
ꢀꢁꢁꢁꢁ
ꢀ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢂꢂꢂ
ꢀꢁꢂꢂꢂꢂ
ꢀꢁꢂꢂꢂꢂ
ꢀꢁꢂꢂꢂꢂ
ꢀꢁꢁꢁꢁꢁ
ꢀꢁꢁꢁꢁ
ꢀꢁꢁꢁꢁ
ꢀꢁꢁꢁꢁ
ꢀꢁꢁꢁꢁ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃ
ARꢀꢁꢂRARꢃ ꢄRꢁꢅꢆ
ꢀ
ꢀ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢂꢂꢁꢃ ꢂꢁꢄꢅ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢈꢉꢊꢋ ꢌꢍ ꢆꢇꢈꢉꢊꢋ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢆ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢃ
Rev A
9
For more information www.analog.com
LTC2358-16
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
TYPICAL PERFORMANCE CHARACTERISTICS
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.
32k Point Arbitrary Two-Tone FFT
fSMPL = 200kHz, IN+ = –7dBFS 2kHz
Sine, IN– = –7dBFS 3.1kHz Sine
32k Point FFT fSMPL = 200kHz,
fIN = 2kHz
32k Point FFT fSMPL = 200kHz,
fIN = 2kHz
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ARꢀꢁꢂRARꢃ ꢄRꢁꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀ
ꢀ
ꢀ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
ꢀꢁꢂꢂꢃ ꢄꢅꢀꢀꢆRꢆꢇꢈꢅAꢂ ꢄRꢅꢉꢆ ꢊꢅꢇ ꢀ ꢁꢂꢃ ꢀ
ꢀꢁꢂ
ꢀꢁR ꢂ ꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ ꢃ ꢄꢅꢅꢅꢆꢇ
ꢀꢁꢂAꢃ ꢄ ꢅꢆꢇꢈꢉꢊ
ꢀꢁꢂR ꢃ ꢄꢄꢅꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂR ꢃ ꢄꢄꢅꢆꢇ
ꢀꢁR ꢂ ꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ
ꢀꢁR ꢂ ꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ ꢃ ꢄꢅꢅꢆꢇꢈ
ꢀꢁꢂAꢃ ꢄ ꢅꢆꢇꢈꢉꢊ
ꢀꢁꢂR ꢃ ꢄꢅꢆꢇꢈ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢀ
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢄ
32k Point FFT fSMPL = 200kHz,
fIN = 2kHz
SNR, SINAD vs VREFBUF
,
THD, Harmonics vs VREFBUF
,
fIN = 2kHz
fIN = 2kHz
–105
–110
–115
–120
–125
–130
–135
ꢀ
ꢀꢁꢂ
ꢀꢁ
95
94
93
92
91
±2.5 • V
RANGE
ꢀꢁꢂꢃꢄꢅ RAꢆꢇ
REFBUF
±2.5 • V
RANGE
REFBUF
–
ꢀ
–
TRUE BIPOLAR DRIVE (IN = 0V)
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
TRUE BIPOLAR DRIVE (IN = 0V)
ꢀꢁꢂ
ꢀꢁR ꢂ ꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ ꢃ ꢄꢅꢅꢆꢇꢈ
ꢀꢁꢂAꢃ ꢄ ꢅꢆꢇꢈꢉꢊ
ꢀꢁꢂR ꢃ ꢄꢄꢅꢆꢇ
ꢀꢁR
ꢀꢁꢂ
ꢀꢁꢂAꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀRꢁ
2.5
3
3.5
4
4.5
5
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
2.5
3
3.5
4
4.5
5
REFBUF VOLTAGE (V)
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
REFBUF VOLTAGE (V)
235816 G15
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢁ
235816 G14
SNR, SINAD
vs Input Frequency
THD, Harmonics vs Input
Common Mode, fIN = 2kHz
THD vs Input Frequency
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀ
ꢀꢁ
ꢀꢁꢀ
ꢀꢁꢂꢂꢃ ꢄꢅꢀꢀꢆRꢆꢇꢈꢅAꢂ ꢄRꢅꢉꢆ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
ꢀꢁR
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂAꢃ
ꢀꢁꢂ
–11V ≤ V ≤ 11V
1kΩ
ꢀꢁ
10kΩ
ꢀꢁꢂRꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂRꢃꢄ
ꢀꢁꢂꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
50Ω SOURCE
±10.24V RANGE
–
TRUE BIPOLAR DRIVE (IN = 0V)
ꢀRꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢇꢆꢁ ꢇꢆꢈꢉ ꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢅ
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢃ
Rev A
10
For more information www.analog.com
LTC2358-16
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
TYPICAL PERFORMANCE CHARACTERISTICS
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.
SNR, SINAD vs Input Level,
fIN = 2kHz
CMRR vs Input Frequency
and Channel
Crosstalk vs Input Frequency
and Channel
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁ ꢀ ꢁꢂ ꢀ ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ ꢀ ꢁꢂ
Aꢀꢀ ꢁꢂAꢃꢃꢄꢀꢅ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ ꢀ ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢀ
Aꢀꢀ ꢁꢂAꢃꢃꢄꢀꢅ ꢁꢆꢃꢇꢄRꢈꢉꢃꢊ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁR
ꢀꢁꢂAꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁꢂ ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢆꢅ ꢈꢉꢊꢋꢌꢍ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢀꢄ
ꢀꢁꢂꢃꢄꢅ ꢆꢀꢇ
SNR, SINAD vs Temperature,
fIN = 2kHz
THD, Harmonics vs Temperature,
fIN = 2kHz
INL, DNL vs Temperature
ꢀꢁꢂꢃ
ꢀꢁꢂꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀ
ꢀ
ꢀ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇAR ꢈRꢄꢉꢂ ꢊꢄꢋ ꢀ ꢁꢂꢃ
Aꢀꢀ ꢁꢂAꢃꢃꢄꢀꢅ
ꢀꢁR
ꢀAꢁ ꢂꢃꢄ
ꢀꢁꢂ
ꢀAꢁ ꢂꢃꢄ
ꢀꢁꢂAꢃ
ꢀꢁꢂ
ꢀꢁꢂ ꢃꢂꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂ ꢁꢂꢃ
ꢀRꢁ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ ꢆꢀꢀ
ꢀꢁꢂꢃꢄꢅ ꢆꢀꢁ
ꢀꢁꢂꢃꢄꢅ ꢆꢀꢇ
Analog Input Leakage
Current vs Temperature
Positive Full-Scale Error vs
Temperature and Channel
Zero-Scale Error vs
Temperature and Channel
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢀꢀ
ꢀꢁꢀꢂꢃ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
Rꢀꢁꢂꢃꢁ ꢄꢅꢀRꢆRꢇꢅꢀꢈ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
Aꢀꢀ ꢁꢂAꢃꢃꢄꢀꢅ
ꢀꢁ AꢂAꢃꢄꢅ ꢆꢂꢇꢈꢉ ꢇꢆꢂ ꢉRAꢊꢋꢌ
ꢀꢁR ꢂAꢃꢄ ꢅꢆꢇꢈꢉ ꢊꢁꢋꢉAꢌꢂ
ꢀ
ꢀ ꢁꢂꢃꢄꢅꢆ
Rꢀꢁꢂꢃꢁ
Aꢀꢀ ꢁꢂAꢃꢃꢄꢀꢅ
ꢀꢁꢀꢂꢀ
ꢀ
ꢀꢁ ꢂ ꢃꢄ
ꢀꢁ ꢂ ꢃꢄꢅꢆ
ꢀꢁ ꢂ ꢃꢄꢅꢆ
ꢀꢁꢀꢂꢃ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢀꢀꢀ
ꢀ
ꢀꢁꢂꢁꢃꢄ
ꢀꢁꢂꢁꢃꢁ
ꢀꢁꢂꢁꢃꢄ
ꢀꢁꢂꢃꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ ꢆꢀꢂ
ꢀꢁꢂꢃꢄꢅ ꢆꢀꢅ
ꢀꢁꢂꢃꢄꢅ ꢆꢀꢇ
Rev A
11
For more information www.analog.com
LTC2358-16
TA = 25°C, VCC = +15V, VEE = –15V, VDD = 5V,
TYPICAL PERFORMANCE CHARACTERISTICS
OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.
Power-Down Current
vs Temperature
Supply Current vs Temperature
PSRR vs Frequency
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢁꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ ꢀ ꢁꢂ ꢀ ꢁꢂ
ꢀ
ꢀ
ꢀꢁꢁ
ꢀꢀ
ꢀ
ꢀꢁꢁ
ꢀꢁ
ꢀꢀ
ꢀ
ꢀꢁꢁ
ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢂ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢀꢂ
ꢀꢁ
ꢀ
ꢀꢁꢂꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀꢁꢂꢃꢄꢅ ꢆꢀꢃ
ꢀꢁꢂꢃꢄꢅ ꢆꢀꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢇ
Offset Error
vs Input Common Mode
Internal Reference Output
vs Temperature
Supply Current vs Sampling Rate
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄAꢅ ꢆꢇꢈꢉ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁ ꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂ ꢄ ꢃ ꢀ ꢁꢂ
ꢀꢀ
ꢀꢁ
ꢀꢀ
ꢀ
ꢀ
ꢀꢁꢁ
ꢀ
ꢀ ꢁꢂ ꢃꢄ ꢅꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀ ꢁꢂꢃꢄ ꢆ ꢅ ꢀ ꢁꢂꢃꢄꢅꢆ
ꢀ ꢁꢂꢃꢄꢅꢆ ꢇꢈ ꢂꢉꢄꢅꢆ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀAꢁꢂꢃꢄꢅꢆ ꢇRꢈꢉꢊꢈꢅꢋꢌ ꢍꢎꢏꢐꢑ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢇꢆꢁ ꢇꢆꢈꢉ ꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢀ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢁ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢄ
Power Dissipation vs Sampling
Rate, N-Channels Enabled
Step Response
(Large-Signal Settling)
Step Response
(Fine Settling)
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀ ꢁ ꢂ
ꢀ
ꢀꢁ ꢀ ꢁꢂꢂꢃꢂꢂꢂꢄꢅꢆꢇꢈ
ꢀ ꢁ ꢂ
ꢀꢁꢂARꢃ ꢄAꢅꢃ
ꢀꢁ
ꢀ
ꢀ ꢁ ꢂ
ꢀꢁ ꢀ ꢁꢂ
ꢀ ꢁ ꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀ ꢁꢂꢂꢃꢂꢂꢂꢄꢅꢆꢇꢈ ꢉꢊꢋARꢌ ꢍAꢎꢌ
ꢀ
ꢀꢁ ꢀ ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ ꢄAꢅ ꢆꢇꢈꢉ
ꢀ
ꢀ ꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ
ꢀꢁꢂꢂ
ꢀ
ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ
ꢀꢁꢂꢂ
ꢀ
ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ ꢀꢁꢁ
ꢀAꢁꢂꢃꢄꢅꢆ ꢇRꢈꢉꢊꢈꢅꢋꢌ ꢍꢎꢏꢐꢑ
ꢀꢁꢂꢂꢃꢄꢅꢆ ꢂꢄꢇꢁ ꢈꢉꢊꢋ
ꢀꢁꢂꢂꢃꢄꢅꢆ ꢂꢄꢇꢁ ꢈꢉꢊꢋ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢂ
ꢀꢁꢂꢃꢄꢅ ꢆꢁꢅ
Rev A
12
For more information www.analog.com
LTC2358-16
PIN FUNCTIONS
Pins that are the Same for All Digital I/O Modes
REFIN. With the buffer disabled, overdrive REFBUF with
an external reference voltage in the range of 2.5V to 5V.
When using the internal reference buffer, limit the loading
of any external circuitry connected to REFBUF to less than
200µA. Using a high input impedance amplifier to buffer
+
–
+
–
IN0 /IN0 toIN7 /IN7 (Pins14/13,12/11,10/9,8/7,6/5,
4/3,2/1,and48/47):PositiveandNegativeAnalogInputs,
Channels 0 to 7. The converter simultaneously samples
and digitizes (V + – V –) for all channels. Wide input
common mode range (V + 4V ≤ V ≤ V – 4V) and
IN
IN
EE
V
to any external circuits is recommended.
REFBUF
CM
CC
high common mode rejection allow the inputs to accept
a wide variety of signal swings. Full-scale input range is
determined by the channel’s SoftSpan configuration.
PD (Pin 22): Power Down Input. When this pin is brought
high, the LTC2358-16 is powered down and subsequent
conversion requests are ignored. If this occurs during a
conversion, the device powers down once the conversion
completes. If this pin is brought high twice without an
intervening conversion, an internal global reset is initi-
ated, equivalent to a power-on-reset event. Logic levels
GND (Pins 15, 18, 20, 30, 41, 44, 46): Ground. Solder
all GND pins to a solid ground plane.
V
(Pin 16): Positive High Voltage Power Supply. The
CC
range of V is 7.5V to 38V with respect to GND and 10V
are determined by OV .
CC
DD
to 38V with respect to V . Bypass V to GND close to
the pin with a 0.1μF ceramic capacitor.
EE
CC
LVDS/CMOS(Pin23):I/OModeSelect.TiethispintoOV
DD
to select LVDS I/O mode, or to ground to select CMOS I/O
V
(Pins 17, 45): Negative High Voltage Power Supply.
mode. Logic levels are determined by OV .
EE
DD
The range of V is 0V to –16.5V with respect to GND and
EE
CNV (Pin 24): Conversion Start Input. A rising edge on
this pin puts the internal sample-and-holds into the hold
mode and initiates a new conversion. CNV is not gated
by CS, allowing conversions to be initiated independent
of the state of the serial I/O bus.
–10V to –38V with respect to V . Connect Pins 17 and 45
CC
together and bypass the V network to GND close to Pin
EE
17 with a 0.1μF ceramic capacitor. In applications where
V
EE
is shorted to GND, this capacitor may be omitted.
REFIN(Pin19):BandgapReferenceOutput/ReferenceBuf-
ferInput.Aninternalbandgapreferencenominallyoutputs
2.048V on this pin. An internal reference buffer amplifies
BUSY (Pin 38): Busy Output. The BUSY signal indicates
that a conversion is in progress. This pin transitions low-
to-high at the start of each conversion and stays high until
the conversion is complete. Logic levels are determined
V
V
to create the converter master reference voltage
REFIN
= 2 • V
on the REFBUF pin. When using the
REFBUF
REFIN
by OV .
DD
internal reference, bypass REFIN to GND (Pin 20) close to
thepinwitha0.1μFceramiccapacitortofilterthebandgap
outputnoise. Ifmoreaccuracyisdesired, overdriveREFIN
with an external reference in the range of 1.25V to 2.2V.
Do not load this pin when internal reference is used.
V
(Pin40):Internal2.5VRegulatorBypassPin. The
DDLBYP
voltage on this pin is generated via an internal regulator
operating off of V . This pin must be bypassed to GND
DD
close to the pin with a 2.2μF ceramic capacitor. Do not
connect this pin to any external circuitry.
REFBUF (Pin 21): Internal Reference Buffer Output. An
internal reference buffer amplifies V
converter master reference voltage V
to create the
V
(Pins 42, 43): 5V Power Supply. The range of V
DD DD
REFIN
= 2 • V
is 4.75V to 5.25V. Connect Pins 42 and 43 together and
REFBUF
REFIN
on this pin, nominally 4.096V when using the internal
bandgapreference. BypassREFBUF to GND(Pin 20)close
to the pin with a 47μF ceramic capacitor. The internal ref-
erence buffer may be disabled by grounding its input at
bypass the V network to GND with a shared 0.1μF
ceramic capacitor close to the pins.
DD
Rev A
13
For more information www.analog.com
LTC2358-16
PIN FUNCTIONS
CMOS I/O Mode
LVDS I/O Mode
SDO0 to SDO7 (Pins 25, 26, 27, 28, 33, 34, 35, and 36):
CMOS Serial Data Outputs, Channels 0 to 7. The most
recent conversion result along with channel configuration
information is clocked out onto the SDO pins on each ris-
ing edge of SCKI. Output data formatting is described in
the Digital Interface section. Leave unused SDO outputs
SDO0, SDO7, SDI (Pins 25, 36, and 37): CMOS Serial
Data I/O. In LVDS I/O mode, these pins are Hi-Z.
+
–
SDI /SDI (Pins26/27):LVDSPositiveandNegativeSerial
+
–
Data Input. Differentially drive SDI /SDI with the desired
24-bitSoftSpanconfigurationword(seeTable1a),latched
+
–
on both the rising and falling edges of SCKI /SCKI . The
unconnected. Logic levels are determined by OV .
+
–
DD
SDI /SDI input pair is internally terminated with a 100Ω
SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with
the serial I/O clock. SCKI rising edges latch serial data in
on SDI and clock serial data out on SDO0 to SDO7. For
standard SPI bus operation, capture output data at the
receiver on rising edges of SCKI. SCKI is allowed to idle
differential resistor when CS is low.
+
–
SCKI /SCKI (Pins 28/29): LVDS Positive and Negative
+
–
Serial Clock Input. Differentially drive SCKI /SCKI with
+
–
the serial I/O clock. SCKI /SCKI rising and falling edges
+
–
latch serial data in on SDI /SDI and clock serial data out
either high or low. Logic levels are determined by OV .
+
–
+
–
DD
on SDO /SDO . Idle SCKI /SCKI low, including when
+
–
OV (Pin 31): I/O Interface Power Supply. In CMOS I/O
transitioning CS. The SCKI /SCKI input pair is internally
terminatedwitha100ΩdifferentialresistorwhenCSislow.
DD
mode, the range of OV is 1.71V to 5.25V. Bypass OV
DD
DD
to GND (Pin 30) close to the pin with a 0.1μF ceramic
OV (Pin 31): I/O Interface Power Supply. In LVDS I/O
DD
capacitor.
mode, therangeofOV is2.375Vto5.25V. BypassOV
DD
DD
SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising
edges trigger transitions on SCKO that are skew-matched
to the serial output data streams on SDO0 to SDO7. The
resulting SCKO frequency is half that of SCKI. Rising and
falling edges of SCKO may be used to capture SDO data
at the receiver (FPGA) in double data rate (DDR) fashion.
For standard SPI bus operation, SCKO is not used and
should be left unconnected. SCKO is forced low at the
to GND (Pin 30) close to the pin with a 0.1μF ceramic
capacitor.
+
–
SCKO /SCKO (Pins 32/33): LVDS Positive and Negative
+
–
Serial Clock Output. SCKO /SCKO outputs a copy of the
+
–
input serial I/O clock received on SCKI /SCKI , skew-
+
–
matchedwiththeserialoutputdatastreamonSDO /SDO .
+
–
Use the rising and falling edges of SCKO /SCKO to cap-
+
–
+
ture SDO /SDO data at the receiver (FPGA). The SCKO /
fallingedgeofBUSY. LogiclevelsaredeterminedbyOV .
–
DD
SCKO output pair must be differentially terminated with
SDI (Pin 37): CMOS Serial Data Input. Drive this pin with
the desired 24-bit SoftSpan configuration word (see Table
1a), latched on the rising edges of SCKI. If all channels
will be configured to operate only in SoftSpan 7, tie SDI
to OV . Logic levels are determined by OV .
a 100Ω resistor at the receiver (FPGA).
+
–
SDO /SDO (Pins 34/35): LVDS Positive and Negative
Serial Data Output. The most recent conversion result
along with channel configuration information is clocked
+
–
DD
DD
out onto SDO /SDO on both rising and falling edges of
+
–
+
–
CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI.
SCKI /SCKI , beginning with channel 0. The SDO /SDO
output pair must be differentially terminated with a 100Ω
resistor at the receiver (FPGA).
Logic levels are determined by OV .
DD
CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low, and is disabled and Hi-Z when
+
CS is high. CS also gates the external shift clock, SCKI /
–
SCKI .Theinternal100Ωdifferentialterminationresistors
+
–
+
–
ontheSCKI /SCKI andSDI /SDI inputpairsaredisabled
when CS is high. Logic levels are determined by OV .
DD
Rev A
14
For more information www.analog.com
LTC2358-16
CONFIGURATION TABLES
Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Independent Binary SoftSpan Codes SS[2:0] for Each
Channel Based on Desired Analog Input Range. Combine SoftSpan Codes to Form 24-Bit SoftSpan Configuration Word S[23:0]. Use
Serial Interface to Write SoftSpan Configuration Word to LTC2358-16, as shown in Figure 18
BINARY SoftSpan CODE
SS[2:0]
BINARY FORMAT OF
CONVERSION RESULT
ANALOG INPUT RANGE
2.5 • V
FULL SCALE RANGE
5 • V
111
110
101
100
011
010
001
000
Two’s Complement
Two’s Complement
Straight Binary
Straight Binary
Two’s Complement
Two’s Complement
Straight Binary
All Zeros
REFBUF
REFBUF
2.5 • V /1.024
REFBUF
5 • V
/1.024
REFBUF
0V to 2.5 • V
2.5 • V
REFBUF
REFBUF
0V to 2.5 • V /1.024
REFBUF
2.5 • V
/1.024
REFBUF
1.25 • V
2.5 • V
REFBUF
REFBUF
1.25 • V /1.024
REFBUF
2.5 • V
/1.024
REFBUF
0V to 1.25 • V
1.25 • V
REFBUF
Channel Disabled
REFBUF
Channel Disabled
Table 1b. Reference Configuration Table. The LTC2358-16 Supports Three Reference Configurations. Analog Input Range Scales with
the Converter Master Reference Voltage, VREFBUF
BINARY SoftSpan CODE
REFERENCE CONFIGURATION
V
REFIN
V
ANALOG INPUT RANGE
REFBUF
SS[2:0]
111
110
101
100
011
010
001
111
110
101
100
011
010
001
111
110
101
100
011
010
001
10.24V
10V
0V to 10.24V
0V to 10V
5.12V
Internal Reference with
Internal Buffer
2.048V
4.096V
5V
0V to 5.12V
6.25V
6.104V
0V to 6.25V
0V to 6.104V
3.125V
1.25V
(Min Value)
2.5V
3.052V
External Reference with
Internal Buffer
0V to 3.125V
11V
(REFIN Pin Externally
Overdriven)
10.742V
0V to 11V
0V to 10.742V
5.5V
2.2V
(Max Value)
4.4V
5.371V
0V to 5.5V
Rev A
15
For more information www.analog.com
LTC2358-16
CONFIGURATION TABLES
Table 1b. Reference Configuration Table (Continued). The LTC2358-16 Supports Three Reference Configurations. Analog Input Range
Scales with the Converter Master Reference Voltage, VREFBUF
BINARY SoftSpan CODE
REFERENCE CONFIGURATION
V
REFIN
V
ANALOG INPUT RANGE
REFBUF
SS[2:0]
111
110
101
100
011
010
001
111
110
101
100
011
010
001
6.25V
6.104V
0V to 6.25V
0V to 6.104V
3.125V
2.5V
0V
(Min Value)
External Reference
Unbuffered
3.052V
0V to 3.125V
12.5V
(REFBUF Pin
Externally Overdriven,
REFIN Pin Grounded)
12.207V
0V to 12.5V
0V to 12.207V
6.25V
5V
0V
(Max Value)
6.104V
0V to 6.25V
Rev A
16
For more information www.analog.com
LTC2358-16
FUNCTIONAL BLOCK DIAGRAM
CMOS I/O Mode
ꢋꢌꢖꢖꢓRꢀ
ꢜ
ꢅꢅ
ꢜ
ꢜ
ꢂꢜ
ꢁꢁ
ꢁꢁ
ꢁꢁꢔꢋꢍꢝ
ꢉ
LTC2358-16
ꢇꢈꢃ
ꢊ
ꢀꢕꢠ
ꢀꢕꢠ
ꢀꢕꢠ
ꢀꢕꢠ
ꢀꢕꢠ
ꢀꢕꢠ
ꢀꢕꢠ
ꢀꢕꢠ
ꢇꢈꢃ
ꢗꢞꢙꢜ
RꢓꢛꢌꢔAꢑꢂR
ꢉ
ꢀꢁꢂꢃ
ꢇꢈꢎ
ꢊ
ꢇꢈꢎ
ꢉ
ꢇꢈꢗ
ꢊ
ꢀꢁꢂꢄ
ꢀꢅꢆꢂ
ꢀꢁꢇ
ꢅꢒꢂꢀ
ꢀꢓRꢇAꢔ
ꢇꢕꢂ
ꢇꢈꢗ
ꢎꢏꢐꢋꢇꢑ
ꢀAR Aꢁꢅ
ꢎꢏ ꢋꢇꢑꢀ
ꢉ
ꢇꢈꢘ
ꢇꢈꢑꢓRꢖAꢅꢓ
ꢊ
ꢇꢈꢘ
ꢉ
ꢀꢅꢆꢇ
CS
ꢇꢈꢟ
ꢊ
ꢇꢈꢟ
ꢉ
ꢇꢈꢙ
ꢊ
ꢇꢈꢙ
ꢉ
ꢇꢈꢏ
RꢓꢖꢓRꢓꢈꢅꢓ
ꢋꢌꢖꢖꢓR
ꢊ
ꢇꢈꢏ
ꢗꢃꢢ
ꢋꢌꢀꢍ
ꢅꢂꢈꢑRꢂꢔ
ꢔꢂꢛꢇꢅ
ꢗꢞꢃꢟꢚꢜ
RꢓꢖꢓRꢓꢈꢅꢓ
ꢉ
ꢇꢈꢄ
ꢗ×
ꢊ
ꢇꢈꢄ
ꢜ
ꢛꢈꢁ
Rꢓꢖꢇꢈ
Rꢓꢖꢋꢌꢖ
ꢅꢈꢜ ꢝꢁ ꢔꢜꢁꢀꢕCMOS
ꢓꢓ
ꢗꢘꢙꢚꢎꢏ ꢋꢁꢃꢎ
LVDS I/O Mode
ꢒ
ꢅꢅ
ꢒ
ꢒ
ꢂꢒ
ꢁꢁ
ꢊꢋꢕꢕꢓRꢀ
ꢁꢁ
ꢁꢁꢑꢊꢌꢛ
ꢃ
LTC2358-16
ꢇꢈꢉ
ꢄ
ꢀꢔꢞ
ꢇꢈꢉ
ꢃ
ꢄ
ꢃ
ꢄ
ꢃ
ꢄ
ꢃ
ꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢅꢆꢂ
ꢀꢅꢆꢂ
ꢀꢁꢇ
ꢖꢜꢘꢒ
ꢃ
RꢓꢚꢋꢑAꢐꢂR
ꢇꢈꢍ
ꢄ
ꢀꢔꢞ
ꢀꢔꢞ
ꢀꢔꢞ
ꢀꢔꢞ
ꢀꢔꢞ
ꢀꢔꢞ
ꢀꢔꢞ
ꢇꢈꢍ
ꢃ
ꢇꢈꢖ
ꢑꢒꢁꢀ
ꢀꢓRꢇAꢑ
ꢇꢔꢂ
ꢄ
ꢇꢈꢖ
ꢍꢎꢏꢊꢇꢐ
ꢍꢎ ꢊꢇꢐꢀ
ꢃ
ꢀAR Aꢁꢅ
ꢇꢈꢗ
ꢀꢁꢇ
ꢇꢈꢐꢓRꢕAꢅꢓ
ꢄ
ꢇꢈꢗ
ꢀꢅꢆꢇ
ꢀꢅꢆꢇ
ꢃ
ꢇꢈꢝ
ꢄ
ꢇꢈꢝ
CS
ꢃ
ꢇꢈꢘ
ꢄ
ꢇꢈꢘ
ꢃ
ꢇꢈꢎ
RꢓꢕꢓRꢓꢈꢅꢓ
ꢊꢋꢕꢕꢓR
ꢄ
ꢇꢈꢎ
ꢖꢉꢢ
ꢊꢋꢀꢌ
ꢅꢂꢈꢐRꢂꢑ
ꢑꢂꢚꢇꢅ
ꢖꢜꢉꢝꢙꢒ
RꢓꢕꢓRꢓꢈꢅꢓ
ꢃ
ꢇꢈꢟ
ꢖ×
ꢄ
ꢇꢈꢟ
ꢒ
ꢚꢈꢁ
Rꢓꢕꢇꢈ
Rꢓꢕꢊꢋꢕ
ꢅꢈꢒ ꢛꢁ ꢑꢒꢁꢀꢔCMOS
ꢓꢓ
ꢖꢗꢘꢙꢍꢎ ꢊꢁꢉꢖ
Rev A
17
For more information www.analog.com
LTC2358-16
TIMING DIAGRAM
CMOS I/O Mode
CS ꢏ ꢐꢋ ꢏ ꢊ
ꢀAꢛꢐꢜꢒ ꢍ
ꢌꢍꢎ
ꢀAꢛꢐꢜꢒ ꢍ ꢝ ꢃ
ꢘꢖꢀꢙ
ꢀꢌꢚꢗ
ꢀꢋꢗ
ꢌꢑꢍꢎꢒRꢓ
AꢌꢕꢖꢗRꢒ
ꢉ ꢃꢊ ꢃꢃ ꢃꢁ ꢃꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢁꢊ ꢁꢃ ꢁꢁ ꢁꢂ ꢁꢄ
ꢃ
ꢁ
ꢂ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢋꢑꢍꢔꢓ ꢌARꢒ
ꢀꢁꢂ ꢀꢁꢁ ꢀꢁꢃ ꢀꢁꢊ ꢀꢃꢉ ꢀꢃꢈ ꢀꢃꢇ ꢀꢃꢆ ꢀꢃꢅ ꢀꢃꢄ ꢀꢃꢂ ꢀꢃꢁ ꢀꢃꢃ ꢀꢃꢊ ꢀꢉ ꢀꢈ ꢀꢇ ꢀꢆ ꢀꢅ ꢀꢄ ꢀꢂ ꢀꢁ ꢀꢃ ꢀꢊ
ꢀꢞꢟꢠꢀꢡꢢꢣ ꢌꢑꢍꢤꢗꢥꢖRAꢓꢗꢑꢍ ꢦꢑRꢋ ꢤꢑR ꢌꢑꢍꢎꢒRꢀꢗꢑꢍ ꢍ ꢝ ꢃ
ꢀꢌꢚꢑ
ꢀꢋꢑꢊ
ꢋꢑꢍꢔꢓ ꢌARꢒ
ꢋꢑꢍꢔꢓ ꢌARꢒ
ꢋꢃꢅ ꢋꢃꢄ ꢋꢃꢂ ꢋꢃꢁ ꢋꢃꢃ ꢋꢃꢊ ꢋꢉ ꢋꢈ ꢋꢇ ꢋꢆ ꢋꢅ ꢋꢄ ꢋꢂ ꢋꢁ ꢋꢃ ꢋꢊ
ꢌꢑꢍꢎꢒRꢀꢗꢑꢍ Rꢒꢀꢖꢜꢓ
ꢊ
ꢊ
ꢌꢁ ꢌꢃ ꢌꢊ ꢀꢀꢁ ꢀꢀꢃ ꢀꢀꢊ ꢋꢃꢅ
ꢌꢧAꢍꢍꢒꢜ ꢗꢋ ꢀꢞꢟꢠꢀꢡꢢꢣ
ꢌꢑꢍꢎꢒRꢀꢗꢑꢍ Rꢒꢀꢖꢜꢓ
ꢌꢧAꢍꢍꢒꢜ ꢊ
ꢌꢑꢍꢎꢒRꢀꢗꢑꢍ ꢍ
ꢌꢧAꢍꢍꢒꢜ ꢃ
ꢌꢑꢍꢎꢒRꢀꢗꢑꢍ ꢍ
ꢀꢋꢑꢇ
ꢋꢃꢅ ꢋꢃꢄ ꢋꢃꢂ ꢋꢃꢁ ꢋꢃꢃ ꢋꢃꢊ ꢋꢉ ꢋꢈ ꢋꢇ ꢋꢆ ꢋꢅ ꢋꢄ ꢋꢂ ꢋꢁ ꢋꢃ ꢋꢊ
ꢌꢑꢍꢎꢒRꢀꢗꢑꢍ Rꢒꢀꢖꢜꢓ
ꢊ
ꢊ
ꢌꢁ ꢌꢃ ꢌꢊ ꢀꢀꢁ ꢀꢀꢃ ꢀꢀꢊ ꢋꢃꢅ
ꢌꢧAꢍꢍꢒꢜ ꢗꢋ ꢀꢞꢟꢠꢀꢡꢢꢣ
ꢌꢑꢍꢎꢒRꢀꢗꢑꢍ Rꢒꢀꢖꢜꢓ
ꢌꢧAꢍꢍꢒꢜ ꢇ
ꢌꢑꢍꢎꢒRꢀꢗꢑꢍ ꢍ
ꢌꢧAꢍꢍꢒꢜ ꢊ
ꢌꢑꢍꢎꢒRꢀꢗꢑꢍ ꢍ
ꢁꢂꢅꢈꢃꢆ ꢓꢋꢊꢃ
LVDS I/O Mode
CS ꢓ ꢔꢋ ꢓ ꢊ
ꢀAꢐꢔꢞꢖ
ꢍ ꢟ ꢃ
ꢀAꢐꢔꢞꢖ ꢍ
ꢌꢍꢎ
ꢏꢌꢐꢑꢀꢒ
• • •
• • •
ꢛꢙꢀꢜ
AꢌꢘꢙꢚRꢖ
ꢏꢌꢐꢑꢀꢒ
ꢌꢑꢍꢎꢖRꢕ
ꢃ
ꢁ
ꢂ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢃꢊ ꢃꢃ ꢃꢁ ꢃꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢁꢊ ꢁꢃ ꢁꢁ ꢁꢂ ꢁꢄ ꢁꢅ ꢁꢆ
ꢃꢈꢆ ꢃꢈꢇ ꢃꢈꢈ ꢃꢈꢉ ꢃꢉꢊ ꢃꢉꢃ ꢃꢉꢁ
ꢀꢌꢝꢚ
ꢏꢞꢎꢋꢀꢒ
• • •
• • •
ꢀꢋꢚ
ꢏꢞꢎꢋꢀꢒ
ꢋꢑꢍꢗꢕ ꢌARꢖ
ꢀꢁꢂ ꢀꢁꢁ ꢀꢁꢃ ꢀꢁꢊ ꢀꢃꢉ ꢀꢃꢈ ꢀꢃꢇ ꢀꢃꢆ ꢀꢃꢅ ꢀꢃꢄ ꢀꢃꢂ ꢀꢃꢁ ꢀꢃꢃ ꢀꢃꢊ ꢀꢉ ꢀꢈ ꢀꢇ ꢀꢆ ꢀꢅ ꢀꢄ ꢀꢂ ꢀꢁ ꢀꢃ ꢀꢊ
ꢀꢠꢡꢢꢀꢣꢤꢥ ꢌꢑꢍꢦꢚꢧꢙRAꢕꢚꢑꢍ ꢨꢑRꢋ ꢦꢑR ꢌꢑꢍꢎꢖRꢀꢚꢑꢍ ꢍ ꢟ ꢃ
ꢀꢌꢝꢑ
ꢏꢞꢎꢋꢀꢒ
• • •
ꢀꢋꢑ
ꢏꢞꢎꢋꢀꢒ
ꢋꢑꢍꢗꢕ ꢌARꢖ ꢋꢃꢅ ꢋꢃꢄ ꢋꢃꢂ ꢋꢃꢁ ꢋꢃꢃ ꢋꢃꢊ ꢋꢉ ꢋꢈ ꢋꢇ ꢋꢆ ꢋꢅ ꢋꢄ ꢋꢂ ꢋꢁ ꢋꢃ ꢋꢊ
ꢌꢑꢍꢎꢖRꢀꢚꢑꢍ Rꢖꢀꢙꢞꢕ
ꢊ
ꢊ
ꢌꢁ ꢌꢃ ꢌꢊ ꢀꢀꢁ ꢀꢀꢃ ꢀꢀꢊ ꢋꢃꢅ ꢋꢃꢄ ꢋꢃꢂ • • • ꢊ ꢌꢁ ꢌꢃ ꢌꢊ ꢀꢀꢁ ꢀꢀꢃ ꢀꢀꢊ ꢋꢃꢅ
ꢌꢑꢍꢎꢖRꢀꢚꢑꢍ
Rꢖꢀꢙꢞꢕ
ꢌꢩAꢍꢍꢖꢞ ꢚꢋ ꢀꢠꢡꢢꢀꢣꢤꢥ
ꢌꢩAꢍꢍꢖꢞ ꢚꢋ ꢀꢠꢡꢢꢀꢣꢤꢥ
ꢌꢩAꢍꢍꢖꢞ ꢊ
ꢌꢑꢍꢎꢖRꢀꢚꢑꢍ ꢍ
ꢌꢩAꢍꢍꢖꢞ ꢃ
ꢌꢑꢍꢎꢖRꢀꢚꢑꢍ ꢍ
ꢌꢩAꢍꢍꢖꢞ ꢇ
ꢌꢑꢍꢎꢖRꢀꢚꢑꢍ ꢍ
ꢌꢩAꢍꢍꢖꢞ ꢊ
ꢌꢑꢍꢎꢖRꢀꢚꢑꢍ ꢍ
ꢁꢂꢅꢈꢃꢆ ꢕꢋꢊꢁ
Rev A
18
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
OVERVIEW
CONVERTER OPERATION
The LTC2358-16 is a 16-bit, low noise 8-channel simul-
taneous sampling successive approximation register
(SAR) ADC with buffered differential, wide common
mode range picoamp inputs. The ADC operates from a
5V low voltage supply and flexible high voltage supplies,
nominally 15V. Using the integrated low-drift reference
The LTC2358-16 operates in two phases. During the ac-
quisitionphase, thesamplingcapacitorsineachchannel’s
sample-and-hold (S/H) circuit connect to their respective
analog input buffers, which track the differential analog
input voltage (V + – V –). A rising edge on the CNV pin
IN
IN
transitions all channels’ S/H circuits from track mode to
hold mode, simultaneously sampling the input signals
on all channels and initiating a conversion. During the
conversion phase, each channel’s sampling capacitors
are connected, one channel at a time, to a 16-bit charge
redistribution capacitor D/A converter (CDAC). The CDAC
is sequenced through a successive approximation algo-
rithm, effectively comparing the sampled input voltage
with binary-weighted fractions of the channel’s SoftSpan
and buffer (V
= 4.096V nominal), each channel of
REFBUF
this SoftSpan ADC can be independently configured on a
conversion-by-conversion basis to accept 10.24V, 0V to
10.24V, 5.12V, or 0V to 5.12V signals. The input signal
range may be expanded up to 12.5V using an external
5V reference. Individual channels may also be disabled to
increase throughput on the remaining channels.
The integrated picoamp-input analog buffers, wide input
common mode range, and 128dB CMRR of the LTC2358-
16 allow the ADC to directly digitize a variety of signals
using minimal board space and power. This input signal
flexibility, combined with 1LSB INL, no missing codes
at 16 bits, and 94.2dB SNR, makes the LTC2358-16 an
ideal choice for many high voltage applications requiring
wide dynamic range.
full-scale range (e.g., V /2, V /4 … V /65536) us-
FSR
FSR
FSR
ing a differential comparator. At the end of this process,
the CDAC output approximates the channel’s sampled
analog input. Once all channels have been converted in
this manner, the ADC control logic prepares the 16-bit
digital output codes from each channel for serial transfer.
TRANSFER FUNCTION
The absolute common mode input range (V + 4V to
EE
TheLTC2358-16digitizeseachchannel’sfull-scalevoltage
V
– 4V) is determined by the choice of high voltage
CC
16
range into 2 levels. In conjunction with the ADC master
supplies. These supplies may be biased asymmetrically
reference voltage, V
, a channel’s SoftSpan configu-
REFBUF
around ground and include the ability for V to be tied
EE
ration determines its input voltage range, full-scale range,
LSB size, and the binary format of its conversion result, as
shown in Tables 1a and 1b. For example, employing the
directly to ground.
TheLTC2358-16supportspin-selectableSPICMOS(1.8V
to 5V) and LVDS serial interfaces, enabling it to com-
municate equally well with legacy microcontrollers and
modern FPGAs. In CMOS mode, applications may employ
betweenoneandeightlanesofserialoutputdata, allowing
the user to optimize bus width and data throughput. The
LTC2358-16typicallydissipates219mWwhenconverting
eight channels simultaneously at 200ksps per channel.
Optional nap and power down modes may be employed to
furtherreducepowerconsumptionduringinactiveperiods.
internal reference and buffer (V
= 4.096V nominal),
REFBUF
SoftSpan 7 configures a channel to accept a 10.24V bi-
polar analog input voltage range, which corresponds to a
20.48Vfull-scalerangewitha312.5μVLSB.OtherSoftSpan
configurationsandreferencevoltagesmaybeemployedto
convert both larger and smaller bipolar and unipolar input
ranges. Conversion results are output in two’s comple-
ment binary format for all bipolar SoftSpan ranges, and
in straight binary format for all unipolar SoftSpan ranges.
Rev A
19
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
The ideal two’s complement transfer function is shown in
Figure 2, while the ideal straight binary transfer function
is shown in Figure 3.
LTC2358-16 enables it to accept a wide variety of signal
swings,includingtraditionalclassesofanaloginputsignals
such as pseudo-differential unipolar, pseudo-differential
true bipolar, and fully differential, simplifying signal chain
design. For conversion of signals extending to V , the
EE
011...111
unbuffered LTC2348-16 ADC is recommended.
BIPOLAR
ZERO
011...110
The wide operating range of the high voltage supplies
offers further input common mode flexibility. As long as
000...001
000...000
111...111
111...110
the voltage difference limits of 10V ≤ (V – V ) ≤ 38V
CC
EE
are observed, V and V may be independently biased
CC
EE
anywhere within their own individually allowed operating
ranges, including the ability for V to be tied directly to
EE
100...001
100...000
FSR = +FS – –FS
1LSB = FSR/65536
ground. This feature enables the common mode input
range of the LTC2358-16 to be tailored to specific ap-
plication requirements.
–1 0V
1
–FSR/2
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
235816 F02
In all SoftSpan ranges, each channel’s analog inputs can
be modeled by the equivalent circuit shown in Figure 4. At
Figure 2. LTC2358-16 Two’s Complement Transfer Function
the start of acquisition, the sampling capacitors (C
)
SAMP
+
–
connecttotheintegratedbuffersBuffer /Buffer through
the sampling switches. The sampled voltage is reset dur-
ing the conversion process and is therefore re-acquired
for each new conversion.
111...111
111...110
100...001
100...000
The diodes between the inputs and the V and V sup-
CC
EE
UNIPOLAR
011...111
pliesprovideinputESDprotection.Whilewithinthesupply
voltages, the analog inputs of the LTC2358-16 draw only
5pA typical DC leakage current and the ESD protection
diodes don’t turn on. This offers a significant advantage
over external op amp buffers, which often have diode
protection that turns on during transients and corrupts
the voltage on any filter capacitors at their inputs.
ZERO
011...110
000...001
FSR = +FS
1LSB = FSR/65536
000...000
0V
FSR – 1LSB
INPUT VOLTAGE (V)
235816 F03
Figure 3. LTC2358-16 Straight Binary Transfer Function
V
CC
C
SAMP
+
BUFFER
R
SAMP
750Ω
30pF
+
BUFFERED ANALOG INPUTS
IN
Each channel of the LTC2358-16 simultaneously samples
V
EE
BIAS
the voltage difference (V + – V –) between its analog
IN
IN
VOLTAGE
V
CC
C
SAMP
30pF
input pins over a wide common mode input range while
attenuating unwanted signals common to both input pins
by the common-mode rejection ratio (CMRR) of the ADC.
WidecommonmodeinputrangecoupledwithhighCMRR
–
BUFFER
R
SAMP
750Ω
–
235816 F04
IN
V
EE
+
–
allows the IN /IN analog inputs to swing with an arbitrary
relationship to each other, provided each pin remains
Figure 4. Equivalent Circuit for Differential Analog
Inputs, Single Channel Shown
between (V + 4V) and (V – 4V). This feature of the
EE
CC
Rev A
20
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
Bipolar SoftSpan Input Ranges
less than 10kΩ of impedance can drive the passive 3pF
analog input capacitance directly. For higher impedances
and slow-settling circuits, add a 680pF capacitor at the
pins to maintain the full DC accuracy of the LTC2358-16.
For channels configured in SoftSpan ranges 7, 6, 3,
or 2, the LTC2358-16 digitizes the differential analog
input voltage (V + – V –) over a bipolar span of
IN
IN
REFBUF
2.5 • V
, 2.5 • V
/1.024, 1.25 • V , or
The very high input impedance of the unity gain buffers in
the LTC2358-16 greatly reduces the drive requirements of
the differential amplifier and make it possible to include
optional RC filters with kΩ impedance and arbitrarily slow
time constants for anti-aliasing or other purposes. Micro-
power op amps with limited drive capability are also well
suited to drive the high impedance analog inputs directly.
REFBUF
REFBUF
1.25 • V
/1.024, respectively, as shown in Table 1a.
REFBUF
TheseSoftSpanrangesareusefulfordigitizinginputsignals
+
–
where IN and IN swing above and below each other.
Traditionalexamplesincludefullydifferentialinputsignals,
+
–
where IN and IN are driven 180 degrees out-of-phase
with respect to each other centered around a common
mode voltage (V + + V –)/2, and pseudo-differential
IN
IN
The LTC2358-16 features proprietary circuitry to achieve
exceptional internal crosstalk isolation between channels
(109dB typical). The PC board wiring to the analog inputs
shouldbeshortandshieldedtopreventexternalcapacitive
crosstalkbetweenchannels.Thecapacitancebetweenadja-
centpackagepinsis0.16pF.Lowsourceresistanceand/or
high source capacitance help reduce external capacitively
coupled crosstalk. Single ended input drive also enjoys
additionalexternalcrosstalkisolationbecauseeveryother
input pin is grounded, or at a low impedance DC source,
and serves as a shield between channels.
+
true bipolar input signals, where IN swings above and
–
below a ground reference level, driven on IN . Regardless
of the chosen SoftSpan range, the wide common mode
+
–
input range and high CMRR of the IN /IN analog inputs
allow them to swing with an arbitrary relationship to each
other, provided each pin remains between (V – 4V) and
CC
(V + 4V). The output data format for all bipolar SoftSpan
EE
ranges is two’s complement.
Unipolar SoftSpan Input Ranges
For channels configured in SoftSpan ranges 5, 4, or 1, the
LTC2358-16 digitizes the differential analog input voltage
INPUT OVERDRIVE TOLERANCE
(V + – V –) over a unipolar span of 0V to 2.5 • V ,
IN
IN
REFBUF
, respec-
DrivingananaloginputaboveV onanychannelupto10mA
0V to 2.5 • V
/1.024, or 0V to 1.25 • V
CC
REFBUF
REFBUF
willnotaffectconversionresultsonotherchannels.Approx-
tively, as shown in Table 1a. These SoftSpan ranges are
+
imately70%ofthisoverdrivecurrentwillflowoutoftheV
usefulfordigitizinginputsignalswhereIN remainsabove
CC
–
pinandtheremaining30%willflowoutofV .Thiscurrent
IN . A traditional example includes pseudo-differential
EE
+
flowing out of V will produce heat across the V – V
unipolar input signals, where IN swings above a ground
EE
CC
EE
–
voltage drop and must be taken into account for the total
reference level, driven on IN . Regardless of the chosen
Absolute Maximum power dissipation of 500mW. Driving
SoftSpan range, the wide common mode input range and
+
–
an analog input below V may corrupt conversion results
high CMRR of the IN /IN analog inputs allow them to
swingwithanarbitraryrelationshiptoeachother,provided
each pin remains between (V – 4V) and (V + 4V).
EE
on other channels. This product can handle input currents
of up to 100mA below V or above V without latchup.
EE
CC
CC
EE
The output data format for all unipolar SoftSpan ranges
is straight binary.
Keep in mind that driving the inputs above V or below
CC
V may reverse the normal current flow from the external
EE
power supplies driving these pins.
INPUT DRIVE CIRCUITS
The CMOS buffer input stage offers a very high degree of
transient isolation from the sampling process. Most sen-
sors,signalconditioningamplifiersandfilternetworkswith
Rev A
21
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
Input Filtering
feature of the LTC2358-16 enables it to accept a wide
variety of signal swings, simplifying signal chain design.
The true high impedance analog inputs can accommodate
a very wide range of passive or active signal conditioning
filters. The buffered ADC inputs have an analog bandwidth
of6MHz,andimposenoparticularbandwidthrequirement
onexternalfilters.Theexternalinputfilterscanthereforebe
optimized independent of the ADC to reduce signal chain
noise and interference. A common filter configuration is
thesimpleanti-aliasingandnoisereducingRCfilterwithits
pole at half the sampling frequency. For example, 100kHz
with R=2.43kΩ and C=680pF as shown in Figure 5.
The two-tone test shown in Figure 6b demonstrates the
arbitraryinputdrivecapabilityoftheLTC2358-16.Thistest
+
simultaneouslydrivesIN witha−7dBFS2kHzsingle-ended
−
sinewaveandIN witha−7dBFS3.1kHzsingle-endedsine
wave. Together, these signals sweep the analog inputs
across a wide range of common mode and differential
mode voltage combinations, similar to the more general
arbitrary input signal case. They also have a simple spec-
tral representation. An ideal differential converter with no
common-mode sensitivity will digitize this signal as two
−7dBFS spectral tones, one at each sine wave frequency.
The FFT plot in Figure 6b demonstrates the LTC2358-16
response approaches this ideal, with 119dB of SFDR
limited by the converter's second harmonic distortion
ꢁꢂꢃ
ꢎꢘꢅꢕꢎꢏAꢄ
ꢅRꢖꢒ ꢗꢕꢘꢎꢄAR
ꢙꢁꢍꢃ
ꢄꢎꢔꢘAꢓꢓ ꢌꢕꢄꢅꢒR
R ꢟ ꢇꢚꢜꢈꢠ
ꢍꢚꢁꢛꢌ
ꢙ
ꢀ
ꢕꢏ
ꢍꢃ
ꢀꢁꢍꢃ
ꢃ
ꢆꢆ
ꢙ
ꢀ
ꢕꢏꢍ
ꢕꢏꢍ
ꢋꢉꢍꢞꢌ
ꢖꢏꢕꢘꢎꢄAR
–
ꢙꢁꢍꢃ
response to the 3.1kHz sine wave on IN .
ꢄꢅꢆꢇꢈꢂꢉꢊꢁꢋ
ꢕꢏ
ꢍꢃ
The ability of the LTC2358-16 to accept arbitrary signal
swings over a wide input common mode range with high
CMRR can simplify application solutions. In practice,
many sensors produce a differential sensor voltage riding
on top of a large common mode signal. Figure 7a depicts
one way of using the LTC2358-16 to digitize signals of
this type. The amplifier stage provides a differential gain
of approximately 10V/V to the desired sensor signal while
the unwanted common mode signal is attenuated by the
ADCCMRR.Thecircuitemploysthe 5VSoftSpanrangeof
the ADC. Figure 7b shows measured CMRR performance
of this solution, which is competitive with the best com-
mercially available instrumentation amplifiers. Figure 7c
shows measured AC performance of this solution.
ꢃ
Rꢒꢌꢗꢖꢌ
ꢜꢝꢛꢌ
Rꢒꢌꢕꢏ
ꢒꢒ
ꢀꢁꢍꢃ
ꢍꢚꢁꢛꢌ
ꢍꢚꢁꢛꢌ
ꢀꢁꢂꢃ
ꢎꢏꢄꢐ ꢆꢑAꢏꢏꢒꢄ ꢍ ꢓꢑꢎꢔꢏ ꢌꢎR ꢆꢄARꢕꢅꢐ
ꢇꢈꢂꢉꢁꢋ ꢌꢍꢂ
Figure 5. Filtering Single-Ended Input Signals
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion.
NPO/COG and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self-heating and from damage
thatmayoccurduringsoldering. Metalfilmsurfacemount
resistors are much less susceptible to both problems.
In Figure 8, another application circuit is shown which
uses two channels of the LTC2358-16 to simultaneously
sensethevoltageandbidirectionalcurrentthroughasense
resistor over a wide common mode range.
Arbitrary and Fully Differential Analog Input Signals
The wide common mode input range and high CMRR of
+
–
the LTC2358-16 allow each channel’s IN and IN pins to
swingwithanarbitraryrelationshiptoeachother,provided
each pin remains between (V – 4V) and (V + 4V). This
CC
EE
Rev A
22
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
AR RAR
R
A
AR
R
AR
R
R
A
R
AR
Figure 6a. Input Arbitrary, Fully Differential, True Bipolar, and Unipolar Signals
Arbitrary Drive
Fully Differential Drive
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁꢂR ꢃ ꢄꢄꢅꢆꢇ
ꢀꢁR ꢂ ꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁR ꢂ ꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ ꢃ ꢄꢅꢅꢆꢇꢈ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂAꢃ ꢄ ꢅꢆꢇꢈꢉꢊ
ꢀꢁꢂR ꢃ ꢄꢅꢆꢇꢈ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢅꢈ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢅꢈ
Figure 6b. Two-Tone Test. IN+ = –7dBFS 2kHz Sine,
IN– = –7dBFS 3.1kHz Sine, 32k Point FFT, fSMPL = 200ksps.
Circuit Shown in Figure 6a
Figure 6c. IN+/IN– = –1dBFS 2kHz Fully Differential Sine,
VCM = 0V, 32k Point FFT, fSMPL = 200ksps. Circuit Shown in
Figure 6a
True Bipolar Drive
Unipolar Drive
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁ ꢂꢃ ꢄꢀꢅꢆꢇꢁ RAꢈꢉꢊ
ꢀꢁR ꢂ ꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ ꢃ ꢄꢅꢅꢅꢆꢇ
ꢀꢁꢂAꢃ ꢄ ꢅꢆꢇꢈꢉꢊ
ꢀꢁꢂR ꢃ ꢄꢄꢅꢆꢇ
ꢀꢁR ꢂ ꢃꢄꢅꢄꢆꢇ
ꢀꢁꢂ ꢃ ꢄꢅꢅꢆꢇꢈ
ꢀꢁꢂAꢃ ꢄ ꢅꢆꢇꢅꢈꢉ
ꢀꢁꢂR ꢃ ꢄꢄꢅꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢅꢈ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢅe
Figure 6d. IN+ = –1dBFS 2kHz True Bipolar Sine, IN– = 0V, 32k
Point FFT, fSMPL = 200ksps. Circuit Shown in Figure 6a
Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN– = 0V,
32k Point FFT, fSMPL = 200ksps. Circuit Shown in Figure 6a
Rev A
23
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
INTERNAL HI-Z BUFFERS
ALLOW OPTIONAL
ARBITRARY
31V
+
31V
kΩ PASSIVE FILTERS
LTC2057HV
GAIN = 10
LTC2057HV
+
–
IN
24V
3.65k
0.1µF
BUFFERED
ANALOG
INPUTS
2.49k
V
+
–
CC
COMMON MODE
INPUT RANGE
IN0
IN0
549Ω
2.49k
2.2nF
LTC2358-16
3.65k
DIFFERENTIAL MODE
INPUT RANGE: 500ꢀV
–
+
V
REFBUF
47µF
REFIN
EE
0V
BW = 10kHz
–
IN
0.1µF
0.1µF
–7V
–7V
ONLY CHANNEL 0 SHOWN FOR CLARITY
235816 F07a
Figure 7a. Amplify Differential Signals with Gain of 10
Over a Wide Common Mode Range with Buffered Analog Inputs
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ RAꢃꢄ
ꢀꢁꢂ RAꢃꢄ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂꢃ ꢄꢅꢀꢀꢆRꢆꢇꢈꢅAꢂ ꢄRꢅꢉꢆ ꢊꢅꢇ ꢀ ꢁꢂꢃ ꢀ
ꢀꢁR ꢂ ꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ ꢃ ꢄꢅꢅꢅꢆꢇ
ꢀꢁꢂAꢃ ꢄ ꢅꢆꢇꢈꢉꢊ
ꢀꢁꢂR ꢃ ꢄꢄꢅꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀꢁ ꢀ ꢁꢂ ꢀ ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ
Figure 7c. IN+/IN– = 450mV 200Hz Fully
Differential Sine, 0V ≤ VCM ≤ 24V, 32k Point FFT,
fSMPL = 200ksps. Circuit Shown in Figure 7a
Figure 7b. CMRR vs Input Frequency.
Circuit Shown in Figure 7a
15V
0.1µF
V
CC
+
–
IN0
IN0
V
S1
LTC2358-16
+
IN1
IN1
R
SENSE
I
SENSE
–
V
REFBUF
47µF
REFIN
EE
V
S2
0.1µF
0.1µF
–15V
235816 F08
ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY
– V –10.24V ≤ V ≤ 10.24V
V
R
S1
S2
S1
I
=
SENSE
–10.24V ≤ V ≤ 10.24V
SENSE
S2
Figure 8. Simultaneously Sense Voltage (CH0) and Current (CH1) Over a Wide Common Mode Range
Rev A
24
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
ADC REFERENCE
ꢏꢐꢑꢀꢁꢂꢃꢒꢄꢅ
Rꢓꢆꢖꢗ
ꢀꢇꢎ
ꢔAꢗꢙꢘAꢚ
AsshownpreviouslyinTable1b, theLTC2358-16supports
three reference configurations. The first uses both the in-
ternalbandgapreferenceandreferencebuffer. Thesecond
externally overdrives the internal reference but retains the
internal buffer, which isolates the external reference from
ADC conversion transients. This configuration is ideal
for sharing a single precision external reference across
multiple ADCs. The third disables the internal buffer and
overdrives the REFBUF pin externally.
RꢓꢆꢓRꢓꢗꢑꢓ
ꢇꢍꢄꢌꢆ
Rꢓꢆꢔꢕꢆ
RꢓꢆꢓRꢓꢗꢑꢓ
ꢔꢕꢆꢆꢓR
ꢅꢍꢂꢎ
ꢊꢋꢌꢆ
ꢅꢍꢂꢎ
ꢘꢗꢙ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ
Figure 9a. Internal Reference with Internal
Buffer Configuration
Internal Reference with Internal Buffer
The LTC2358-16 has an on-chip, low noise, low drift
(20ppm/°C maximum), temperature compensated band-
gap reference that is factory trimmed to 2.048V. The
reference output connects through a 20kΩ resistor to
the REFIN pin, which serves as the input to the on-chip
reference buffer, as shown in Figure 9a. When employing
the internal bandgap reference, the REFIN pin should be
bypassed to GND (Pin 20) close to the pin with a 0.1μF
ceramic capacitor to filter wideband noise. The reference
ꢏꢐꢑꢀꢁꢂꢃꢒꢄꢅ
Rꢓꢆꢖꢗ
ꢀꢇꢎ
ꢔAꢗꢙꢘAꢚ
RꢓꢆꢓRꢓꢗꢑꢓ
ꢀꢍꢋꢌꢆ
Rꢓꢆꢔꢕꢆ
RꢓꢆꢓRꢓꢗꢑꢓ
ꢔꢕꢆꢆꢓR
ꢅꢍꢂꢎ
ꢊꢋꢌꢆ
ꢏꢐꢑꢅꢅꢂꢂꢒꢀꢍꢇꢊꢃ
ꢅꢍꢂꢎ
buffer amplifies V
to create the converter master
REFIN
reference voltage V
ꢘꢗꢙ
= 2 • V
on the REFBUF pin,
REFBUF
REFIN
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ
nominally 4.096V when using the internal bandgap refer-
ence. BypassREFBUFtoGND(Pin20)closetothepinwith
at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or
X5R, 10V, 0805 size) to compensate the reference buffer,
absorbtransientconversioncurrents,andminimizenoise.
Figure 9b. External Reference with Internal
Buffer Configuration
ꢏꢐꢑꢀꢁꢂꢃꢒꢄꢅ
ꢀꢇꢎ
External Reference with Internal Buffer
Rꢓꢆꢖꢗ
ꢔAꢗꢙꢘAꢚ
RꢓꢆꢓRꢓꢗꢑꢓ
If more accuracy and/or lower drift is desired, REFIN can
be easily overdriven by an external reference since 20kΩ
of resistance separates the internal bandgap reference
output from the REFIN pin, as shown in Figure 9b. The
valid range of external reference voltage overdrive on the
REFIN pin is 1.25V to 2.2V, resulting in converter master
Rꢓꢆꢔꢕꢆ
RꢓꢆꢓRꢓꢗꢑꢓ
ꢔꢕꢆꢆꢓR
ꢅꢍꢂꢎ
ꢊꢋꢌꢆ
ꢏꢐꢑꢅꢅꢂꢂꢒꢂ
ꢅꢍꢂꢎ
ꢘꢗꢙ
reference voltages V
between 2.5V and 4.4V, re-
REFBUF
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ
spectively. Analog Devices, Inc. offers a portfolio of high
performance references designed to meet the needs of
manyapplications.Withitssmallsize,lowpower,andhigh
accuracy,theLTC6655-2.048iswellsuitedforusewiththe
LTC2358-16 when overdriving the internal reference. The
Figure 9c. External Reference with Disabled
Internal Buffer Configuration
Rev A
25
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
LTC6655-2.048offers0.025%(maximum)initialaccuracy
and2ppm/°C(maximum)temperaturecoefficientforhigh
precision applications. The LTC6655-2.048 is fully speci-
fied over the H-grade temperature range, complementing
the extended temperature range of the LTC2358-16 up to
125°C.BypassingtheLTC6655-2.048witha2.7µFto100µF
ceramiccapacitorclosetotheREFINpinisrecommended.
current step triggers a transient response in the external
reference that must be considered, since any deviation in
REFBUF
is used to overdrive REFBUF, the fast settling LTC6655
family of references is recommended.
V
affectsconverteraccuracy.Ifanexternalreference
Internal Reference Buffer Transient Response
Foroptimumperformanceinapplicationsemployingburst
sampling, the external reference with internal reference
bufferconfigurationshouldbeused.Theinternalreference
buffer incorporates a proprietary design that minimizes
External Reference with Disabled Internal Buffer
The internal reference buffer supports V
= 4.4V
REFBUF
maximum. By grounding REFIN, the internal buffer may
be disabled allowing REFBUF to be overdriven with an
externalreferencevoltagebetween2.5Vand5V, asshown
in Figure 9c. Maximum input signal swing and SNR are
achieved by overdriving REFBUF using an external 5V
reference. The buffer feedback resistors load the REFBUF
pin with 13kΩ even when the reference buffer is disabled.
The LTC6655-5 offers the same small size, accuracy, drift,
and extended temperature range as the LTC6655-2.048,
and achieves a typical SNR of 94.8dB when paired with
the LTC2358-16. Bypass the LTC6655-5 to GND (Pin 20)
close to the REFBUF pin with at least a 47μF ceramic ca-
pacitor (X7R, 10V, 1210 size or X5R, 10V, 0805 size) to
absorb transient conversion currents and minimize noise.
movements in V
when responding to a burst of
REFBUF
conversions following an idle period. Figure 11 compares
the burst conversion response of the LTC2358-16 with an
input near full scale for two reference configurations. The
first configuration employs the internal reference buffer
with REFIN externally overdriven by an LTC6655-2.048,
while the second configuration disables the internal ref-
erence buffer and overdrives REFBUF with an external
LTC6655-4.096. In both cases REFBUF is bypassed to
GND with a 47µF ceramic capacitor.
ꢀꢁꢂꢁ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀ
ꢀꢁ ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁ ꢀ ꢁꢂ
The LTC2358-16 converter draws a charge (Q
) from
CONV
ꢀꢁꢂꢀRꢃAꢄ RꢀꢅꢀRꢀꢃꢆꢀ ꢇꢃ Rꢀꢅꢈꢉꢅ
the REFBUF pin during each conversion cycle. On short
time scales most of this charge is supplied by the external
REFBUF bypass capacitor, but on longer time scales all of
the charge is supplied by either the reference buffer, or
when the internal reference buffer is disabled, the external
reference. This charge draw corresponds to a DC current
ꢀꢁꢂꢃRꢁAꢄ RꢃꢅꢃRꢃꢁꢆꢃ ꢇꢈꢅꢅꢃR
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
ꢀꢁꢁ
equivalentofI
=Q
•f
,whichisproportional
REFBUF
CONV SMPL
ꢀꢁꢂꢃ ꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢄ
to sample rate. In applications where a burst of samples
is taken after idling for long periods of time, as shown in
Figure 11. Burst Conversion Response of the LTC2358-16,
fSMPL = 200ksps
Figure 10, I
quickly transitions from approximately
REFBUF
0.4mA to 1.5mA (V
= 5V, f
= 200kHz). This
REFBUF
SMPL
ꢀꢁꢂ
ꢉꢊꢋꢌꢍꢎ ꢏꢍꢐ
ꢃꢄꢅꢆ
ꢇꢆRꢃꢈꢄ
ꢃꢄꢅꢆ
ꢇꢆRꢃꢈꢄ
Figure 10. CNV Waveform Showing Burst Sampling
Rev A
26
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
through Nth harmonics, respectively. Figure 12 shows
that the LTC2358-16 achieves a typical THD of –111dB
(N = 6) in the 10.24V range at a 200kHz sampling rate
with a true bipolar 2kHz input signal.
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion, and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2358-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ RAꢇꢈ
ꢀꢁR ꢂ ꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ ꢃ ꢄꢅꢅꢅꢆꢇ
ꢀꢁꢂAꢃ ꢄ ꢅꢆꢇꢈꢉꢊ
ꢀꢁꢂR ꢃ ꢄꢄꢅꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies below half the sampling frequency, exclud-
ing DC. Figure 12 shows that the LTC2358-16 achieves a
typical SINAD of 94.1dB in the 10.24V range at a 200kHz
sampling rate with a true bipolar 2kHz input signal.
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢀ
Figure 12. 32k Point FFT fSMPL = 200ksps, fIN = 2kHz
POWER CONSIDERATIONS
The LTC2358-16 requires four power supplies: the posi-
Signal-to-Noise Ratio (SNR)
tive and negative high voltage power supplies (V and
CC
V ), the 5V core power supply (V ) and the digital input/
EE
DD
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 12 shows
that the LTC2358-16 achieves a typical SNR of 94.2dB in
the 10.24V range at a 200kHz sampling rate with a true
bipolar 2kHz input signal.
output (I/O) interface power supply (OV ). As long as
DD
CC
the voltage difference limits of 10V ≤ V – V ≤ 38V
EE
are observed, V and V may be independently biased
CC
EE
anywhere within their own individual allowed operating
ranges, including the ability for V to be tied directly to
EE
ground. This feature enables the common mode input
range of the LTC2358-16 to be tailored to the specific
application’s requirements. The flexible OV supply al-
DD
Total Harmonic Distortion (THD)
lows the LTC2358-16 to communicate with CMOS logic
Totalharmonicdistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (f
THD is expressed as:
operating between 1.8V and 5V, including 2.5V and 3.3V
systems. When using LVDS I/O mode, the range of OV
is 2.375V to 5.25V.
DD
/2).
SMPL
Power Supply Sequencing
The LTC2358-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2358-16 has
an internal power-on-reset (POR) circuit which resets the
2
2
2
2
V + V + V ...V
N
2
3
4
THD = 20log
V
1
where V is the RMS amplitude of the fundamental fre-
quencyandV throughV aretheamplitudesofthesecond
1
2
N
Rev A
27
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
converter on initial power-up and whenever V drops
sion process. The CNV timing required to take advantage
of the reduced power nap mode of operation is described
in the Nap Mode section.
DD
below 2V. Once the supply voltage re-enters the nominal
supply voltage range, the POR reinitializes the ADC. No
conversions should be initiated until at least 10ms after
a POR event to ensure the initialization period has ended.
Whenemployingtheinternalreferencebuffer,allow200ms
forthebuffertopowerupandrechargetheREFBUFbypass
capacitor. Any conversion initiated before these times will
produce invalid results.
Internal Conversion Clock
The LTC2358-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 550•N ns with N
channels enabled. With a minimum acquisition time of
570ns when converting eight channels simultaneously,
throughputperformanceof200kspsisguaranteedwithout
any external adjustments. Also note that the minimum
TIMING AND CONTROL
CNV Timing
acquisition time varies with sampling frequency (f
and the number of enabled channels.
)
SMPL
The LTC2358-16 sampling and conversion is controlled
by CNV. A rising edge on CNV transitions all channels’ S/H
circuits from track mode to hold mode, simultaneously
sampling the input signals on all channels and initiating
a conversion. Once a conversion has been started, it
cannot be terminated early except by resetting the ADC,
as discussed in the Reset Timing section. For optimum
performance, drive CNV with a clean, low jitter signal and
avoid transitions on data I/O lines leading up to the rising
edge of CNV. Additionally, to minimize channel-to-channel
crosstalk, avoid high slew rates on the analog inputs for
100ns before and after the rising edge of CNV. Converter
status is indicated by the BUSY output, which transitions
low-to-high at the start of each conversion and stays high
untiltheconversioniscomplete.OnceCNVisbroughthigh
to begin a conversion, it should be returned low between
40ns and 60ns later or after the falling edge of BUSY to
minimizeexternaldisturbancesduringtheinternalconver-
Nap Mode
The LTC2358-16 can be placed into nap mode after a con-
versionhasbeencompletedtoreducepowerconsumption
between conversions. In this mode a portion of the device
circuitry is turned off, including circuits associated with
sampling the analog input signals. Nap mode is enabled
by keeping CNV high between conversions, as shown in
Figure 13. To initiate a new conversion after entering nap
mode, bring CNV low and hold for at least 750ns before
bringingithighagain.Theconverteracquisitiontime(t
is set by the CNV low time (t
)
ACQ
) when using nap mode.
CNVL
Power Down Mode
When PD is brought high, the LTC2358-16 is powered
down and subsequent conversion requests are ignored. If
this occurs during a conversion, the device powers down
once the conversion completes. In this mode, the device
ꢃ
ꢀꢁꢂꢎ
ꢀꢁꢂ
ꢃ
ꢀꢄꢁꢂ
ꢆꢇꢈꢉ
ꢁAꢊ
ꢃ
Aꢀꢅ
ꢁAꢊ ꢋꢄꢌꢍ
ꢏꢐꢑꢒꢓꢔ ꢕꢓꢐ
Figure 13. Nap Mode Timing for the LTC2358-16
Rev A
28
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
draws only a small regulator standby current resulting in a
typical power dissipation of 0.68mW. To exit power down
mode, bring the PD pin low and wait at least 10ms before
initiatingaconversion. When employingtheinternal refer-
ence buffer, allow 200ms for the buffer to power up and
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.
reduced, as shown in Figure 15. This decrease in aver-
age power dissipation occurs because a portion of the
LTC2358-16 circuitry is turned off during nap mode, and
the fraction of the conversion cycle (t ) spent napping
CYC
increasesasthesamplingfrequency(f
)isdecreased.
SMPL
ꢀꢁ
ꢀꢁꢂꢃ ꢄAꢅ ꢆꢇꢈꢉ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀ
Reset Timing
A global reset of the LTC2358-16, equivalent to a power-
on-reset event, may be executed without needing to cycle
the supplies. This feature is useful when recovering from
system-level events that require the state of the entire sys-
tem to be reset to a known synchronized value. To initiate
a global reset, bring PD high twice without an intervening
conversion, as shown in Figure 14. The reset event is trig-
geredonthesecondrisingedgeofPD,andasynchronously
ends based on an internal timer. Reset clears all serial data
outputregistersandrestorestheinternalSoftSpanconfigu-
ration register default state of all channels in SoftSpan 7.
If reset is triggered during a conversion, the conversion
is immediately halted. The normal power down behavior
associatedwithPDgoinghighisnotaffectedbyreset.Once
PD is brought low, wait at least 10ms before initiating a
conversion. When employing the internal reference buffer,
allow 200ms for the buffer to power up and recharge the
REFBUF bypass capacitor. Any conversion initiated before
these times will produce invalid results.
ꢀ
ꢀ
ꢀꢁꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀAꢁꢂꢃꢄꢅꢆ ꢇRꢈꢉꢊꢈꢅꢋꢌ ꢍꢎꢏꢐꢑ
ꢀꢁꢂꢃꢄꢅ ꢆꢄꢂ
Figure 15. Power Dissipation of the LTC2358-16
Decreases with Decreasing Sampling Frequency
DIGITAL INTERFACE
TheLTC2358-16featuresCMOSandLVDSserialinterfaces,
selectable using the LVDS/CMOS pin. The flexible OV
DD
supply allows the LTC2358-16 to communicate with any
CMOS logic operating between 1.8V and 5V, including
2.5V and 3.3V systems, while the LVDS interface supports
low noise digital designs. In CMOS mode, applications
may employ between one and eight lanes of serial data
output, allowing the user to optimize bus width and data
throughput. Together, these I/O interface options enable
the LTC2358-16 to communicate equally well with legacy
microcontrollers and modern FPGAs.
Power Dissipation vs Sampling Frequency
When nap mode is employed, the power dissipation of
the LTC2358-16 decreases as the sampling frequency is
ꢃ
ꢆꢇꢅ
ꢃ
ꢆꢇ
ꢓAꢔꢍ
ꢃ
ꢃ
ꢆꢇꢈ
ꢀꢁꢂꢅ
ꢀꢁꢂ
ꢋꢍꢀꢄꢁꢇ Rꢏꢋꢏꢁꢑ ꢍꢇꢑꢍ ꢄꢒ
ꢆꢇ ꢎRꢏꢑꢑꢍRꢋ Rꢍꢋꢍꢎ
ꢉꢊꢋꢌ
ꢃ
ꢀꢄꢁꢂ
Rꢍꢋꢍꢎ ꢎꢏꢐꢍ
ꢋꢍꢎ ꢏꢁꢎꢍRꢁAꢈꢈꢌ
Rꢍꢋꢍꢎ
ꢕꢖꢗꢘꢙꢚ ꢒꢙꢛ
Figure 14. Reset Timing for the LTC2358-16
Rev A
29
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
CS ꢏ ꢐꢌ ꢏ ꢃ
ꢄAꢜꢐꢝꢔ ꢍ
ꢄAꢜꢐꢝꢔ ꢍ ꢟ ꢂ
ꢕ
ꢀꢙꢀ
ꢕ
ꢀꢍꢎꢢ
ꢕ
ꢀꢍꢎ
ꢀꢍꢎꢝ
ꢗꢘꢄꢙ
ꢕ
ꢕ
Aꢀꢖ
ꢀꢑꢍꢎ
ꢕ
Rꢔꢀꢑꢜꢜꢔꢍꢌꢔꢌ ꢌAꢓA ꢓRAꢍꢄAꢀꢓꢛꢑꢍ ꢞꢛꢍꢌꢑꢞ
ꢗꢘꢄꢙꢝꢢ
ꢕ
ꢖꢘꢛꢔꢓ
ꢕ
ꢕ
ꢕ
ꢄꢄꢌꢛꢄꢀꢚꢛ
ꢄꢀꢚꢛ
ꢄꢀꢚꢛꢢ
ꢄꢀꢚꢛ
ꢄꢌꢛ
ꢂ
ꢁ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ ꢂꢃ ꢂꢂ ꢂꢁ ꢂꢅ ꢂꢆ ꢂꢇ ꢂꢈ ꢂꢉ ꢂꢊ ꢂꢋ ꢁꢃ ꢁꢂ ꢁꢁ ꢁꢅ ꢁꢆ
ꢕ
ꢕ
ꢢꢄꢌꢛꢄꢀꢚꢛ
ꢄꢀꢚꢛꢝ
ꢌꢑꢍꢒꢓ ꢀARꢔ
ꢄꢁꢅ ꢄꢁꢁ ꢄꢁꢂ ꢄꢁꢃ ꢄꢂꢋ ꢄꢂꢊ ꢄꢂꢉ ꢄꢂꢈ ꢄꢂꢇ ꢄꢂꢆ ꢄꢂꢅ ꢄꢂꢁ ꢄꢂꢂ ꢄꢂꢃ ꢄꢋ ꢄꢊ ꢄꢉ ꢄꢈ ꢄꢇ ꢄꢆ ꢄꢅ ꢄꢁ ꢄꢂ ꢄꢃ
ꢄꢑꢠꢓꢄꢐAꢍ ꢀꢑꢍꢠꢛꢡꢘRAꢓꢛꢑꢍ ꢞꢑRꢌ ꢠꢑR ꢀꢑꢍꢎꢔRꢄꢛꢑꢍ ꢍ ꢟ ꢂ
ꢕ
ꢕ
ꢕ
ꢄꢚꢔꢞ
ꢌꢄꢌꢑꢗꢘꢄꢙꢝ
ꢢꢄꢌꢑꢄꢀꢚꢛ
ꢄꢀꢚꢑ
ꢄꢌꢑꢃ
ꢕ
ꢌꢄꢌꢑꢄꢀꢚꢛ
ꢌꢑꢍꢒꢓ ꢀARꢔ
ꢌꢑꢍꢒꢓ ꢀARꢔ
ꢌꢂꢇ
ꢌꢂꢇ
ꢌꢂꢆ ꢌꢂꢅ ꢌꢂꢁ ꢌꢂꢂ ꢌꢂꢃ ꢌꢋ ꢌꢊ ꢌꢉ ꢌꢈ ꢌꢇ ꢌꢆ ꢌꢅ ꢌꢁ ꢌꢂ ꢌꢃ
ꢀꢑꢍꢎꢔRꢄꢛꢑꢍ Rꢔꢄꢘꢝꢓ
ꢃ
ꢃ
ꢃ
ꢃ
ꢀꢁ ꢀꢂ ꢀꢃ ꢄꢄꢁ ꢄꢄꢂ ꢄꢄꢃ ꢌꢂꢇ
ꢀꢢAꢍꢍꢔꢝ ꢛꢌ ꢄꢑꢠꢓꢄꢐAꢍ
ꢀꢑꢍꢎꢔRꢄꢛꢑꢍ Rꢔꢄꢘꢝꢓ
ꢀꢢAꢍꢍꢔꢝ ꢃ
ꢁꢆꢣꢗꢛꢓ ꢐAꢀꢚꢔꢓ
ꢀꢑꢍꢎꢔRꢄꢛꢑꢍ ꢍ
ꢀꢢAꢍꢍꢔꢝ ꢂ
ꢁꢆꢣꢗꢛꢓ ꢐAꢀꢚꢔꢓ
ꢀꢑꢍꢎꢔRꢄꢛꢑꢍ ꢍ
ꢄꢌꢑꢉ
ꢌꢂꢆ ꢌꢂꢅ ꢌꢂꢁ ꢌꢂꢂ ꢌꢂꢃ ꢌꢋ ꢌꢊ ꢌꢉ ꢌꢈ ꢌꢇ ꢌꢆ ꢌꢅ ꢌꢁ ꢌꢂ ꢌꢃ
ꢀꢑꢍꢎꢔRꢄꢛꢑꢍ Rꢔꢄꢘꢝꢓ
ꢀꢁ ꢀꢂ ꢀꢃ ꢄꢄꢁ ꢄꢄꢂ ꢄꢄꢃ ꢌꢂꢇ
ꢀꢢAꢍꢍꢔꢝ ꢛꢌ ꢄꢑꢠꢓꢄꢐAꢍ ꢀꢑꢍꢎꢔRꢄꢛꢑꢍ Rꢔꢄꢘꢝꢓ
ꢀꢢAꢍꢍꢔꢝ ꢉ
ꢁꢆꢣꢗꢛꢓ ꢐAꢀꢚꢔꢓ
ꢀꢑꢍꢎꢔRꢄꢛꢑꢍ ꢍ
ꢀꢢAꢍꢍꢔꢝ ꢃ
ꢁꢆꢣꢗꢛꢓ ꢐAꢀꢚꢔꢓ
ꢀꢑꢍꢎꢔRꢄꢛꢑꢍ ꢍ
ꢁꢅꢇꢊꢂꢈ ꢠꢂꢈ
Figure 16. Serial CMOS I/O Mode
Serial CMOS I/O Mode
configuration words are only accepted within this recom-
mended data transaction window, but SoftSpan changes
take effect immediately with no additional analog input
settling time required before starting the next conversion.
It is still possible to read conversion data after starting the
nextconversion,butthiswilldegradeconversionaccuracy
and therefore is not recommended.
As shown in Figure 16, in CMOS I/O mode the serial data
bus consists of a serial clock input, SCKI, serial data
input, SDI, serial clock output, SCKO, and eight lanes of
serial data output, SDO0 to SDO7. Communication with
the LTC2358-16 across this bus occurs during predefined
data transaction windows. Within a window, the device
accepts 24-bit SoftSpan configuration words for the next
conversion on SDI and outputs 24-bit packets containing
conversion results and channel configuration information
from the previous conversion on SDO0 to SDO7. New
data transaction windows open 10ms after powering up
or resetting the LTC2358-16, and at the end of each con-
version on the falling edge of BUSY. In the recommended
use case, the data transaction should be completed with
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SCKO is forced low and
SDO0 to SDO7 are updated with the latest conversion
results from analog input channels 0 to 7, respectively.
Rising edges on SCKI serially clock conversion results
and analog input channel configuration information out
on SDO0 to SDO7 and trigger transitions on SCKO that are
skew-matchedtothedataonSDO0toSDO7. Theresulting
SCKO frequency is half that of SCKI. SCKI rising edges
also latch SoftSpan configuration words provided on SDI,
a minimum t
time of 20ns prior to the start of the
QUIET
next conversion, as shown in Figure 16. New SoftSpan
Rev A
30
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
which are used to program the internal 24-bit SoftSpan
configuration register. See the section Programming the
SoftSpan Configuration Register in CMOS I/O Mode for
further details. SCKI is allowed to idle either high or low
in CMOS I/O mode. As shown in Figure 17, the CMOS
bus is enabled when CS is low and is disabled and Hi-Z
when CS is high, allowing the bus to be shared across
multiple devices.
When interfacing the LTC2358-16 with a standard SPI
bus, capture output data at the receiver on rising edges of
SCKI. SCKO is not used in this case. Multiple SDO lanes
are also usually not useful in this case. In other applica-
tions, such as interfacing the LTC2358-16 with an FPGA
or CPLD, rising and falling edges of SCKO may be used
to capture serial output data on SDO0 to SDO7 in double
data rate (DDR) fashion. Capturing data using SCKO adds
robustnesstodelayvariationsovertemperatureandsupply.
ThedataonSDO0toSDO7aregroupedinto24-bitpackets
consisting of a 16-bit conversion result followed by two
zeros,3-bitanalogchannelID,and3-bitSoftSpancode,all
presented MSB first. As suggested in Figures 16 and 17,
each SDO lane outputs these packets for all analog input
channels in a sequential, circular manner. For example,
the first 24-bit packet output on SDO0 corresponds to
analog input channel 0, followed by the packets for chan-
nels 1 through 7. The data output on SDO0 then wraps
back to channel 0, and this pattern repeats indefinitely.
Other SDO lanes follow a similar circular pattern, except
the first packet presented on each lane corresponds to
its associated analog input channel.
Full Eight Lane Serial CMOS Output Data Capture
As shown in Table 2, full 200ksps per channel throughput
canbeachievedwitha45MHzSCKIfrequencybycapturing
the first packet (24 SCKI cycles total) from all eight serial
data output lanes SDO0 to SDO7. This configuration also
allowsconversionresultsfromallchannelstobecaptured
using as few as 16 SCKI cycles if the 3-bit analog channel
ID and 3-bit SoftSpan code are not needed and the device
SoftSpan configuration is not being changed. Multi-lane
data capture is usually best suited for use with FPGA
or CPLD capture hardware, but may be useful in other
application-specific cases.
ꢀꢁ ꢂ ꢃ
ꢊꢋꢌꢍ
CS
ꢌꢈꢏꢐ ꢁꢄꢅꢆꢇ ꢈARꢉ
ꢁꢄꢅꢆꢇ ꢈARꢉ
ꢅꢉꢟ ꢌꢠꢡꢢꢌꢣꢤꢥ ꢈꢄꢅꢗꢐꢦꢋRAꢇꢐꢄꢅ ꢟꢄRꢁ
ꢌꢁꢐ ꢁꢄꢅꢆꢇ ꢈARꢉ
ꢇꢟꢄ AꢜꢜꢚꢛꢉRꢄ ꢟꢄRꢁꢌ Aꢅꢁ ꢄꢅꢉ ꢀARꢇꢐAꢜ ꢟꢄRꢁ
ꢁꢄꢅꢆꢇ ꢈARꢉ
ꢝꢄꢧꢉRꢟRꢐꢇꢉꢌ ꢐꢅꢇꢉRꢅAꢜ ꢈꢄꢅꢗꢐꢦ RꢉꢦꢐꢌꢇꢉRꢞ
ꢝꢐꢅꢇꢉRꢅAꢜ ꢈꢄꢅꢗꢐꢦ RꢉꢦꢐꢌꢇꢉR RꢉꢇAꢐꢅꢌ ꢈꢋRRꢉꢅꢇ ꢧAꢜꢋꢉꢞ
ꢘꢙꢚꢛ
ꢘꢙꢚꢛ
ꢌꢈꢏꢄ
ꢘꢙꢚꢛ
ꢘꢙꢚꢛ
ꢁꢐꢌ
ꢈꢘAꢅꢅꢉꢜ ꢒ ꢀAꢈꢏꢉꢇ
ꢝꢀARꢇꢐAꢜꢞ
ꢌꢁꢄꢃ
ꢈꢘAꢅꢅꢉꢜ ꢃ ꢀAꢈꢏꢉꢇ
ꢈꢘAꢅꢅꢉꢜ ꢎ ꢀAꢈꢏꢉꢇ
ꢈꢘAꢅꢅꢉꢜ ꢕ ꢀAꢈꢏꢉꢇ
ꢈꢘAꢅꢅꢉꢜ ꢃ ꢀAꢈꢏꢉꢇ
ꢈꢘAꢅꢅꢉꢜ ꢑ ꢀAꢈꢏꢉꢇ
ꢈꢘAꢅꢅꢉꢜ ꢕ ꢀAꢈꢏꢉꢇ
ꢢ
ꢉꢅ
ꢢ
ꢘꢙꢚꢛ
ꢘꢙꢚꢛ
ꢈꢘAꢅꢅꢉꢜ ꢑ ꢀAꢈꢏꢉꢇ
ꢝꢀARꢇꢐAꢜꢞ
ꢌꢁꢄꢎ
ꢑꢒꢓꢔꢕꢖ ꢗꢕꢎ
Figure 17. Internal SoftSpan Configuration Register Behavior. Serial CMOS Bus Response to CS
Rev A
31
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
Fewer Than Eight Lane Serial CMOS Output Data Capture
Programming the SoftSpan Configuration Register in
CMOS I/O Mode
Applications that cannot accommodate the full eight lanes
of serial data capture may employ fewer lanes without
reconfiguring the LTC2358-16. For example, capturing
the first two packets (48 SCKI cycles total) from SDO0,
SDO2, SDO4, and SDO6 provides data for analog input
channels 0 and 1, 2 and 3, 4 and 5, and 6 and 7, respec-
tively,usingfouroutputlanes.Similarly,capturingthefirst
four packets (96 SCKI cycles total) from SDO0 and SDO4
provides data for analog input channels 0 to 3 and 4 to
7, respectively, using two output lanes. If only one lane
can be accommodated, capturing the first eight packets
(192 SCKI cycles total) from SDO0 provides data for all
analog input channels. As shown in Table 2, full 200ksps
per channel throughput can be achieved with a 90MHz
SCKI frequency in the four lane case, but the maximum
CMOS SCKI frequency of 100MHz limits the throughput
to less than 200ksps per channel in the two lane and one
lane cases. Finally, note that in choosing the number of
lanes and which lanes to use for data capture, the user is
notrestrictedtothespecificcasesmentionedabove.Other
choices may be more optimal in particular applications.
The internal 24-bit SoftSpan configuration register con-
trols the SoftSpan range for all analog input channels of
the LTC2358-16. The default state of this register after
power-up or resetting the device is all ones, configuring
each channel to convert in SoftSpan 7, the 2.5 • V
REFBUF
range (see Table 1a). The state of this register may be
modifiedbyprovidinganew24-bitSoftSpanconfiguration
word on SDI during the data transaction window shown
in Figure 16. New SoftSpan configuration words are only
accepted within this recommended data transaction win-
dow, but SoftSpan changes take effect immediately with
no additional analog input settling time required before
starting the next conversion. Setting a channel’s SoftSpan
code to SS[2:0] = 000 immediately disables the channel,
resultinginacorrespondingreductionint
onthenext
CONV
conversion.Similarly,enablingapreviouslydisabledchan-
nelrequiresnoadditionalanaloginputsettlingtimebefore
starting the next conversion. The mapping between the
serial SoftSpan configuration word, the internal SoftSpan
configuration register, and each channel’s 3-bit SoftSpan
code is illustrated in Figure 18.
Table 2. Required SCKI Frequency to Achieve Various Throughputs in Common Output Bus Configurations with Eight Channels Enabled.
Shaded Entries Denote Throughputs That Are Not Achievable in a Given Configuration. Calculated Using fSCKI = (Number of SCKI
Cycles)/(tACQ(MIN) – tQUIET
)
REQUIRED f
200ksps/CHANNEL
(tACQ = 570ns)
(MHz) TO ACHIEVE THROUGHPUT OF
SCKI
NUMBER OF SDO
LANES
NUMBER OF SCKI
CYCLES
I/O MODE
100ksps/CHANNEL
(tACQ = 5570ns)
50ksps/CHANNEL
(tACQ = 15570ns)
8
8
4
2
1
1
16
24
30
45
3
2
5
2
CMOS
LVDS
48
90
9
4
96
Not Achievable
Not Achievable
180 (360Mbps)
18
35
7
13
192
96
18 (36Mbps)
7 (14Mbps)
Rev A
32
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
CMOS I/O MODE
ꢖ
ꢖ
ꢖ
ꢀꢀꢋꢓꢀꢐꢒꢓ
ꢀꢐꢒꢓ
ꢀꢐꢒꢓꢢ
ꢀꢐꢒꢓ
ꢀꢋꢓ
ꢃ
ꢁ
ꢂ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢃꢊ ꢃꢃ ꢃꢁ ꢃꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢁꢊ ꢁꢃ ꢁꢁ ꢁꢂ ꢁꢄ
ꢖ
ꢖ
ꢢꢀꢋꢓꢀꢐꢒꢓ
ꢀꢐꢒꢓꢟ
ꢋꢌꢍꢎꢏ ꢐARꢑ
ꢀꢁꢂ ꢀꢁꢁ ꢀꢁꢃ ꢀꢁꢊ ꢀꢃꢉ ꢀꢃꢈ ꢀꢃꢇ ꢀꢃꢆ ꢀꢃꢅ ꢀꢃꢄ ꢀꢃꢂ ꢀꢃꢁ ꢀꢃꢃ ꢀꢃꢊ ꢀꢉ ꢀꢈ ꢀꢇ ꢀꢆ ꢀꢅ ꢀꢄ ꢀꢂ ꢀꢁ ꢀꢃ ꢀꢊ
ꢀꢔꢕꢖꢀꢗꢘꢙ ꢐꢌꢍꢚꢓꢛꢜRAꢏꢓꢌꢍ ꢝꢌRꢋ
LVDS I/O MODE
ꢖ
ꢖ
ꢀꢐꢒꢓ
ꢁ
ꢀꢐꢒꢓꢢ
ꢀꢐꢒꢓ
ꢞꢟꢠꢋꢀꢡ
ꢃ
ꢂ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢃꢊ ꢃꢃ ꢃꢁ ꢃꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢁꢊ ꢁꢃ ꢁꢁ ꢁꢂ ꢁꢄ
ꢖ
ꢖ
ꢖ
ꢖ
ꢖ
ꢢꢀꢋꢓꢀꢐꢒꢓ
ꢀꢐꢒꢓꢟ
ꢀꢀꢋꢓꢀꢐꢒꢓ
ꢀꢀꢋꢓꢀꢐꢒꢓ
ꢢꢀꢋꢓꢀꢐꢒꢓ
ꢀꢋꢓ
ꢞꢟꢠꢋꢀꢡ
ꢋꢌꢍꢎꢏ ꢐARꢑ
ꢀꢁꢂ ꢀꢁꢁ ꢀꢁꢃ ꢀꢁꢊ ꢀꢃꢉ ꢀꢃꢈ ꢀꢃꢇ ꢀꢃꢆ ꢀꢃꢅ ꢀꢃꢄ ꢀꢃꢂ ꢀꢃꢁ ꢀꢃꢃ ꢀꢃꢊ ꢀꢉ ꢀꢈ ꢀꢇ ꢀꢆ ꢀꢅ ꢀꢄ ꢀꢂ ꢀꢁ ꢀꢃ ꢀꢊ
ꢀꢔꢕꢖꢀꢗꢘꢙ ꢐꢌꢍꢚꢓꢛꢜRAꢏꢓꢌꢍ ꢝꢌRꢋ
INTERNAL 24-BIT SoftSpan CONFIGURATION REGISTER
(SAME FOR CMOS AND LVDS)
ꢁꢂ
ꢐꢢAꢍꢍꢑꢟ ꢇ ꢀꢔꢕꢖꢀꢗꢘꢙ ꢐꢢAꢍꢍꢑꢟ ꢆ ꢀꢔꢕꢖꢀꢗꢘꢙ ꢐꢢAꢍꢍꢑꢟ ꢅ ꢀꢔꢕꢖꢀꢗꢘꢙ ꢐꢢAꢍꢍꢑꢟ ꢄ ꢀꢔꢕꢖꢀꢗꢘꢙ ꢐꢢAꢍꢍꢑꢟ ꢂ ꢀꢔꢕꢖꢀꢗꢘꢙ ꢐꢢAꢍꢍꢑꢟ ꢁ ꢀꢔꢕꢖꢀꢗꢘꢙ ꢐꢢAꢍꢍꢑꢟ ꢃ ꢀꢔꢕꢖꢀꢗꢘꢙ ꢐꢢAꢍꢍꢑꢟ ꢊ ꢀꢔꢕꢖꢀꢗꢘꢙ
ꢐꢌꢋꢑ ꢀꢀꢣꢁꢤꢊꢥ ꢐꢌꢋꢑ ꢀꢀꢣꢁꢤꢊꢥ ꢐꢌꢋꢑ ꢀꢀꢣꢁꢤꢊꢥ ꢐꢌꢋꢑ ꢀꢀꢣꢁꢤꢊꢥ ꢐꢌꢋꢑ ꢀꢀꢣꢁꢤꢊꢥ ꢐꢌꢋꢑ ꢀꢀꢣꢁꢤꢊꢥ ꢐꢌꢋꢑ ꢀꢀꢣꢁꢤꢊꢥ ꢐꢌꢋꢑ ꢀꢀꢣꢁꢤꢊꢥ
ꢁꢁ
ꢁꢃ
ꢁꢊ
ꢃꢉ
ꢃꢈ
ꢃꢇ
ꢃꢆ
ꢃꢅ
ꢃꢄ
ꢃꢂ
ꢃꢁ
ꢃꢃ
ꢃꢊ
ꢉ
ꢈ
ꢇ
ꢆ
ꢅ
ꢄ
ꢂ
ꢁ
ꢃ
ꢊ
ꢁꢂꢅꢈꢃꢆ ꢚꢃꢈ
Figure 18. Mapping Between Serial SoftSpan Configuration Word, Internal SoftSpan
Configuration Register, and SoftSpan Code for Each Analog Input Channel
Iffewerthan24SCKIrisingedgesareprovidedduringadata
transactionwindow,thepartialwordreceivedonSDIwillbe
ignoredandtheSoftSpanconfigurationregisterwillnotbe
updated. If exactly 24 SCKI rising edges are provided, the
SoftSpan configuration register will be updated to match
the received SoftSpan configuration word, S[23:0]. The
one exception to this behavior occurs when S[23:0] is all
zeros. In this case, the SoftSpan configuration register
will not be updated, allowing applications to retain the
current SoftSpan configuration state by idling SDI low. If
more than24SCKI risingedges areprovided during a data
transaction window, each complete 24-bit word received
onSDIwillbeinterpretedasanewSoftSpanconfiguration
word and applied to the SoftSpan configuration register
as described above. Any partial words are ignored.
After the opening of a new data transaction window at the
falling edge of BUSY, the user supplies a 24-bit SoftSpan
configuration word on SDI during the first 24 SCKI cycles.
Thisnewwordoverwritestheinternalconfigurationregister
contentsfollowingthe24thSCKIrisingedge.Theuserthen
holds SDI low for the remainder of the data transaction
windowcausingtheregistertoretainitscontentsregardless
of the number of additional SCKI cycles applied. SoftSpan
settings may be retained across multiple conversions by
holding SDI low for the entire data transaction window,
regardless of the number of SCKI cycles applied.
Serial LVDS I/O Mode
In LVDS I/O mode, information is transmitted using posi-
+
−
tive and negative signal pairs (LVDS /LVDS ) with bits
+
−
differentially encoded as (LVDS − LVDS ). These signals
are typically routed using differential transmission lines
Typically, applications will update the SoftSpan configura-
tion register in the manner shown in Figures 16 and 17.
Rev A
33
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
with 100Ω characteristic impedance. Logical 1’s and 0’s
are nominally represented by differential +350mV and
−350mV,respectively.Forclarity,allLVDStimingdiagrams
and interface discussions adopt the logical rather than
physical convention.
version on the falling edge of BUSY. In the recommended
use case, the data transaction should be completed with
a minimum t
time of 20ns prior to the start of the
QUIET
next conversion, as shown in Figure 19. New SoftSpan
configuration words are only accepted within this recom-
mended data transaction window, but SoftSpan changes
take effect immediately with no additional analog input
settling time required before starting the next conversion.
It is still possible to read conversion data after starting the
nextconversion,butthiswilldegradeconversionaccuracy
and therefore is not recommended.
As shown in Figure 19, in LVDS I/O mode the serial data
busconsistsofaserialclockdifferentialinput, SCKI, serial
data differential input, SDI, serial clock differential output,
SCKO, and serial data differential output, SDO. Communi-
cation with the LTC2358-16 across this bus occurs during
predefined data transaction windows. Within a window,
the device accepts 24-bit SoftSpan configuration words
for the next conversion on SDI and outputs 24-bit packets
containing conversion results and channel configuration
information from the previous conversion on SDO. New
data transaction windows open 10ms after powering up
or resetting the LTC2358-16, and at the end of each con-
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SDO is updated with the
latestconversionresultsfromanaloginputchannel0.Both
rising and falling edges on SCKI serially clock conversion
resultsandanaloginputchannelconfigurationinformation
out on SDO. SCKI is also echoed on SCKO, skew-matched
CS ꢓ ꢔꢋ ꢓ ꢊ
ꢀAꢐꢔꢟꢘ ꢍ
ꢀAꢐꢔꢟꢘ ꢍ ꢢ ꢃ
ꢙ
ꢌꢝꢌ
ꢙ
ꢌꢍꢎꢩ
ꢌꢍꢎ
ꢏꢌꢐꢑꢀꢒ
ꢙ
ꢌꢍꢎꢟ
ꢛꢜꢀꢝ
ꢏꢌꢐꢑꢀꢒ
ꢙ
ꢙ
ꢌꢑꢍꢎ
Aꢌꢚ
ꢙ
ꢛꢜꢀꢝꢟꢩ
Rꢘꢌꢑꢐꢐꢘꢍꢋꢘꢋ ꢋAꢗA ꢗRAꢍꢀAꢌꢗꢠꢑꢍ ꢡꢠꢍꢋꢑꢡ
ꢙ
ꢙ
ꢚꢜꢠꢘꢗ
ꢀꢌꢞꢠ
ꢙ
ꢀꢌꢞꢠꢩ
ꢀꢌꢞꢠ
ꢏꢟꢎꢋꢀꢒ
ꢃ
ꢁ
ꢂ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢃꢊ ꢃꢃ ꢃꢁ ꢃꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢁꢊ ꢁꢃ ꢁꢁ ꢁꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢃꢈꢅ ꢃꢈꢆ ꢃꢈꢇ ꢃꢈꢈ ꢃꢈꢉ ꢃꢉꢊ ꢃꢉꢃ ꢃꢉꢁ
ꢙ
ꢙ
ꢙ
ꢙ
ꢩꢀꢋꢠꢀꢌꢞꢠ
ꢀꢌꢞꢠꢟ
ꢀꢀꢋꢠꢀꢌꢞꢠ
ꢩꢀꢋꢠꢀꢌꢞꢠ
ꢙ
ꢀꢀꢋꢠꢀꢌꢞꢠ
ꢀꢋꢠ
ꢏꢟꢎꢋꢀꢒ
ꢋꢑꢍꢖꢗ ꢌARꢘ
ꢀꢁꢂ ꢀꢁꢁ ꢀꢁꢃ ꢀꢁꢊ ꢀꢃꢉ ꢀꢃꢈ ꢀꢃꢇ ꢀꢃꢆ ꢀꢃꢅ ꢀꢃꢄ ꢀꢃꢂ ꢀꢃꢁ ꢀꢃꢃ ꢀꢃꢊ ꢀꢉ ꢀꢈ ꢀꢇ ꢀꢆ ꢀꢅ ꢀꢄ ꢀꢂ ꢀꢁ ꢀꢃ ꢀꢊ
ꢙ
ꢀꢣꢤꢙꢀꢥꢦꢧ ꢌꢑꢍꢕꢠꢨꢜRAꢗꢠꢑꢍ ꢡꢑRꢋ ꢕꢑR ꢌꢑꢍꢎꢘRꢀꢠꢑꢍ ꢍ ꢢ ꢃ
ꢋꢀꢋꢑꢛꢜꢀꢝꢟ
ꢙ
ꢀꢞꢘꢡ
ꢙ
ꢩꢀꢋꢑꢀꢌꢞꢠ
ꢀꢌꢞꢑ
ꢏꢟꢎꢋꢀꢒ
ꢙ
ꢋꢀꢋꢑꢀꢌꢞꢠ
ꢀꢋꢑ
ꢏꢟꢎꢋꢀꢒ
ꢋꢑꢍꢖꢗ ꢌARꢘ
ꢋꢃꢅ
ꢋꢃꢄ ꢋꢃꢂ ꢋꢃꢁ ꢋꢃꢃ ꢋꢃꢊ ꢋꢉ ꢋꢈ ꢋꢇ ꢋꢆ ꢋꢅ ꢋꢄ ꢋꢂ ꢋꢁ ꢋꢃ ꢋꢊ
ꢌꢑꢍꢎꢘRꢀꢠꢑꢍ Rꢘꢀꢜꢟꢗ
ꢊ
ꢊ
ꢌꢁ ꢌꢃ ꢌꢊ ꢀꢀꢁ ꢀꢀꢃ ꢀꢀꢊ ꢋꢃꢅ ꢋꢃꢄ ꢋꢃꢂ
ꢌꢩAꢍꢍꢘꢟ ꢠꢋ ꢀꢣꢤꢙꢀꢥꢦꢧ
ꢊ
ꢌꢁ ꢌꢃ ꢌꢊ ꢀꢀꢁ ꢀꢀꢃ ꢀꢀꢊ ꢋꢃꢅ
ꢌꢑꢍꢎꢘRꢀꢠꢑꢍ
Rꢘꢀꢜꢟꢗ
ꢌꢩAꢍꢍꢘꢟ ꢠꢋ ꢀꢣꢤꢙꢀꢥꢦꢧ
ꢌꢩAꢍꢍꢘꢟ ꢊ
ꢁꢄꢪꢛꢠꢗ ꢔAꢌꢞꢘꢗ
ꢌꢑꢍꢎꢘRꢀꢠꢑꢍ ꢍ
ꢌꢩAꢍꢍꢘꢟ ꢃ
ꢌꢩAꢍꢍꢘꢟ ꢇ
ꢌꢩAꢍꢍꢘꢟ ꢊ
ꢁꢄꢪꢛꢠꢗ ꢔAꢌꢞꢘꢗ
ꢌꢑꢍꢎꢘRꢀꢠꢑꢍ ꢍ
ꢁꢂꢅꢈꢃꢆ ꢕꢃꢉ
ꢁꢄꢪꢛꢠꢗ ꢔAꢌꢞꢘꢗ
ꢁꢄꢪꢛꢠꢗ ꢔAꢌꢞꢘꢗ
ꢌꢑꢍꢎꢘRꢀꢠꢑꢍ ꢍ ꢌꢑꢍꢎꢘRꢀꢠꢑꢍ ꢍ
Figure 19. Serial LVDS I/O Mode
Rev A
34
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
tothedataonSDO.Wheneverpossible,itisrecommended
that rising and falling edges of SCKO be used to capture
DDR serial output data on SDO, as this will yield the best
robustness to delay variations over supply and tempera-
ture. SCKI rising and falling edges also latch SoftSpan
configuration words provided on SDI, which are used to
programtheinternal24-bitSoftSpanconfigurationregister.
See the section Programming the SoftSpan Configuration
Register in LVDS I/O Mode for further details. As shown in
Figure 20, the LVDS bus is enabled when CS is low and is
disabled and Hi-Z when CS is high, allowing the bus to be
shared across multiple devices. Due to the high speeds
involved in LVDS signaling, LVDS bus sharing must be
carefullyconsidered.Transmissionlinelimitationsimposed
by the shared bus may limit the maximum achievable bus
clock speed. LVDS inputs are internally terminated with a
100Ω differential resistor when CS is low, while outputs
must be differentially terminated with a 100Ω resistor at
the receiver (FPGA). SCKI must idle in the low state in
LVDS I/O mode, including when transitioning CS.
ThedataonSDOaregroupedinto24-bitpacketsconsisting
of a 16-bit conversion result followed by two zeros, 3-bit
analog channel ID, and 3-bit SoftSpan code, all presented
MSBfirst.AssuggestedinFigures19and20,SDOoutputs
these packets for all analog input channels in a sequential,
circularmanner.Forexample,thefirst24-bitpacketoutput
on SDO corresponds to analog input channel 0, followed
by the packets for channels 1 through 7. The data output
on SDO then wraps back to channel 0, and this pattern
repeats indefinitely.
ꢆꢇ ꢈ ꢉ
ꢎꢏꢄꢐ
ꢀꢁꢂꢃꢄꢅ
CS
ꢀꢁꢂꢃꢄꢅ
ꢣ
ꢍꢊ
ꢣ
ꢇꢔꢄ
ꢄꢁꢑꢔ
ꢀꢒꢓꢇꢄꢅ
ꢇꢃꢊꢋꢌ ꢁARꢍ
ꢇꢃꢊꢋꢌ ꢁARꢍ
ꢄꢇꢔ
ꢀꢒꢓꢇꢄꢅ
ꢊꢍꢠ ꢄꢡꢢꢣꢄꢤꢥꢦ ꢁꢃꢊꢛꢔꢧꢏRAꢌꢔꢃꢊ ꢠꢃRꢇ
ꢀꢃꢓꢍRꢠRꢔꢌꢍꢄ ꢔꢊꢌꢍRꢊAꢒ ꢁꢃꢊꢛꢔꢧ RꢍꢧꢔꢄꢌꢍRꢅ
ꢌꢠꢃ AꢒꢒꢞꢟꢍRꢃ ꢠꢃRꢇꢄ Aꢊꢇ ꢃꢊꢍ ꢆARꢌꢔAꢒ ꢠꢃRꢇ
ꢀꢔꢊꢌꢍRꢊAꢒ ꢁꢃꢊꢛꢔꢧ RꢍꢧꢔꢄꢌꢍR RꢍꢌAꢔꢊꢄ ꢁꢏRRꢍꢊꢌ ꢓAꢒꢏꢍꢅ
ꢇꢃꢊꢋꢌ ꢁARꢍ
ꢇꢃꢊꢋꢌ ꢁARꢍ
ꢜꢝꢞꢟ
ꢜꢝꢞꢟ
ꢄꢁꢑꢃ
ꢀꢒꢓꢇꢄꢅ
ꢜꢝꢞꢟ
ꢜꢝꢞꢟ
ꢕꢖꢗꢘꢙꢚ ꢛꢕꢉ
ꢁꢜAꢊꢊꢍꢒ ꢖ ꢆAꢁꢑꢍꢌ
ꢀꢆARꢌꢔAꢒꢅ
ꢄꢇꢃ
ꢀꢒꢓꢇꢄꢅ
ꢁꢜAꢊꢊꢍꢒ ꢉ ꢆAꢁꢑꢍꢌ
ꢁꢜAꢊꢊꢍꢒ ꢙ ꢆAꢁꢑꢍꢌ
ꢁꢜAꢊꢊꢍꢒ ꢕ ꢆAꢁꢑꢍꢌ
Figure 20. Internal SoftSpan Configuration Register Behavior. Serial LVDS Bus Response to CS
Rev A
35
For more information www.analog.com
LTC2358-16
APPLICATIONS INFORMATION
Serial LVDS Output Data Capture
If fewer than 24 SCKI edges (rising plus falling) are
provided during a data transaction window, the partial
word received on SDI will be ignored and the SoftSpan
configuration register will not be updated. If exactly 24
SCKI edges are provided, the SoftSpan configuration
register will be updated to match the received SoftSpan
configuration word, S[23:0]. The one exception to this
behavior occurs when S[23:0] is all zeros. In this case,
the SoftSpan configuration register will not be updated,
allowing applications to retain the current SoftSpan con-
figuration state by idling SDI low. If more than 24 SCKI
edgesareprovidedduringadatatransactionwindow,each
complete 24-bit word received on SDI will be interpreted
as a new SoftSpan configuration word and applied to the
SoftSpan configuration register as described above. Any
partial words are ignored.
As shown in Table 2, full 200ksps per channel throughput
can be achieved with a 180MHz SCKI frequency by captur-
ing eight packets (96 SCKI cycles total) of DDR data from
SDO. The LTC2358-16 supports LVDS SCKI frequencies
up to 250MHz.
Programming the SoftSpan Configuration Register in
LVDS I/O Mode
The internal 24-bit SoftSpan configuration register con-
trols the SoftSpan range for all analog input channels of
the LTC2358-16. The default state of this register after
power-up or resetting the device is all ones, configuring
each channel to convert in SoftSpan 7, the 2.5 • V
REFBUF
range (see Table 1a). The state of this register may be
modifiedbyprovidinganew24-bitSoftSpanconfiguration
word on SDI during the data transaction window shown
in Figure 19. New SoftSpan configuration words are only
accepted within this recommended data transaction win-
dow, but SoftSpan changes take effect immediately with
no additional analog input settling time required before
starting the next conversion. Setting a channel’s SoftSpan
code to SS[2:0] = 000 immediately disables the channel,
Typically, applications will update the SoftSpan configura-
tion register in the manner shown in Figures 19 and 20.
After the opening of a new data transaction window at
the falling edge of BUSY, the user supplies a 24-bit DDR
SoftSpan configuration word on SDI during the first 12
SCKI cycles. This new word overwrites the internal con-
th
figuration register contents following the 12 SCKI falling
edge. The user then holds SDI low for the remainder of
the data transaction window causing the register to retain
its contents regardless of the number of additional SCKI
cycles applied. SoftSpan settings may be retained across
multiple conversions by holding SDI low for the entire
data transaction window, regardless of the number of
SCKI cycles applied
resultinginacorrespondingreductionint
onthenext
CONV
conversion.Similarly,enablingapreviouslydisabledchan-
nelrequiresnoadditionalanaloginputsettlingtimebefore
starting the next conversion. The mapping between the
serial SoftSpan configuration word, the internal SoftSpan
configuration register, and each channel’s 3-bit SoftSpan
code is illustrated in Figure 18.
Rev A
36
For more information www.analog.com
LTC2358-16
BOARD LAYOUT
To obtain the best performance from the LTC2358-16, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Also minimize the length of the REFBUF to GND (Pin 20)
bypass capacitor return loop, and avoid routing CNV near
signals which could potentially disturb its rising edge.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common re-
turns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this con-
verter, including schematics and PCB layout, please refer
to DC2365, the evaluation kit for the LTC2358-16.
Rev A
37
For more information www.analog.com
LTC2358-16
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2358-16#packaging for the most recent package drawings.
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
ꢩReꢪeꢫeꢬꢭe ꢀꢜꢔ ꢟꢨꢘ ꢢ ꢇꢐꢣꢇꢃꢣꢈꢎꢖꢇ Rev Aꢮ
ꢎꢏꢈꢐ ꢍ ꢎꢏꢕꢐ
ꢐꢏꢐꢇ Rꢊꢅ
ꢑꢏꢇꢇ ꢒꢓꢔ
ꢎꢏꢇꢇ ꢒꢓꢔ
ꢂꢃ
ꢂꢃ
ꢓꢊꢊ ꢚꢛꢜꢊꢝ ꢂ
ꢈ
ꢕ
ꢈ
ꢕ
ꢇꢏꢐꢇ ꢒꢓꢔ
ꢑꢏꢇꢇ ꢒꢓꢔ
ꢎꢏꢇꢇ ꢒꢓꢔ
ꢐꢏꢐꢇ Rꢊꢅ
ꢎꢏꢈꢐ ꢍ ꢎꢏꢕꢐ
ꢇꢏꢕꢇ ꢍ ꢇꢏꢉꢇ
A
A
ꢆAꢔꢞAꢘꢊ ꢛꢙꢜꢀꢠꢚꢊ
ꢔꢇꢏꢉꢇ ꢍ ꢇꢏꢐꢇ
ꢈꢏꢉꢇ ꢗꢠꢚ
Rꢊꢔꢛꢗꢗꢊꢚꢟꢊꢟ ꢓꢛꢀꢟꢊR ꢆAꢟ ꢀAꢦꢛꢙꢜ
Aꢆꢆꢀꢦ ꢓꢛꢀꢟꢊR ꢗAꢓꢞ ꢜꢛ ARꢊAꢓ ꢜꢤAꢜ ARꢊ ꢚꢛꢜ ꢓꢛꢀꢟꢊRꢊꢟ
ꢈꢏꢖꢇ
ꢈꢏꢉꢐ ꢍ ꢈꢏꢂꢐ ꢗAꢁ
ꢈꢈꢌ ꢍ ꢈꢉꢌ
Rꢇꢏꢇꢃ ꢍ ꢇꢏꢕꢇ
ꢘAꢙꢘꢊ ꢆꢀAꢚꢊ
ꢇꢏꢕꢐ
ꢇꢌ ꢍ ꢎꢌ
ꢈꢈꢌ ꢍ ꢈꢉꢌ
ꢈꢏꢇꢇ Rꢊꢅ
ꢇꢏꢐꢇ
ꢒꢓꢔ
ꢇꢏꢇꢑ ꢍ ꢇꢏꢕꢇ
ꢇꢏꢈꢎ ꢍ ꢇꢏꢕꢎ
ꢇꢏꢇꢐ ꢍ ꢇꢏꢈꢐ
ꢇꢏꢂꢐ ꢍ ꢇꢏꢎꢐ
ꢓꢊꢔꢜꢠꢛꢚ A ꢍ A
e ꢉ
ꢚꢛꢜꢊꢝ
ꢈꢏ ꢆAꢔꢞAꢘꢊ ꢟꢠꢗꢊꢚꢓꢠꢛꢚꢓ ꢔꢛꢚꢅꢛRꢗ ꢜꢛ ꢡꢊꢟꢊꢔ ꢢꢗꢓꢣꢇꢕꢖ ꢆAꢔꢞAꢘꢊ ꢛꢙꢜꢀꢠꢚꢊ
ꢕꢏ ꢟꢠꢗꢊꢚꢓꢠꢛꢚꢓ ARꢊ ꢠꢚ ꢗꢠꢀꢀꢠꢗꢊꢜꢊRꢓ
ꢉꢏ ꢟꢠꢗꢊꢚꢓꢠꢛꢚꢓ ꢛꢅ ꢆAꢔꢞAꢘꢊ ꢟꢛ ꢚꢛꢜ ꢠꢚꢔꢀꢙꢟꢊ ꢗꢛꢀꢟ ꢅꢀAꢓꢤꢏ ꢗꢛꢀꢟ ꢅꢀAꢓꢤ
ꢓꢤAꢀꢀ ꢚꢛꢜ ꢊꢁꢔꢊꢊꢟ ꢇꢏꢕꢐꢥꢥ ꢛꢚ Aꢚꢦ ꢓꢠꢟꢊꢧ ꢠꢅ ꢆRꢊꢓꢊꢚꢜ
ꢂꢏ ꢆꢠꢚꢣꢈ ꢠꢚꢟꢊꢚꢜꢠꢅꢠꢊR ꢠꢓ A ꢗꢛꢀꢟꢊꢟ ꢠꢚꢟꢊꢚꢜAꢜꢠꢛꢚꢧ ꢇꢏꢐꢇꢥꢥ ꢟꢠAꢗꢊꢜꢊR
ꢐꢏ ꢟRAꢨꢠꢚꢘ ꢠꢓ ꢚꢛꢜ ꢜꢛ ꢓꢔAꢀꢊ
ꢔꢛꢗꢆꢛꢚꢊꢚꢜ
ꢆꢠꢚ ꢰAꢈꢱ
ꢀꢁꢂꢃ ꢀꢄꢅꢆ ꢇꢈꢈꢉ Rꢊꢋ A
ꢜRAꢦ ꢆꢠꢚ ꢈ
ꢒꢊꢋꢊꢀ
ꢆAꢔꢞAꢘꢊ ꢠꢚ ꢜRAꢦ ꢀꢛAꢟꢠꢚꢘ ꢛRꢠꢊꢚꢜAꢜꢠꢛꢚ
Rev A
38
For more information www.analog.com
LTC2358-16
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
05/18 Updated max limits for analog input leakage
1, 3
Rev A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
39
LTC2358-16
TYPICAL APPLICATION
Amplify Differential Signals with Gain of 10
Over a Wide Common Mode Range with Buffered Analog Inputs
INTERNAL HI-Z BUFFERS
ARBITRARY
31V
ALLOW OPTIONAL
+
31V
kΩ PASSIVE FILTERS
LTC2057HV
GAIN = 10
LTC2057HV
+
–
IN
24V
3.65k
0.1µF
BUFFERED
ANALOG
INPUTS
2.49k
V
+
–
CC
COMMON MODE
INPUT RANGE
IN0
IN0
549Ω
2.49k
2.2nF
LTC2358-16
3.65k
DIFFERENTIAL MODE
INPUT RANGE: 500ꢀV
–
+
V
REFBUF
47µF
REFIN
EE
0V
BW = 10kHz
–
IN
0.1µF
0.1µF
–7V
–7V
235816 TA02
ONLY CHANNEL 0 SHOWN FOR CLARITY
RELATED PARTS
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2358-18
18-Bit, 200ksps/Ch, Buffered 8-Channel
10.24V Buffered SoftSpan Inputs with 30V Common Mode Range,
P-P
Simultaneous Sampling, 3.5LSB INL, Serial ADC 96.4dB SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
LTC2348-18/LTC2348-16 18-/16-Bit, 200ksps/Ch, 8-Channel Simultaneous 10.24V SoftSpan Inputs with Wide Common Mode Range, 97dB/94dB
Sampling, 3LSB/ 1LSB INL, Serial ADC
SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
LTC2335-18/LTC2335-16 18-/16-Bit, 1Msps, 8-Channel Multiplexed,
3LSB/ 1LSB INL, Serial ADC
10.24V SoftSpan Inputs with Wide Common Mode Range, 97dB/94dB
SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
LTC2345-18/LTC2345-16 18-/16-Bit, 200ksps/Ch, 8-Channel Simultaneous 4.096V SoftSpan Inputs with Wide Common Mode Range, 92dB/91dB
Sampling, 5LSB/ 1.25LSB INL, Serial ADC
SNR, Serial CMOS and LVDS I/O, 7mm × 7mm QFN-48 Package
LTC2378-20/LTC2377-20/ 20-Bit, 1Msps/500ksps/250ksps,
2.5V Supply, 5V Fully Differential Input, 104dB SNR, MSOP-16 and
4mm × 3mm DFN-16 Packages
LTC2376-20
0.5ppm INL Serial, Low Power ADC
LTC2338-18/LTC2337-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial,
LTC2336-18 Low Power ADC
LTC2328-18/LTC2327-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial,
LTC2326-18 Low Power ADC
LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC
5V Supply, 10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package
5V Supply, 10.24V Pseudo-Differential Input, 95dB SNR,
MSOP-16 Package
5V Supply, 8 Channel Multiplexed, Configurable Input Range, 100dB SNR,
DGC, 5mm × 5mm QFN-32 Package
LTC2379-18/LTC2378-18/ 18-Bit,1.6Msps/1Msps/500ksps/250ksps, Serial, 2.5V Supply, Differential Input, 101.2dB SNR, 5V Input Range, DGC, Pin
LTC2377-18/LTC2376-18 Low Power ADC Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps, Serial, 2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC, Pin
LTC2377-16/LTC2376-16 Low Power ADC
LTC2387-18/LTC2387-16 18-/16-Bit, 15Msps SAR ADC
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
5V Supply, Differential Input, 93.8dB SNR, 5mm × 5mm QFN Package
LTC1859/LTC1858/
LTC1857
16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC
10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,
SSOP-28 Package
DACs
LTC2756/LTC2757
18-Bit, Serial/Parallel I
SoftSpan DAC
1LSB INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm
LQFP-48 Package
OUT
LTC2668
16-Channel 16-/12-Bit 10V V
SoftSpan DACs 4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package
OUT
References
LTC6655
Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8
Package
LT6657
Precision Low Drift Low Noise Buffered Reference 5V/3V/2.5V, 1.5ppm/°C, 0.5ppm Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LTC2057/LTC2057HV
LT6020
High Voltage, Low Noise Zero-Drift Op Amp
Dual, Micropower, 5V/µs, Rail-to-Rail Op Amp
Maximum Input Offset: 4.5µV, Supply Voltage Range: 4.75V to 60V
Maximum Input Offset: 30µV, Maximum Supply Current: 100µA/Amplifier
LT1354/LT1355/LT1356
Single/Dual/Quad 1mA, 12MHz, 400V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads
Rev A
D16870-0-5/18(A)
www.analog.com
40
© ANALOG DEVICES, INC. 2016-2018
相关型号：
LTC2335-18
Buffered Octal, 16-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range
Linear
LTC2335CLX-18#PBF
LTC2335-18 - 18-Bit, 1Msps 8-Channel Differential ±10.24V Input SoftSpan ADC with Wide Input Common Mode Range; Package: LQFP; Pins: 48; Temperature Range: 0°C to 70°C
Linear
LTC2335HLX-18#PBF
LTC2335-18 - 18-Bit, 1Msps 8-Channel Differential ±10.24V Input SoftSpan ADC with Wide Input Common Mode Range; Package: LQFP; Pins: 48; Temperature Range: -40°C to 125°C
Linear
LTC2335ILX-18#PBF
LTC2335-18 - 18-Bit, 1Msps 8-Channel Differential ±10.24V Input SoftSpan ADC with Wide Input Common Mode Range; Package: LQFP; Pins: 48; Temperature Range: -40°C to 85°C
Linear
LTC2336-18
Buffered Octal, 16-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range
Linear
LTC2336CMS-18#PBF
LTC2336-18 - 18-Bit, 250ksps, ±10.24V True Bipolar, Fully Differential Input ADC with 100dB SNR; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
Linear
LTC2337-18
Buffered Octal, 16-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range
Linear
LTC2338-18
Buffered Octal, 16-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range
Linear
©2020 ICPDF网 联系我们和版权申明