LTC2327HMS-18#PBF_技术文档

LTC2327-18

18-Bit, 500ksps, 10ꢀ.24

True Bipolar, Pseudo-Differential

Input ADC with 95dB SNR

DescripTion

FeaTures

The LTC^®2327-18 is a low noise, high speed 18-bit suc-

cessive approximation register (SAR) ADC with pseudo-

differential inputs. Operating from a single 5V supply,

the LTC2327-18 has a 1ꢀ.2ꢁV true bipolar input range,

n

500ksps Throughput Rate

n

±5ꢀLS ꢁIꢀ ꢂ(aꢃx

n

Guaranteed 18-Sit Io (issing Codes

Pseudo-Differential ꢁnputs

n

True Sipolar ꢁnput Ranges ±±6.5ꢄV ±106.2ꢄV ±1.65ꢄ

making it ideal for high voltage applications which require

a wide dynamic range. The LTC2327-18 achieves 5LSꢂ

INLmaximum,nomissingcodesat18bitswith95dꢂSNR.

n

95dS LIR ꢂTypx at f = .kHz

ꢁI

–111dS THD ꢂTypx at f = .kHz

ꢁI

Guaranteed Operation to 125°C

Single 5V Supply

The LTC2327-18 has an onboard single-shot capable

reference buffer and low drift (2ꢀppm/°C max) 2.ꢀꢁ8V

temperature compensated reference. The LTC2327-18

also has a high speed SPI-compatible serial interface that

supports1.8V,2.5V,3.3Vand5Vlogicwhilealsofeaturing

a daisy-chain mode. The fast 5ꢀꢀksps throughput with

no cycle latency makes the LTC2327-18 ideally suited

for a wide variety of high speed applications. An internal

oscillator sets the conversion time, easing external timing

considerations. The LTC2327-18 dissipates only 36mW

and automatically naps between conversions, leading to

reduced power dissipation that scales with the sampling

rate. A sleep mode is also provided to reduce the power

consumption of the LTC2327-18 to 3ꢀꢀμW for further

power savings during inactive periods.

Low Drift (2ꢀppm/°C Max) 2.ꢀꢁ8V Internal Reference

Onboard Single-Shot Capable Reference ꢂuffer

No Pipeline Delay, No Cycle Latency

1.8V to 5V I/O Voltages

SPI-Compatible Serial I/O with Daisy-Chain Mode

Internal Conversion Clock

Power Dissipation 36mW (Typ)

16-Lead MSOP Package

applicaTions

n

Programmable Logic Controllers

n

Industrial Process Control

n

High Speed Data Acquisition

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 77ꢀ5765, 7961132.

n

Portable or Compact Instrumentation

n

ATE

Typical applicaTion

3.k Point FFT f_L= 500kspsV

f_ꢁI= .kHz

0

SNR = 95.3dB

5V

1.8V TO 5V

–20

–40

THD = –113dB

SINAD = 95.2dB

SFDR = –116dB

10µF

2.2µF

0.1µF

+10.24V

–60

+

V

OV

DD

DDLBYP DD

–80

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

–10.24V

+

–

LT^®1468

IN

–100

–120

–140

–160

–180

LTC2327-18

–

IN

SAMPLE CLOCK

REF

REFBUF

REFIN

GND

232718 TA01

100nF

47µF

0

50

100

150

200

250

FREQUENCY (kHz)

232718 TA01b

232718fb

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For more information www.linear.com/LTC2327-18

LTC2327-18

absoluTe MaxiMuM raTings

pin conFiguraTion

ꢂIotes 1V .x

TOP VIEW

Supply Voltage (V )..................................................6V

DD

V

1

2

16 GND

DDLBYP

V

15 OV

DD

Supply Voltage (OV )................................................6V

DD

GND 3

14 SDO

13 SCK

+

–

IN

4

5

Supply ꢂypass Voltage (V

Analog Input Voltage

) ...........................3.2V

DDLꢂYP

12 RDL/SDI

11 BUSY

10 CHAIN

GND 6

REFBUF 7

REFIN 8

+

–

IN , IN ..............................................–16.5V to 16.5V

REFꢂUF...................................................................6V

REFIN ..................................................................2.8V

Digital Input Voltage

9

CNV

MS PACKAGE

16-LEAD PLASTIC MSOP

= 15ꢀ°C, θ = 11ꢀ°C/W

T

JMAX

JA

(Note 3)........................... (GND –ꢀ.3V) to (OV + ꢀ.3V)

DD

Digital Output Voltage

(Note 3)........................... (GND –ꢀ.3V) to (OV + ꢀ.3V)

DD

Power Dissipation.............................................. 5ꢀꢀmW

Operating Temperature Range

LTC2327C ................................................ ꢀ°C to 7ꢀ°C

LTC2327I .............................................–ꢁꢀ°C to 85°C

LTC2327H.......................................... –ꢁꢀ°C to 125°C

Storage Temperature Range .................. –65°C to 15ꢀ°C

orDer inForMaTion ^{http://www6linear6com/product/ꢀTC.3.7-18#orderinfo}

ꢀEAD FREE FꢁIꢁLH

TAPE AID REEꢀ

PART (ARKꢁIG*

PACKAGE DELCRꢁPTꢁOI

16-Lead Plastic MSOP

TE(PERATURE RAIGE

ꢀ°C to 7ꢀ°C

LTC2327CMS-18#PꢂF

LTC2327IMS-18#PꢂF

LTC2327HMS-18#PꢂF

LTC2327CMS-18#TRPꢂF 232718

LTC2327IMS-18#TRPꢂF 232718

LTC2327HMS-18#TRPꢂF 232718

–ꢁꢀ°C to 85°C

–ꢁꢀ°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 5ꢀꢀ unit reels through

designated sales channels with #TRMPꢂF suffix.

232718fb

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For more information www.linear.com/LTC2327-18

LTC2327-18

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature rangeV otherwise specifications are at T_A= .5°C6 ꢂIote 2x

LY(SOꢀ

PARA(ETER

COIDꢁTꢁOIL

(ꢁI

TYP

(AX

UIꢁTL

V

+

l

V

IN

V

IN

V

IN

Absolute Input Range (IN )

(Note 5)

–2.5 • V

– ꢀ.5

2.5 • V

+ ꢀ.5

REFꢂUF

–

+

–

Absolute Input Range (IN )

(Note 5)

–ꢀ.5

ꢀ.5

V

–

+

–

– V

Input Differential Voltage Range

Analog Input Current

V

= V – V

–2.5 • V

2.5 • V

REFꢂUF

V

IN

REFꢂUF

I

–7.8

ꢁ.8

mA

pF

IN

C

Analog Input Capacitance

Analog Input Resistance

5

IN

R

2.ꢀ83

66

kΩ

dꢂ

IN

CMRR

Input Common Mode Rejection Ratio

f

= 25ꢀkHz

IN

converTer characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature rangeV otherwise specifications are at T_A= .5°C6 ꢂIote 2x

LY(SOꢀ

PARA(ETER

COIDꢁTꢁOIL

(ꢁI

18

TYP

(AX

UIꢁTL

ꢂits

l

Resolution

No Missing Codes

18

ꢂits

Transition Noise

1.6

1

LSꢂ

RMS

l

INL

Integral Linearity Error

Differential Linearity Error

ꢂipolar Zero-Scale Error

ꢂipolar Zero-Scale Error Drift

ꢂipolar Full-Scale Error

(Note 6)

(Note 7)

–5

–1

5

LSꢂ

DNL

ꢂZE

ꢀ.1

ꢀ

1.25

3ꢀ

LSꢂ

–3ꢀ

ꢀ.ꢀ1

LSꢂ/°C

LSꢂ

l

FSE

V

= ꢁ.ꢀ96V (REFꢂUF Overdriven)

–125

–15ꢀ

125

15ꢀ

REFꢂUF

(Notes 7, 9)

REFIN = 2.ꢀꢁ8V (Note 7)

LSꢂ

ꢂipolar Full-Scale Error Drift

ꢀ.5

ppm/°C

The l denotes the specifications which apply over the full operating temperature rangeV

DynaMic accuracy

otherwise specifications are at T_A= .5°C and A_ꢁI= –1dSFL6 ꢂIotes 2V 8x

LY(SOꢀ PARA(ETER COIDꢁTꢁOIL

6.25V Range, f = 2kHz, REFIN = 1.25V

(ꢁI

87.6

91

TYP

91

(AX

UIꢁTL

dꢂ

l

SINAD

Signal-to-(Noise + Distortion) Ratio

IN

1ꢀ.2ꢁV Range, f = 2kHz, REFIN = 2.ꢀꢁ8V

95

dꢂ

IN

12.5V Range, f = 2kHz, REFꢂUF = 5V

92

96.5

91.5

95

dꢂ

IN

SNR

Signal-to-Noise Ratio

6.25V Range, f = 2kHz, REFIN = 1.25V

88

dꢂ

IN

1ꢀ.2ꢁV Range, f = 2kHz, REFIN = 2.ꢀꢁ8V

92

dꢂ

IN

12.5V Range, f = 2kHz, REFꢂUF = 5V

9ꢁ

97

dꢂ

IN

THD

Total Harmonic Distortion

Spurious Free Dynamic Range

6.25V Range, f = 2kHz, REFIN = 1.25V

–1ꢀ8

–111

–1ꢀ6

11ꢀ

113

1ꢀ8

7

–98

–96

dꢂ

IN

1ꢀ.2ꢁV Range, f = 2kHz, REFIN = 2.ꢀꢁ8V

dꢂ

IN

12.5V Range, f = 2kHz, REFꢂUF = 5V

dꢂ

IN

SFDR

6.25V Range, f = 2kHz, REFIN = 1.25V

98

96

dꢂ

IN

1ꢀ.2ꢁV Range, f = 2kHz, REFIN = 2.ꢀꢁ8V

dꢂ

IN

12.5V Range, f = 2kHz, REFꢂUF = 5V

dꢂ

IN

–3dꢂ Input Linear ꢂandwidth

Aperture Delay

MHz

ps

5ꢀꢀ

232718fb

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For more information www.linear.com/LTC2327-18

LTC2327-18

DynaMic accuracy ^Thel denotes the specifications which apply over the full operating temperature rangeV

otherwise specifications are at T_A= .5°C and A_ꢁI= –1dSFL6 ꢂIotes 2V 8x

LY(SOꢀ PARA(ETER

COIDꢁTꢁOIL

(ꢁI

TYP

ꢁ

(AX

UIꢁTL

Aperture Jitter

ps

RMS

Transient Response

Full-Scale Step

ꢀ.5

µs

inTernal reFerence characTerisTics ^Thel denotes the specifications which apply over the

full operating temperature rangeV otherwise specifications are at T_A= .5°C6 ꢂIote 2x

LY(SOꢀ

PARA(ETER

COIDꢁTꢁOIL

(ꢁI

TYP

2.ꢀꢁ8

2

(AX

2.ꢀ53

2ꢀ

UIꢁTL

V

Internal Reference Output Voltage

2.ꢀꢁ3

REFIN

l

V

REFIN

Temperature Coefficient

(Note 1ꢁ)

ppm/°C

kΩ

REFIN Output Impedance

Line Regulation

15

V

REFIN

V

= ꢁ.75V to 5.25V

DD

ꢀ.ꢀ8

mV/V

V

REFIN Input Voltage Range

(REFIN Overdriven) (Note 5)

1.25

2.ꢁ

reFerence buFFer characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature rangeV otherwise specifications are at T_A= .5°C6 ꢂIote 2x

LY(SOꢀ PARA(ETER

COIDꢁTꢁOIL

= 2.ꢀꢁ8V

(ꢁI

ꢁ.ꢀ91

2.5

TYP

(AX

ꢁ.1ꢀ1

5

UIꢁTL

l

V

Reference ꢂuffer Output Voltage

REFꢂUF Input Voltage Range

REFꢂUF Output Impedance

REFꢂUF Load Current

V

ꢁ.ꢀ96

V

REFꢂUF

REFIN

(REFꢂUF Overdriven) (Notes 5, 9)

V

= ꢀV

13

kΩ

REFIN

l

I

V

= 5V (REFꢂUF Overdriven) (Notes 9, 1ꢀ)

= 5V, Nap Mode (REFꢂUF Overdriven) (Note 9)

ꢀ.6ꢁ

ꢀ.39

ꢀ.7

mA

REFꢂUF

DigiTal inpuTs anD DigiTal ouTpuTs ^Thel denotes the specifications which apply over the

full operating temperature rangeV otherwise specifications are at T_A= .5°C6 ꢂIote 2x

LY(SOꢀ

PARA(ETER

COIDꢁTꢁOIL

(ꢁI

TYP

(AX

UIꢁTL

V

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

ꢀ.8 • OV

IH

IL

DD

ꢀ.2 • OV

V

DD

I

V

IN

= ꢀV to OV

DD

–1ꢀ

1ꢀ

μA

pF

IN

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

IN

l

I = –5ꢀꢀµA

O

OV – ꢀ.2

DD

V

OH

OL

I = 5ꢀꢀµA

O

ꢀ.2

1ꢀ

V

I

V

OUT

V

OUT

V

OUT

= ꢀV to OV

DD

–1ꢀ

µA

mA

OZ

= ꢀV

= OV

–1ꢀ

1ꢀ

SOURCE

SINK

DD

232718fb

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LTC2327-18

power requireMenTs ^Thel denotes the specifications which apply over the full operating temperature

rangeV otherwise specifications are at T_A= .5°C6 ꢂIote 2x

LY(SOꢀ

PARA(ETER

COIDꢁTꢁOIL

(ꢁI

ꢁ.75

1.71

TYP

(AX

5.25

1ꢁ

UIꢁTL

l

V

Supply Voltage

Supply Current

5

V

DD

OV

DD

+

–

I

5ꢀꢀksps Sample Rate (IN = –1ꢀ.2ꢁV, IN = ꢀV)

11.ꢁ

7.2

ꢀ.1

8.ꢁ

6ꢀ

mA

μA

VDD

–

5ꢀꢀksps Sample Rate (IN = IN = ꢀV)

5ꢀꢀksps Sample Rate (C = 2ꢀpF)

I

Supply Current

Nap Mode Current

Sleep Mode Current

OVDD

NAP

SLEEP

L

+

–

l

Conversion Done (I

Sleep Mode (I

+ I

OVDD

, IN = –1ꢀ.2ꢁV, IN = ꢀV)

1ꢀ

225

VDD

+ I )

OVDD

VDD

+

–

l

P

Power Dissipation

5ꢀꢀksps Sample Rate (IN = –1ꢀ.2ꢁV, IN = ꢀV)

57

36

ꢁ2

ꢀ.3

7ꢀ

mW

D

–

5ꢀꢀksps Sample Rate (IN = IN = ꢀV)

+

–

l

Nap Mode

Sleep Mode

Conversion Done (I

+ I

OVDD

, IN = –1ꢀ.2ꢁV, IN = ꢀV)

5ꢀ

1.1

VDD

+ I

OVDD

Sleep Mode (I

)

VDD

aDc TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature rangeV otherwise specifications are at T_A= .5°C6 ꢂIote 2x

LY(SOꢀ

PARA(ETER

COIDꢁTꢁOIL

(ꢁI

TYP

(AX

5ꢀꢀ

1.5

UIꢁTL

ksps

µs

l

f

t

Maximum Sampling Frequency

Conversion Time

SMPL

CONV

ACQ

1

Acquisition Time

t

= t

CYC

– t (Note 11)

HOLD

1.ꢁ6ꢀ

µs

ACQ

Maximum Time between Acquisitions

Time ꢂetween Conversions

CNV High Time

5ꢁꢀ

13

ns

HOLD

CYC

2

µs

2ꢀ

ns

CNVH

ꢂUSYLH

CNVL

CNV↑ to ꢂUSY Delay

Minimum Low Time for CNV

SCK Quiet Time from CNV↑

SCK Period

C = 2ꢀpF

L

ns

(Note 12)

(Note 11)

2ꢀ

1ꢀ

ꢁ

ns

QUIET

SCK

(Notes 12, 13)

ns

SCK High Time

ns

SCKH

SCKL

SCK Low Time

ꢁ

ns

SDI Setup Time From SCK↑

SDI Hold Time From SCK↑

SCK Period in Chain Mode

SDO Data Valid Delay from SCK↑

(Note 12)

ꢁ

ns

SSDISCK

HSDISCK

SCKCH

DSDO

1

ns

t

= t

+ t (Note 12)

DSDO

13.5

ns

SCKCH

SSDISCK

l

C = 2ꢀpF, OV = 5.25V

7.5

8

9.5

ns

L

DD

C = 2ꢀpF, OV = 2.5V

L

C = 2ꢀpF, OV = 1.71V

L

l

t

SDO Data Remains Valid Delay from SCK↑

SDO Data Valid Delay from ꢂUSY↓

ꢂus Enable Time After RDL↓

C = 2ꢀpF (Note 11)

1

ns

HSDO

DSDOꢂUSYL

EN

L

C = 2ꢀpF (Note 11)

L

5

(Note 12)

16

13

ns

ꢂus Relinquish Time After RDL↑

REFꢂUF Wakeup Time

ns

DIS

C

= ꢁ7μF, C = 1ꢀꢀnF

REFIN

2ꢀꢀ

ms

WAKE

REFꢂUF

232718fb

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LTC2327-18

elecTrical characTerisTics

Iote 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Iote 8: All specifications in dꢂ are referred to a full-scale 1ꢀ.2ꢁV input

with REFIN = 2.ꢀꢁ8V.

Iote 9: When REFꢂUF is overdriven, the internal reference buffer must be

turned off by setting REFIN = ꢀV.

Iote .: All voltage values are with respect to ground.

Iote 10: f

= 5ꢀꢀkHz, I

varies proportionally with sample rate.

SMPL

REFꢂUF

Iote 3: When these pin voltages are taken below ground or above V or

DD

Iote 11: Guaranteed by design, not subject to test.

Iote 1.: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V

OV , they will be clamped by internal diodes. This product can handle

DD

input currents up to 1ꢀꢀmA below ground or above V or OV without

DD

and OV = 5.25V.

DD

latch-up.

Iote 13: t

of 1ꢀns maximum allows a shift clock frequency up to

SCK

Iote 2: V = 5V, OV = 2.5V, 1ꢀ.2ꢁV Range, REFIN = 2.ꢀꢁ8V,

DD

1ꢀꢀMHz for rising edge capture.

Iote 12: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

f

= 5ꢀꢀkHz.

SMPL

Iote 5: Recommended operating conditions.

Iote ±: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Iote 7: ꢂipolar zero error is the offset voltage measured from –ꢀ.5LSꢂ

when the output code flickers between ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ and 11

1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS

or +FS untrimmed deviation from ideal first and last code transitions and

includes the effect of offset error.

0.8 • OV

DD

t

WIDTH

0.2 • OV

DD

50%

t

DELAY

232718 F01

0.8 • OV

0.2 • OV

DD

0.2 • OV

Figure 16 ꢄoltage ꢀevels for Timing Lpecifications

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LTC2327-18

T_A= .5°CV ꢄ_DD= 5ꢄV Oꢄ_DD= .65ꢄV REFꢁI = .6028ꢄV

Typical perForMance characTerisTics

f_L(Pꢀ= 500kspsV unless otherwise noted6

ꢁntegral Ionlinearity

vs Output Code

Differential Ionlinearity

vs Output Code

DC Histogram

3.0

2.5

3000

0.5

0.4

σ = 1.6

2.0

2500

2000

1500

1000

500

0.3

1.5

0.2

1.0

0.1

0.5

0

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–0.1

–0.2

–0.3

–0.4

–0.5

0

–6 –5 –4 –3 –2 –1 0

1 2 3 4 5 6 7

–131072 –65536

0

65536

131072

–131072 –65536

0

65536

131072

OUTPUT CODE

CODE

232718 G01

232718 G02

233718 G03

3.k Point FFT f_L= 500kspsV

f_ꢁI= .kHz

THDV Harmonics

vs ꢁnput Frequency

LIRV LꢁIAD vs ꢁnput Frequency

–70

–80

0

–20

100

90

SNR = 95.3dB

SNR

THD = –113dB

SINAD = 95.2dB

SFDR = –116dB

–40

–90

–60

SINAD

–100

–110

–120

–130

–140

–80

80

–100

–120

–140

–160

–180

70

THD

2ND

3RD

60

0

25 50 75 100 125 150 175 200

0

25 50 75 100 125 150 175 200

FREQUENCY (kHz)

0

50

100

150

200

250

FREQUENCY (kHz)

232718 G06

232718 G04

232718 G05

LIRV LꢁIAD vs ꢁnput ꢀevelV

f_ꢁI= .kHz

LIRV LꢁIAD vs TemperatureV

f_ꢁI= .kHz

THDV Harmonics vs TemperatureV

f_ꢁI= .kHz

96.0

95.5

95.0

94.5

–105

–110

–115

–120

–125

98

97

THD

3RD

2ND

96

SNR

95

94

SINAD

93

92

–40

–30

–20

–10

0

5

20 35 50 65

80 95 110

125

–40 –25 –10

5

20 35 50 65

80 95 110

125

–40 –25 –10

TEMPERATURE (°C)

INPUT LEVEL (dB)

TEMPERATURE (°C)

232718 G09

232718 G07

232718 G08

232718fb

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LTC2327-18

T_A= .5°CV ꢄ_DD= 5ꢄV Oꢄ_DD= .65ꢄV REFꢁI = .6028ꢄV

Typical perForMance characTerisTics

f_L(Pꢀ= 500kspsV unless otherwise noted6

ꢁIꢀ/DIꢀ vs Temperature

Full-Lcale Error vs Temperature

Offset Error vs Temperature

2.0

1.5

20

15

5

4

3

1.0

10

2

MAX INL

0.5

5

1

MAX DNL

MIN DNL

MIN INL

0

–1

–2

–3

–4

–5

–0.5

–1.0

–1.5

–2.0

–5

–10

–15

–20

5

20 35 50 65

80 95 110

125

–40 –25 –10

5

20 35 50 65

80 95 110

125

–40

–25 –10

5

20

TEMPERATURE (°C)

35 50

65

80 95 110 125

–40 –25 –10

TEMPERATURE (°C)

232718 G10

232718 G11

232718 G12

ꢁnternal Reference Output vs

Temperature

Lupply Current vs Temperature

Lleep Current vs Temperature

8

7

6

5

4

3

2

1

0

120

100

80

60

40

20

0

2.0484

2.0483

2.0482

2.0481

2.0480

2.0479

2.0478

2.0477

2.0476

V

DD

+

–

IN = IN = 0V

OV

DD

5

20 35 50 65

TEMPERATURE (°C)

80 95 110

125

–40

–25 –10

5

20

35 50

65

80 95 110 125

–40

–25 –10

5

35 50

20 65

80 95 110 125

TEMPERATURE (°C)

–40 –25 –10

TEMPERATURE (°C)

232718 G15

232718 G13

232718 G14

ꢁnternal Reference Output

Temperature Coefficient

Distribution

C(RR vs ꢁnput Frequency

Lupply Current vs Lampling Rate

80

75

12

10

35

30

+

V

(IN = –10.24V)

DD

25

70

65

8

6

20

15

10

5

+

V

(IN = 0V)

DD

+

60

55

50

4

2

0

V

(IN = 10.24V)

DD

OV

DD

0

50

100

150

200

250

0

100

200

300

400

500

–10

–4

0

2

4

6

10

8

–8 –6

–2

FREQUENCY (kHz)

SAMPLING FREQUENCY (kHz)

DRIFT (ppm/°C)

232718 G17

232718 G18

232718 G16

232718fb

8

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LTC2327-18

pin FuncTions

ꢄ

ꢂPin 1x: 2.5V Supply ꢂypass Pin. The voltage

CHAꢁI ꢂPin 10x: Chain Mode Selector Pin. When low,

the LTC2327-18 operates in normal mode and the

RDL/SDI input pin functions to enable or disable SDO.

Whenhigh,theLTC2327-18operatesinchainmodeandthe

RDL/SDI pin functions as SDI, the daisy-chain serial data

DDꢀSYP

on this pin is generated via an onboard regulator off of

DD

V . This pin must be bypassed with a 2.2μF ceramic

capacitor to GND.

ꢄ

ꢂPin.x:5VPowerSupply.TherangeofV isꢁ.75Vto

DD

input. Logic levels are determined by OV .

DD

5.25V. ꢂypass V to GND with a 1ꢀµF ceramic capacitor.

DD

SULY ꢂPin 11x: ꢂUSY Indicator. Goes high at the start of

GID ꢂPins 3V ± and 1±x: Ground.

a new conversion and returns low when the conversion

+

–

ꢁI ꢂPin 2x: Analog Input. IN operates differential with

has finished. Logic levels are determined by OV .

DD

–

+

respect to IN with an IN -IN range of –2.5 • V

to

REFꢂUF

RDꢀ/LDꢁ ꢂPin 1.x: When CHAIN is low, the part is in nor-

mal mode and the pin is treated as a bus enabling input.

When CHAIN is high, the part is in chain mode and the

pin is treated as a serial data input pin where data from

another ADC in the daisy chain is input. Logic levels are

2.5 • V

.

REFꢂUF

–

ꢁI ꢂPin 5x: Analog Ground Sense. IN has an input range

of 5ꢀꢀmV with respect to GND and must be tied to the

ground plane or a remote sense.

determined by OV .

DD

REFSUF ꢂPin 7x: Reference ꢂuffer Output. An onboard

buffer nominally outputs ꢁ.ꢀ96V to this pin. This pin is

referredtoGNDandshouldbedecoupledcloselytothepin

with a ꢁ7μF ceramic capacitor. The internal buffer driving

this pin may be disabled by grounding its input at REFIN.

Once the buffer is disabled, an external reference may

overdrive this pin in the range of 2.5V to 5V. A resistive

load greater than 5ꢀꢀkΩ can be placed on the reference

buffer output.

LCKꢂPin13x:SerialDataClockInput.WhenSDOisenabled,

the conversion result or daisy-chain data from another

ADC is shifted out on the rising edges of this clock MSꢂ

first. Logic levels are determined by OV .

DD

LDOꢂPin12x:SerialDataOutput. Theconversionresultor

daisy-chain data is output on this pin on each rising edge

of SCK MSꢂ first. The output data is in 2’s complement

format. Logic levels are determined by OV .

DD

REFꢁI ꢂPin 8x: Reference Output/Reference ꢂuffer Input.

An onboard bandgap reference nominally outputs 2.ꢀꢁ8V

at this pin. ꢂypass this pin with a 1ꢀꢀnF ceramic capacitor

to GND to limit the reference output noise. If more accu-

racy is desired, this pin may be overdriven by an external

reference in the range of 1.25V to 2.ꢁV.

Oꢄ ꢂPin 15x: I/O Interface Digital Power. The range of

DD

OV is 1.71V to 5.25V. This supply is nominally set to

DD

the same supply as the host interface (1.8V, 2.5V, 3.3V,

or 5V). ꢂypass OV to GND with a ꢀ.1μF capacitor.

DD

CIꢄ ꢂPin 9x: Convert Input. A rising edge on this input

powers up the part and initiates a new conversion. Logic

levels are determined by OV .

DD

232718fb

9

For more information www.linear.com/LTC2327-18

LTC2327-18

FuncTional block DiagraM

REFIN = 1.25V REFBUF = 2.5V

OV = 1.8V

DD

TO 5V

V

= 5V

V

= 2.5V

DDLBYP

TO 2.4V

TO 5V

DD

LDO

15k

2.048V

REFERENCE

2× REFERENCE

BUFFER

R

0.63× BUFFER

4R

CHAIN

SDO

RDL/SDI

SCK

+

–

IN

+

SPI

PORT

R

18-BIT SAMPLING ADC

4R

–

CNV

BUSY

CONTROL LOGIC

GND

232718 BD01

TiMing DiagraM

Conversion Timing Using the Lerial ꢁnterface

CHAIN, RDL/SDI = 0

CNV

CONVERT

NAP

BUSY

SCK

HOLD

ACQUIRE

D17 D16 D15 D2 D1 D0

SDO

232718 TD01

232718fb

10

For more information www.linear.com/LTC2327-18

LTC2327-18

applicaTions inForMaTion

OꢄERꢄꢁEꢅ

TRAILFER FUICTꢁOI

The LTC2327-18 is a low noise, high speed 18-bit suc-

cessive approximation register (SAR) ADC with pseudo-

differential inputs. Operating from a single 5V supply,

the LTC2327-18 has a 1ꢀ.2ꢁV true bipolar input range,

making it ideal for high voltage applications which require

a wide dynamic range. The LTC2327-18 achieves 5LSꢂ

INLmaximum,nomissingcodesat18-bitsand95dꢂSNR.

The LTC2327-18 digitizes the full-scale voltage of 2.5 •

18

REFꢂUF into 2 levels, resulting in an LSꢂ size of 78µV

withREFꢂUF=ꢁ.ꢀ96V.Theidealtransferfunctionisshown

in Figure 2. The output data is in 2’s complement format.

AIAꢀOG ꢁIPUT

TheanaloginputsoftheLTC2327-18arepseudo-differen-

tialinordertoreduceanyunwantedsignalthatiscommon

to both inputs. The analog inputs can be modeled by the

equivalent circuit shown in Figure 3. The back-to-back

diodes at the inputs form clamps that provide ESD protec-

tion. Each input drives a resistor divider network that has

The LTC2327-18 has an onboard single-shot capable

reference buffer and low drift (2ꢀppm/°C max) 2.ꢀꢁ8V

temperature-compensated reference. The LTC2327-18

also has a high speed SPI-compatible serial interface that

supports1.8V,2.5V,3.3Vand5Vlogicwhilealsofeaturing

a daisy-chain mode. The fast 5ꢀꢀksps throughput with

no cycle latency makes the LTC2327-18 ideally suited

for a wide variety of high speed applications. An internal

oscillator sets the conversion time, easing external timing

considerations. The LTC2327-18 dissipates only 36mW

and automatically naps between conversions, leading to

reduced power dissipation that scales with the sampling

rate. A sleep mode is also provided to reduce the power

consumption of the LTC2327-18 to 3ꢀꢀμW for further

power savings during inactive periods.

011...111

BIPOLAR

ZERO

011...110

000...001

000...000

111...111

111...110

100...001

100...000

FSR = +FS – –FS

1LSB = FSR/262144

–1 0V

LSB

1

LSB

–FSR/2

FSR/2 – 1LSB

COIꢄERTER OPERATꢁOI

INPUT VOLTAGE (V)

232718 F02

The LTC2327-18 operates in two phases. During the ac-

quisition phase, the charge redistribution capacitor D/A

converter (CDAC) is connected to the outputs of the resis-

tor divider networks that pins IN and IN drive to sample

an attenuated and level-shifted version of the pseudo-

differential analog input voltage as shown in Figure 3. A

rising edge on the CNV pin initiates a conversion. During

the conversion phase, the 18-bit CDAC is sequenced

throughasuccessiveapproximationalgorithm,effectively

comparing the sampled input with binary-weighted frac-

Figure .6 ꢀTC.3.7-18 Transfer Function

0.63 • V

+

–

REFBUF

C

45pF

IN

R

50Ω

400Ω

ON

1.6k

+

–

IN

0.63 • V

BIAS

VOLTAGE

REFBUF

C

45pF

IN

R

50Ω

400Ω

ON

1.6k

232718 F03

IN

tions of the reference voltage (e.g. V

/2, V

/ꢁ

REFꢂUF

… V

/2621ꢁꢁ) using the differential comparator. At

REFꢂUF

the end of conversion, the CDAC output approximates the

sampledanaloginput.TheADCcontrollogicthenprepares

the 18-bit digital output code for serial transfer.

Figure 36 The Equivalent Circuit for the Differential

Analog ꢁnput of the ꢀTC.3.7-18

232718fb

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LTC2327-18

applicaTions inForMaTion

a total impedance of 2kΩ. The resistor divider network

attenuates and level shifts the 2.5 • REFꢂUF true bipolar

signal swing of each input to the ꢀ-REFꢂUF input signal

50Ω

66nF

+

–

+

–

LT±468

IN

±±0ꢀ.4ꢁ

LTC.3.7-±8

swingoftheADCcore.Intheacquisitionphase,ꢁ5pF(C )

BW = 48kHz

IN

fromthesamplingCDACinserieswithapproximately5ꢀΩ

.3.7±8 F04

(R ) from the on-resistance of the sampling switch is

ON

connected to the output of the resistor divider network.

Any unwanted signal that is common to both inputs will

be reduced by the common mode rejection of the ADC

Figure 26 ꢁnput Lignal Chain

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

+

core and resistor divider network. The IN input of the

ADC core draws a current spike while charging the C

capacitor during acquisition.

IN

ꢁIPUT DRꢁꢄE CꢁRCUꢁTL

A low impedance source can directly drive the high im-

pedance input of the LTC2327-18 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

is important even for DC inputs, because the ADC input

draws a current spike when entering acquisition.

Pseudo-Differential Sipolar ꢁnputs

For most applications, we recommend the low power

LT1ꢁ68 ADC driver to drive the LTC2327-18. With a low

noisedensityof5nV/√Hzandalowsupplycurrentof3mA,

the LT1ꢁ68 is flexible and may be configured to convert

signals of various amplitudes to the 1ꢀ.2ꢁV input range

of the LTC2327-18.

For best performance, a buffer amplifier should be used

to drive the analog input of the LTC2327-18. The amplifier

provides low output impedance to minimize gain error

and allows for fast settling of the analog signal during

the acquisition phase. It also provides isolation between

the signal source and the ADC input which draws a small

current spike during acquisition.

To achieve the full distortion performance of the

LTC2327-18, a low distortion single-ended signal source

driven through the LT1ꢁ68 configured as a unity-gain

buffer as shown in Figure ꢁ can be used to get the full

data sheet THD specification of –111dꢂ.

ꢁnput Filtering

ADC REFEREICE

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Noisy input signals should be filtered prior

to the buffer amplifier input with a low bandwidth filter to

minimizenoise.Thesimple1-poleRClowpassfiltershown

in Figure ꢁ is sufficient for many applications.

There are three ways of providing the ADC reference. The

first is to use both the internal reference and reference

buffer. The second is to externally overdrive the internal

reference and use the internal reference buffer. The third

is to disable the internal reference buffer and overdrive

the REFꢂUF pin from an external source. The following

tables give examples of these cases and the resulting

bipolar input ranges.

The input resistor divider network, sampling switch on-

resistance (R ) and the sample capacitor (C ) form a

ON

IN

second lowpass filter that limits the input bandwidth to

the ADC core to 7MHz. A buffer amplifier with a low noise

density must be selected to minimize the degradation of

the SNR over this bandwidth.

232718fb

12

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LTC2327-18

applicaTions inForMaTion

Table 16 ꢁnternal Reference with ꢁnternal Suffer

Eꢃternal Reference with ꢁnternal Suffer

REFꢁI

REFSUF

SꢁPOꢀAR ꢁIPUT RAIGE

If more accuracy and/or lower drift is desired, REFIN

can be easily overdriven by an external reference since

a 15k resistor is in series with the reference as shown

in Figure 5b. REFIN can be overdriven in the range from

1.25V to 2.ꢁV. The resulting voltage at REFꢂUF will be

2 • REFIN. So the input range is 5 • REFIN, as shown

in Table 2. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

manyapplications.Withitssmallsize,lowpower,andhigh

accuracy, the LTC6655-2.ꢀꢁ8 is well suited for use with

the LTC2327-18 when overdriving the internal reference.

The LTC6655-2.ꢀꢁ8 offers ꢀ.ꢀ25% (max) initial accuracy

and 2ppm/°C (max) temperature coefficient for high pre-

cision applications. The LTC6655-2.ꢀꢁ8 is fully specified

over the H-grade temperature range and complements

the extended temperature range of the LTC2327-18 up to

125°C.ꢂypassingtheLTC6655-2.ꢀꢁ8witha2.7μFto1ꢀꢀµF

ceramiccapacitorclosetotheREFINpinisrecommended.

2.ꢀꢁ8V

ꢁ.ꢀ96V

1ꢀ.2ꢁV

Table .6 Eꢃternal Reference with ꢁnternal Suffer

REFꢁI

ꢂOꢄERDRꢁꢄEx

REFSUF

SꢁPOꢀAR ꢁIPUT RAIGE

1.25V (Min)

2.ꢀꢁ8V

2.5V

ꢁ.ꢀ96V

ꢁ.8V

6.25V

1ꢀ.2ꢁV

12V

2.ꢁV (Max)

Table 36 Eꢃternal Reference Unbuffered

REFꢁI

REFSUF

ꢂOꢄERDRꢁꢄEx

SꢁPOꢀAR ꢁIPUT RAIGE

ꢀV

2.5V (Min)

5V (Max)

6.25V

12.5V

ꢁnternal Reference with ꢁnternal Suffer

The LTC2327-18 has an on-chip, low noise, low drift

(2ꢀppm/°C max), temperature compensated bandgap

reference that is factory trimmed to 2.ꢀꢁ8V. It is internally

connected to a reference buffer as shown in Figure 5a and

is available at REFIN (Pin 8). REFIN should be bypassed to

GNDwitha1ꢀꢀnFceramiccapacitortominimizenoise.The

reference buffer gains the REFIN voltage by 2 to ꢁ.ꢀ96V at

REFꢂUF (Pin 7). So the input range is 1ꢀ.2ꢁV, as shown

in Table 1. ꢂypass REFꢂUF to GND with at least a ꢁ7μF

ceramic capacitor (X7R, 1ꢀV, 121ꢀ size) to compensate

the reference buffer and minimize noise.

Eꢃternal Reference Unbuffered

The internal reference buffer can also be overdriven from

2.5V to 5V with an external reference at REFꢂUF as shown

in Figure 5c. So the input ranges are 6.25V to 12.5V,

respectively, as shown in Table 3. To do so, REFIN must

be grounded to disable the reference buffer. A 13k resis-

tor loads the REFꢂUF pin when the reference buffer is

disabled. To maximize the input signal swing and cor-

responding SNR, the LTC6655-5 is recommended when

overdrivingREFꢂUF.TheLTC6655-5offersthesamesmall

size, accuracy, drift and extended temperature range as

the LTC6655-2.ꢀꢁ8. ꢂy using this 5V reference, an SNR

of 97dꢂ can be achieved. ꢂypassing the LTC6655-5 with

a ꢁ7μF ceramic capacitor (X5R, ꢀ8ꢀ5 size) close to the

REFꢂUF pin is recommended.

15k

REFIN

BANDGAP

REFERENCE

100nF

REFBUF

REFERENCE

BUFFER

6.5k

TheREFꢂUFpinoftheLTC2327-18drawsacharge(Q

)

CONV

47µF

fromtheexternalbypasscapacitorduringeachconversion

cycle. If the internal reference buffer is overdriven, the

external reference must provide all of this charge with a

6.5k

LTC2327-18

GND

232718 F05a

DC current equivalent to I

= Q

/t . Thus, the

REFꢂUF

CONV CYC

Figure 5a6 ꢀTC.3.7-18 ꢁnternal Reference Circuit

DC current draw of REFꢂUF depends on the sampling

232718fb

13

For more information www.linear.com/LTC2327-18

LTC2327-18

applicaTions inForMaTion

of the output code. If an external reference is used to

overdrive REFꢂUF, the fast settling LTC6655-5 reference

is recommended.

15k

REFIN

BANDGAP

REFERENCE

2.7µF

REFBUF

REFERENCE

BUFFER

ꢁnternal Reference Suffer Transient Response

47µF

LTC6655-2.048

6.5k

Foroptimumtransientperformance,theinternalreference

buffer should be used. The internal reference buffer uses a

proprietarydesignthatresultsinanoutputvoltagechange

atREFꢂUFoflessthan1LSꢂwhenrespondingtoasudden

burst of conversions. This makes the internal reference

bufferoftheLTC2327-18trulysingle-shotcapablesincethe

first sample taken after idling will yield the same result as

a sample taken after the transient response of the internal

reference buffer has settled. Figure 7 shows the transient

responses of the LTC2327-18 with the internal reference

buffer and with the internal reference buffer overdriven by

the LTC6655-5, both with a bypass capacitance of ꢁ7μF.

6.5k

LTC2327-18

GND

232718 F05b

Figure 5b6 Using the ꢀTC±±55-.6028 as an Eꢃternal Reference

15k

REFIN

BANDGAP

REFERENCE

REFBUF

REFERENCE

BUFFER

6.5k

47µF

LTC6655-5

6.5k

2

LTC2327-18

INTERNAL REFERENCE BUFFER

GND

232718 F05c

0

Figure 5c6 Overdriving REFSUF Using the ꢀTC±±55-5

–2

EXTERNAL SOURCE ON REFBUF

–4

rate and output code. In applications where a burst of

samples is taken after idling for long periods, as shown in

–6

–8

Figure 6, I

quickly goes from approximately 39ꢀµA

REFꢂUF

to a maximum of ꢀ.7mA for REFꢂUF = 5V at 5ꢀꢀksps. This

step in DC current draw triggers a transient response in

the external reference that must be considered since any

deviation in the voltage at REFꢂUF will affect the accuracy

0

100 200 300 400 500 600 700 800 9001000

TIME (µs)

232718 F07

Figure 76 Transient Response of the ꢀTC.3.7-18

CNV

232718 F06

IDLE

PERIOD

IDLE

PERIOD

Figure ±6 CIꢄ ꢅaveform Lhowing Surst Lampling

232718fb

14

For more information www.linear.com/LTC2327-18

LTC2327-18

applicaTions inForMaTion

DYIA(ꢁC PERFOR(AICE

Total Harmonic Distortion ꢂTHDx

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. ꢂy applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2327-18 provides

guaranteed tested limits for both AC distortion and noise

measurements.

TotalHarmonicDistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

2

V2²+V3²+Vꢁ²+…+V_N

THD=2ꢀlog

V1

where V1 is the RMS amplitude of the fundamental

Lignal-to-Ioise and Distortion Ratio ꢂLꢁIADx

frequency and V2 through V are the amplitudes of the

N

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 8 shows that the LTC2327-18 achieves

a typical SINAD of 95dꢂ at a 5ꢀꢀkHz sampling rate with

a 2kHz input.

second through Nth harmonics.

POꢅER COILꢁDERATꢁOIL

The LTC2327-18 provides two power supply pins: the 5V

power supply (V ), and the digital input/output interface

DD

power supply (OV ). The flexible OV supply allows

DD

the LTC2327-18 to communicate with any digital logic

operating between 1.8V and 5V, including 2.5V and 3.3V

systems.

Lignal-to-Ioise Ratio ꢂLIRx

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 8 shows

that the LTC2327-18 achieves a typical SNR of 95dꢂ at a

5ꢀꢀkHz sampling rate with a 2kHz input.

Power Lupply Lequencing

The LTC2327-18 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2327-18

has a power-on reset (POR) circuit that will reset the

LTC2327-18 at initial power-up or whenever the power

supply voltage drops below 2V. Once the supply voltage

reenters the nominal supply voltage range, the POR will

re-initialize the ADC. No conversions should be initiated

until 2ꢀꢀμs after a POR event to ensure the re-initialization

period has ended. Any conversions initiated before this

time will produce invalid results.

0

SNR = 95.3dB

–20

–40

THD = –113dB

SINAD = 95.2dB

SFDR = –116dB

–60

–80

–100

–120

–140

–160

–180

Tꢁ(ꢁIG AID COITROꢀ

CIꢄ Timing

0

50

100

150

200

250

FREQUENCY (kHz)

232718 F08

The LTC2327-18 conversion is controlled by CNV. A ris-

ing edge on CNV will start a conversion and power up

the LTC2327-18. Once a conversion has been initiated,

Figure 86 3.k Point FFT of the ꢀTC.3.7-18

232718fb

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LTC2327-18

applicaTions inForMaTion

it cannot be restarted until the conversion is complete.

For optimum performance, CNV should be driven by a

clean low jitter signal. Converter status is indicated by the

ꢂUSY output which remains high while the conversion is

in progress. To ensure that no errors occur in the digitized

results, any additional transitions on CNV should occur

within ꢁꢀns from the start of the conversion or after the

conversion has been completed. Once the conversion has

completed, the LTC2327-18 powers down.

12

10

+

V

(IN = –10.24V)

DD

8

6

+

V

(IN = 0V)

DD

+

4

2

0

V

(IN = 10.24V)

DD

OV

DD

Acquisition

0

100

200

300

400

500

SAMPLING FREQUENCY (kHz)

AproprietarysamplingarchitectureallowstheLTC2327-18

to begin acquiring the input signal for the next conver-

sion 527ns after the start of the current conversion. This

extends the acquisition time to 1.ꢁ6ꢀµs, easing settling

requirementsandallowingtheuseofextremelylowpower

ADC drivers. (Refer to the Timing Diagram.)

232718 F09

Figure 96 Power Lupply Current of the ꢀTC.3.7-18

ꢄersus Lampling Rate

twice with no intervening rising edge on SCK. The part

will enter sleep mode on the falling edge of ꢂUSY from

the last conversion initiated. Once in sleep mode, a rising

edge on SCK will wake the part up. Upon emerging from

ꢁnternal Conversion Clock

sleep mode, wait t

ms before initiating a conversion

The LTC2327-18 has an internal clock that is trimmed to

achieve a maximum conversion time of 1.5µs.

WAKE

to allow the reference and reference buffer to wake up

and charge the bypass capacitors at REFIN and REFꢂUF.

(Refer to the Timing Diagrams section for more detailed

timing information about sleep mode.)

Auto Iap (ode

The LTC2327-18 automatically enters nap mode after a

conversion has been completed and completely powers

up once a new conversion is initiated on the rising edge of

CNV. During nap mode, only the ADC core powers down

and all other circuits remain active. During nap, data from

thelastconversioncanbeclockedout. Theautonapmode

featurewillreducethepowerdissipationoftheLTC2327-18

as the sampling frequency is reduced. Since full power is

consumed only during a conversion, the ADC core of the

LTC2327-18remainspowereddownforalargerfractionof

DꢁGꢁTAꢀ ꢁITERFACE

The LTC2327-18 has a serial digital interface. The flexible

OV supplyallowstheLTC2327-18tocommunicatewith

DD

any digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

The serial output data is clocked out on the SDO pin when

anexternalclockisappliedtotheSCKpinifSDOisenabled.

Clocking out the data after the conversion will yield the

best performance. With a shift clock frequency of at least

ꢁꢀMHz, a 5ꢀꢀksps throughput is still achieved. The serial

output data changes state on the rising edge of SCK and

can be captured on the falling edge or next rising edge of

SCK. D17 remains valid till the first rising edge of SCK.

the conversion cycle (t ) at lower sample rates, thereby

CYC

reducing the average power dissipation which scales with

the sampling rate as shown in Figure 9.

Lleep (ode

Theautonapmodefeatureprovideslimitedpowersavings

since only the ADC core powers down. To obtain greater

power savings, the LTC2327-18 provides a sleep mode.

During sleep mode, the entire part is powered down

except for a small standby current resulting in a power

dissipation of 3ꢀꢀμW. To enter sleep mode, toggle CNV

The serial interface on the LTC2327-18 is simple and

straightforwardtouse.Thefollowingsectionsdescribethe

operationoftheLTC2327-18. Severalmodesareprovided

depending on whether a single or multiple ADCs share the

SPI bus or are daisy-chained.

232718fb

16

For more information www.linear.com/LTC2327-18

LTC2327-18

applicaTions inForMaTion

Iormal (odeV Lingle Device

shows a single LTC2327-18 operated in normal mode

with CHAIN and RDL/SDI tied to ground. With RDL/SDI

grounded, SDO is enabled and the MSꢂ(D17) of the new

conversion data is available at the falling edge of ꢂUSY.

This is the simplest way to operate the LTC2327-18.

When CHAIN = ꢀ, the LTC2327-18 operates in normal

mode. In normal mode, RDL/SDI enables or disables the

serial data output pin SDO. If RDL/SDI is high, SDO is in

highimpedance.IfRDL/SDIislow,SDOisdriven.Figure1ꢀ

CONVERT

DIGITAL HOST

CNV

CHAIN

BUSY

IRQ

LTC2327-18

RDL/SDI

SCK

SDO

DATA IN

CLK

NAP

CONVERT

NAP

CONVERT

ACQUIRE

CHAIN = 0

RDL/SDI = 0

t

CYC

t

CNVH

t

CNVL

CNV

t

HOLD

ACQ

t

= t

– t

ACQ CYC HOLD

t

CONV

BUSY

t

SCK

t

BUSYLH

t

QUIET

SCKH

1

2

3

16

17

18

SCK

SDO

t

SCKL

HSDO

t

DSDO

DSDOBUSYL

D17

D16

D15

D1

D0

232718 F12

Figure 106 Using a Lingle ꢀTC.3.7-18 in Iormal (ode

232718fb

17

For more information www.linear.com/LTC2327-18

LTC2327-18

applicaTions inForMaTion

Iormal (odeV (ultiple Devices

be used to allow only one LTC2327-18 to drive SDO at a

timeinordertoavoidbusconflicts. AsshowninFigure11,

the RDL/SDI inputs idle high and are individually brought

low to read data out of each device between conversions.

When RDL/SDI is brought low, the MSꢂ of the selected

device is output onto SDO.

Figure 11 shows multiple LTC2327-18 devices operating

in normal mode (CHAIN = ꢀ) sharing CNV, SCK and SDO.

ꢂy sharing CNV, SCK and SDO, the number of required

signals to operate multiple ADCs in parallel is reduced.

Since SDO is shared, the RDL/SDI input of each ADC must

RDL

B

A

CONVERT

CNV

CHAIN

BUSY

SDO

IRQ

CHAIN

LTC2327-18

B

LTC2327-18

A

DIGITAL HOST

SDO

RDL/SDI

SCK

DATA IN

CLK

NAP

CONVERT

NAP

CONVERT

ACQUIRE

CHAIN = 0

t

CNVL

CNV

t

HOLD

BUSY

t

CONV

t

BUSYLH

RDL/SDI

A

B

RDL/SDI

t

SCK

t

QUIET

SCKH

SCK

SDO

1

2

3

16

17

18

19

20

21

34

35

36

t

SCKL

HSDO

t

DIS

DSDO

t

EN

Hi-Z

D17

D16

D15

D1

A

D0

A

D17

D16

D15

D1

B

D0

B

A

B

232718 F11

Figure 116 Iormal (ode with (ultiple Devices Lharing CIꢄV LCKV and LDO

232718fb

18

For more information www.linear.com/LTC2327-18

LTC2327-18

applicaTions inForMaTion

Chain (odeV (ultiple Devices

may limit the numberoflines needed to interface toa large

number of converters. Figure 12 shows an example with

two daisy-chained devices. The MSꢂ of converter A will

appear at SDO of converter ꢂ after 18 SCK cycles. The

MSꢂ of converter A is clocked in at the SDI/RDL pin of

converter ꢂ on the rising edge of the first SCK.

When CHAIN = OV , the LTC2327-18 operates in

DD

chain mode. In chain mode, SDO is always enabled and

RDL/SDI serves as the serial data input pin (SDI) where

daisy-chain data output from another ADC can be input.

This is useful for applications where hardware constraints

CONVERT

OV

DD

CNV

CHAIN

DIGITAL HOST

LTC2327-18

RDL/SDI

SDO

RDL/SDI

BUSY

SDO

IRQ

A

B

DATA IN

SCK

CLK

NAP

ACQUIRE

CONVERT

NAP

ACQUIRE

CONVERT

CHAIN = OV

DD

RDL/SDI = 0

A

t

CYC

t

CNVL

CNV

t

HOLD

BUSY

t

CONV

t

BUSYLH

SCK

t

SCKCH

t

QUIET

SCKH

1

2

3

16

17

18

19

20

34

35

36

t

SCKL

t

HSDO

SSDISCK

t

DSDO

HSDISCK

SDO = RDL/SDI

A

B

D17

D16

D15

D1

D0

A

t

DSDOBUSYL

D17

D16

D15

D1

B

D17

D16

D1

A

D0

A

SDO

B

A

B

232718 F12

Figure 1.6 Chain (ode Timing Diagram

232718fb

19

For more information www.linear.com/LTC2327-18

LTC2327-18

applicaTions inForMaTion

Lleep (ode

the last conversion initiated. Once in sleep mode, a rising

edge on SCK will wake the part up. Upon emerging from

To enter sleep mode, toggle CNV twice with no interven-

ing rising edge on SCK as shown in Figure 13. The part

will enter sleep mode on the falling edge of ꢂUSY from

sleep mode, wait t

ms before initiating a conversion

WAKE

to allow the reference and reference buffer to wake up

and charge the bypass capacitors at REFIN and REFꢂUF.

NAP AND

ACQUIRE

CHAIN = DON’T CARE

RDL/SDI = DON’T CARE

CONVERT

t

CONVERT

SLEEP

CONVERT

NAP

ACQUIRE

t

WAKE

CNVH

CNV

t

ACQ

HOLD

BUSY

t

CONV

t

BUSYLH

SCK

NAP AND

ACQUIRE

CHAIN = DON’T CARE

RDL/SDI = DON’T CARE

CONVERT

SLEEP

CONVERT

t

WAKE

CNVH

CNV

t

CONV

BUSY

t

BUSYLH

SCK

232718 F13

Figure 136 Lleep (ode Timing Diagram

232718fb

20

For more information www.linear.com/LTC2327-18

LTC2327-18

boarD layouT

To obtain the best performance from the LTC2327-18 a

printed circuit board (PCꢂ) is recommended. Layout for

PCꢂ should ensure the digital and analog signal lines are

separated as much as possible. In particular, care should

be taken not to run any digital clocks or signals alongside

analog signals or underneath the ADC.

Recommended ꢀayout

ThefollowingisanexampleofarecommendedPCꢂlayout.

A single solid ground plane is used. ꢂypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC19ꢀ8, the

evaluation kit for the LTC2327-18.

Partial Top Lilkscreen

Partial ꢀayer 1 Component Lide

232718fb

21

For more information www.linear.com/LTC2327-18

LTC2327-18

boarD layouT

Partial ꢀayer . Ground Plane

Partial ꢀayer 3 Power Plane

Partial ꢀayer 2 Sottom ꢀayer

232718fb

22

For more information www.linear.com/LTC2327-18

LTC2327-18

boarD layouT

Partial Lchematic of Demo Soard

232718fb

23

For more information www.linear.com/LTC2327-18

LTC2327-18

package DescripTion

Please refer to http://www6linear6com/product/ꢀTC.3.7-18#packaging for the most recent package drawings6

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev A)

0.889 ±0.127

(.035 ±.005)

5.10

3.20 – 3.45

(.201)

(.126 – .136)

MIN

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

0.50

(.0197)

BSC

0.305 ±0.038

(.0120 ±.0015)

TYP

0.280 ±0.076

(.011 ±.003)

REF

16151413121110

9

RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

DETAIL “A”

0.254

4.90 ±0.152

(.193 ±.006)

(.010)

0° – 6° TYP

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

1 2 3 4 5 6 7 8

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

MSOP (MS16) 0213 REV A

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

232718fb

24

For more information www.linear.com/LTC2327-18

LTC2327-18

revision hisTory

REꢄ

DATE

DELCRꢁPTꢁOI

PAGE IU(SER

A

ꢀ9/1ꢁ Updated minimum SNR/SINAD for 6.25V input range.

ꢀ7/16 Updated graphs Gꢀ1, Gꢀ2 and Gꢀ3

3

7

ꢂ

232718fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

25

For more information www.linear.com/LTC2327-18

LTC2327-18

Typical applicaTion

ꢀT12±8 Configured to Suffer a ±106.2ꢄ Lingle-Ended Lignal ꢁnto the ꢀTC.3.7-18

15V

7

LT1468

5V

+10.24V

–10.24V

3

2

+

–

V

DD

+

–

IN

6

LTC2327-18

REFBUF

47µF

REFIN

4

100nF

232718 TA02

–15V

relaTeD parTs

PART IU(SER

ADCs

DELCRꢁPTꢁOI

CO((EITL

LTC2338-18/LTC2337-18/ 18-ꢂit, 1Msps/5ꢀꢀksps/25ꢀksps Serial,

LTC2336-18 Low Power ADC

5V Supply, 1ꢀ.2ꢁV True ꢂipolar, Differential Input, 1ꢀꢀdꢂ SNR, Pin-Compatible

Family in MSOP-16 Package

LTC2378-2ꢀ/LTC2377-2ꢀ/ 2ꢀ-ꢂit, 1Msps/5ꢀꢀksps/25ꢀksps Serial,

LTC2376-2ꢀ Low Power ADC

2.5V Supply, Differential Input, ꢀ.5ppm INL, 5V Input Range, DGC, Pin-

Compatible Family in MSOP-16 and ꢁmm × 3mm DFN-16 Packages

LTC2379-18/LTC2378-18/ 18-ꢂit, 1.6Msps/1Msps/5ꢀꢀksps/25ꢀksps

LTC2377-18/LTC2376-18 Serial, Low Power ADC

2.5V Supply, Differential Input, 1ꢀ1.2dꢂ SNR, 5V Input Range, DGC,

Pin-Compatible Family in MSOP-16 and ꢁmm × 3mm DFN-16 Packages

LTC238ꢀ-16/LTC2378-16/ 16-ꢂit, 2Msps/1Msps/5ꢀꢀksps/25ꢀksps

LTC2377-16/LTC2376-16 Serial, Low Power ADC

2.5V Supply, Differential Input, 96.2dꢂ SNR, 5V Input Range, DGC,

Pin-Compatible Family in MSOP-16 and ꢁmm × 3mm DFN-16 Packages

LTC2369-18/LTC2368-18/ 18-ꢂit, 1.6Msps/1Msps/5ꢀꢀksps/25ꢀksps

LTC2367-18/LTC236ꢁ-18 Serial, Low Power ADC

2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dꢂ SNR, ꢀV to 5V Input

Range, Pin-Compatible Family in MSOP-16 and ꢁmm × 3mm DFN-16 Packages

LTC237ꢀ-16/LTC2368-16/ 16-ꢂit, 2Msps/1Msps/5ꢀꢀksps/25ꢀksps

LTC2367-16/LTC236ꢁ-16 Serial, Low Power ADC

2.5V Supply, Pseudo-Differential Unipolar Input, 9ꢁdꢂ SNR, ꢀV to 5V Input

Range, Pin-Compatible Family in MSOP-16 and ꢁmm × 3mm DFN-16 Packages

LTC2389-18/LTC2389-16 18-ꢂit/16-ꢂit, 2.5Msps Parallel/Serial ADC

5V Supply, Pin-Configurable Input Range, 99.8dꢂ/96dꢂ SNR, Parallel or Serial

I/O 7mm × 7mm LQFP-ꢁ8 and QFN-ꢁ8 Packages

LTC16ꢀ9

16-ꢂit, 2ꢀꢀksps Serial ADC

1ꢀV, Configurable Unipolar/ꢂipolar Input, Single 5V Supply, SSOP-28 and

SO-2ꢀ Packages

DACs

LTC2756/LTC2757

18-ꢂit, Single Serial/Parallel I

DAC

SoftSpan™ 1LSꢂ INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm LQFP-ꢁ8

OUT

Package

LTC26ꢁ1

LTC263ꢀ

References

LTC6655

16-ꢂit/1ꢁ-ꢂit/12-ꢂit Single Serial V

DAC

1LSꢂ INL /DNL, MSOP-8 Package, ꢀV to 5V Output

OUT

12-ꢂit/1ꢀ-ꢂit/8-ꢂit Single V

DACs

1LSꢂ INL (12 ꢂits), Internal Reference, SC7ꢀ 6-Pin Package

OUT

Precision Low Drift Low Noise ꢂuffered

Reference

5V/2.5V/2.ꢀꢁ8V/1.2V, 2ppm/°C, ꢀ.25ppm Peak-to-Peak Noise, MSOP-8 Package

5V/2.5V/2.ꢀꢁ8V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package

LTC6652

Precision Low Drift Low Noise ꢂuffered

Reference

Amplifiers

LT1ꢁ68/LT1ꢁ69

Single/Dual 9ꢀMHz, 22V/μs, 16-ꢂit Accurate Low Input Offset: 75μV/125µV

Op Amp

232718fb

LT 0716 REV B • PRINTED IN USA

LinearTechnology Corporation

163ꢀ McCarthy ꢂlvd., Milpitas, CA 95ꢀ35-7ꢁ17

26

For more information www.linear.com/LTC2327-18

(ꢁꢀ8)ꢁ32-19ꢀꢀ FAX: (ꢁꢀ8) ꢁ3ꢁ-ꢀ5ꢀ7 www.linear.com/LTC2327-18

●

 LINEAR TECHNOLOGY CORPORATION 2014


型号：	LTC2327HMS-18#PBF
厂家：	Linear
描述：	LTC2327-18 - 18-Bit, 500ksps, ±10.24V True Bipolar, Pseudo-Differential Input ADC with 95dB SNR; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C 光电二极管转换器
文件：	总26页 (文件大小：497K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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