X9460 [INTERSIL]
Dual Audio Control Digitally Controlled Potentiometer; 双音频控制数字电位器
| 型号： | X9460 |
| 厂家： | 
Intersil |
| 描述： | Dual Audio Control Digitally Controlled Potentiometer |
| 文件： | 总16页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9460
®
Low Noise, Low Cost, High End Features, Dual Audio Log Potentiometer
Data Sheet
October 17, 2005
FN8203.2
Dual Audio Control Digitally Controlled
Potentiometer (XDCP™)
Features
• Dual Audio Control – Two 32 Taps Log Pots
The X9460 integrates two digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit. The two
XDCPs can be used as stereo gain controls in audio
applications. Read/Write operations can directly access
each channel independently or both channels
simultaneously. Increment/Decrement can adjust each
channel independently or both channels simultaneously.
• Zero Amplitude Wiper Switching
• 2-Wire Serial Interface
4 Slave Byte Addresses for Writes[A1,A0]
• Total Resistance: 33kΩ Each XDCP (Typical)
• Dual Voltage Operation
V+/V- = ±2.7 to ±5.5V
The X9460 contains a zero amplitude wiper switching circuit
that delays wiper changes until the next zero crossing of the
audio signal.
• Temp Range = -40°C to +85°C
• Package Options
14 L d TSSOP
The digitally controlled potentiometer is implemented using
31 polysilicon resistors in a log array. Between each of the
resistors are tap points connected to the wiper terminal
through switches. The XDCPs are designed to minimize
wiper noise to avoid pops and clicks during audio volume
transitions. The position of the wiper on the array is
• Zero Amplitude Wiper Switching
• Pb-Free Plus Anneal Available (RoHS Compliant)
Audio Performance
• 0 to - 62dB Volume Control
controlled by the user through the 2-wire serial bus interface.
• -92dB Mute
Power-up reset the wiper to the mute position.
- Power-Up to Mute Position
• SNR -96dB
Pinout
• THD+N: -95dB @1kHz
X9460
(14 LD TSSOP)
TOP VIEW
• Crosstalk Rejection: -102dB @ 1kHz
• Channel-to-Channel Variation: ± 0.1dB
• 3dB-Cutoff: 100kHz
SDA
SCL
14
13
12
11
10
1
2
3
4
5
6
7
V-
R
H-right
V
CC
R
R
L-right
X9460
Applications
• Set Top Boxes
V+
W-right
V
SS
R
R
R
H-left
L-left
A0
A1
9
8
• Stereo Amplifiers
• DVD Players
W-left
• Portable Audio Products
Ordering Information
PART NUMBER
PART MARKING
X9460KV I
X9460KV Z I
VCC LIMITS (V)
TEMP RANGE (°C)
-40 to +85
PACKAGE
14 Ld TSSOP
X9460KV14I*
5V ± 10%
X9460KV14IZ* (Note)
X9460KV14I-2.7*
-40 to +85
14 Ld TSSOP (Pb-free)
14 Ld TSSOP
X9460KV G
2.7 to 5.5
-40 to +85
X9460KV14IZ-2.7* (Note)
X9460KV Z G
-40 to +85
14 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9460
Simplified Functional Diagram
R
R
H-Left
H-Right
V
V+
CC
62dB total
Power-on
Recall
# OF
mute
STEP SIZE
-1dB
STEPS
data
select
inc/dec
address
11
10
5
BUS
POT
Left
2
POT
Right
I C
INTERFACE
CONTROL &
REGISTER
-2dB
bus
-3dB
-4dB
4
Mute
1
V
R
R
R
R
L-Right
V-
SS
W-Left
L-Left
W-Right
Detailed Functional Diagram
V
V+
CC
Power-on
Recall
R
H-Left
WIPER
mute
COUNTER
REGISTER
(WCR)
SCL
R
L-Left
INTERFACE
AND
CONTROL
CIRCUITRY
SDA
A0
POT Left
R
W-Left
8
R
A1
W-Right
DATA
R
H-Right
WIPER
COUNTER
REGISTER
(WCR)
R
L-Right
POT Right
V
V-
SS
FN8203.2
October 17, 2005
2
X9460
Typical Application
Audio
Amplifier
Left
Audio
DAC
X9460
2 XDCP
Gain / Volume Control
Left Channel Control
Right Channel Control
Audio => R
R
Simultaneous Left and Right Channel
Control
HL, HR
R
, R
=> Amplifier
WR
WL
Audio
Amplifier
Right
Power-up in Mute
µController
Serial Bus
EEPROM
Pin Assignments
PIN
(TSSOP)
SYMBOL
SDA
SCL
FUNCTION
1
2
Serial Data
Serial Clock
3
VCC
System Supply Voltage
Positive Analog Supply
System Ground
4
V+
5
VSS
6
A0
Device Address
7
A1
Device Address
8
RW-left
RL-left
RH-left
RW-right
RL-right
RH-right
V-
Wiper terminal of the Left Potentiometer
Negative terminal of the Left Potentiometer
Positive terminal of the Left Potentiometer
Wiper terminal of the Right Potentiometer
Negative terminal of the Right Potentiometer
Positive terminal of the Right Potentiometer
Negative Analog Supply
9
10
11
12
13
14
FN8203.2
3
October 17, 2005
X9460
The VSS pin is always connected to the system common or
ground. VH, VL, VW are the voltages on the RH, RL, and RW
potentiometer pins.
Detailed Pin Description
Host Interface Pins
SERIAL CLOCK (SCL)
The SCL input clocks data into and out of the X9460.
X9460 Principles of Operation
The X9460 is a highly integrated microcircuit incorporating
two resistor arrays with their associated registers, counters
and the serial interface logic providing direct communication
between the host and the DCP potentiometers. This section
provides detailed description as following:
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-
ORed with any number of open drain or open collector
outputs. An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the guidelines
for calculating typical values on the bus pull-up resistors
graph.
- Resistor Array Description
- Serial Interface Description
- Command Set and Register Information Description
DEVICE ADDRESS (A1 - A0)
Resistor Array Description
The Address inputs are used to set the least significant 2 bits
of the 8-bit Slave Byte Address. A match in the slave
address serial data stream must be made with the Address
input in order to initiate communication with the X9460. Up to
4 X9460s may be connected to a single I2C serial bus and
written to (NOTE: you cannot read from more than one
device on the same 2-wire bus). If left floating, these pins are
internally pulled to ground.
The X9460 is comprised of two resistor arrays. Each array
contains 31 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (RH and
RL inputs). Tables 1 and 2 provide a description of the step
size and tap positions.
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (RW)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The five bits of the WCR are
decoded to select, and enable, one of thirty-two switches.
Slave Byte (bits, MSB-LSB) = 0101 0 A1 A0 R/W
Potentiometer Pins
RH-LEFT, RL-LEFT, RH-RIGHT, RL-RIGHT
The RH and RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
TABLE 1. TOTAL -62dB RANGE PLUS MUTE POSITION
STEP SIZE
# OF STEPS
R
W-LEFT, RW-RIGHT
-1dB
- 2dB
- 3dB
- 4dB
Mute
11 steps
10 steps
5 steps
4 steps
1 step
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Supply Pins
ANALOG SUPPLY V- AND V+
The positive power supply for the DCP analog control
section is connected to V+. The negative power supply for
the DCP analog control section is connected to V-.
TABLE 2. WIPER TAP POSITION vs dB
TAP POSITION, n
dB
MIN/MAX dB
DIGITAL SUPPLIES VCC, VSS
The power supplies for the digital control sections.
for n = 20 to 31
for n = 10 to 19
for n = 5 to 9
for n = 1 to 4
n = 0
n - 31
2n-51
3n-61
4n-66
-92
-11/0
-31/-13
-46/-34
-62/-50
-92
Power-up and Down Recommendations
There are no restrictions on the power-up condition of VCC
V+ and V- and the voltages applied to the potentiometer pins
provided that the VCC and V+ are more positive or equal to
the voltage at RH, RL, and RW, ie. VCC, V+ > RH, RL, RW. At
all times, the voltages on the potentiometer pins must be
less than V+ and more than V-.
,
The following VCC ramp rate spec is always in effect.
0.2 V/ms < VCC ramp < 50 V/ms
FN8203.2
October 17, 2005
4
X9460
Stop Condition
Serial Interface Description
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Serial Interface
The X9460 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. The X9460 is a slave device in all
applications.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions.
The X9460 will respond with an acknowledge: 1) after
recognition of a start condition and after an identification and
slave address byte, and 2) again after each successful
receipt of the instruction or databyte. See Figure 1.
Start Condition
All commands to the X9460 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9460 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met.
Invalid Commands
For any invalid commands or unrecognizable addresses, the
X9460 will NOT acknowledge and return the X9460 to the
idle state.
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
FIGURE 1. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN8203.2
5
October 17, 2005
X9460
Several instructions require a three-byte sequence to
complete. These instructions transfer data between the host
and the X9460. These instructions are: Read Wiper Counter
Register, Write Wiper Counter Register. The sequence of
operations is shown in Figure 4 and 5. The four-byte
command is used for write command for both right and left
pots (Figure 6).
Command Set and Register Description
Device Addressing
Following a start condition the master must output the Slave
Byte Address of the slave it is accessing. The most
significant four bits of the slave address are the device type
identifier (refer to Figure 2). For the X9460 this is fixed as
0101.
Special Commands
DEVICE TYPE
IDENTIFIER
Increment/Decrement Instruction. The Increment/Decrement
command is different from the other commands. Once the
command is issued and the X9460 has responded with an
acknowledge, the master can clock the selected wiper up
and/or down. For each SCL clock pulse (tHIGH) while SDA is
HIGH, the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock pulse
while SDA is LOW, the selected wiper will move one resistor
segment towards the RL terminal. A detailed illustration of
the sequence and timing for this operation are shown in
Figures 7 and 8 respectively.
0
1
0
1
0
A1
A0
R/W
DEVICE ADDRESS
FIGURE 2. SLAVE BYTE ADDRESS
The next three bits of the Slave Byte Address are the device
address. The device address is defined by the A1 - A0 inputs.
The X9460 compares the serial data stream with the Slave
Byte Address; a successful compare is required for the
X9460 to respond with an acknowledge. The A1 - A0 inputs
can be actively driven by CMOS input signals or tied to VCC
or VSS. The R/W bit sets the device for read or write
operations. Note that the X9460 supports reads and writes to
a single device on the 2-wire bus. If more than one X9460 is
used on the same 2-wire bus, those devices must have
unique device addresses and only writes are supported. You
may not read from multiple devices or contention will result
and the data is not valid.
Wiper Counter Register
The X9460 contains two Wiper Counter Registers. The
Wiper Counter Register output is decoded to select one of
thirty-two switches along its resistor array. The Write Wiper
Counter Register command directly sets the WCR to a
value. The Increment/Decrement instruction steps the
register value up or down one to multiple times.
The WCR is a volatile register (Table 3) and is reset to the
mute position (tap 0, “zero”) at power-up.
TABLE 3. WIPER COUNTER REGISTERS, 5-bit - VOLATILE:
WCR4
WCR3
WCR2
WCR1
WCR0
Command Set
(MSB)
(LSB)
After a Slave Byte Address match, the next byte sent
contains the Command and register pointer information. The
four most significant bits are the Command. The next bit is a
“X” (don’t care) set to zero.
The X9460 contains one 5-bit Wiper Counter Register for
each DCP. (Two 5-bit registers in total.)
this bit not used, set to 0
I3
I2
I1
I0
0
Z
RT
LT
D
WIPER COUNTER
SELECT
INSTRUCTIONS
FIGURE 3. COMMAND BYTE FORMAT
The ZD bit enables and disables the Zero Amplitude Wiper
Switching circuit. When ZD=1, the wiper switches will turn on
when close-to-zero amplitude is detected across the
potentiometer pins. When ZD=0, this circuit is disabled. The
last two bits, LT (left POT enable) and RT (right POT
enable), select which of the two potentiometers is affected
by the instruction.
FN8203.2
October 17, 2005
6
X9460
TABLE 4. COMMAND SET
INSTRUCTION SET
INSTRUCTION
Read Wiper
I3
I2
I1
I0
X
ZD
RT
LT
OPERATION
LSB of Slave Byte=1, no command required
Slave will return Left then Right Data( not to be used with more
than one device on the 2-wire bus)
Write Left Wiper Counter
Write Right Wiper Counter
Write Both Wiper Counters
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1/0
1/0
1/0
0
1
1
1
0
1
Write new value to the Wiper Counter Register
Write new value to the Wiper Counter Register
Write new value to the Wiper Counter Register
Inc/Dec Left Wiper Counter
Inc/Dec Right Wiper Counter
Inc/Dec Both Wiper Counters
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1/0
1/0
1/0
0
1
1
1
0
1
Enable Increment/decrement of the Control Latch
Enable Increment/decrement of the Control Latch
Enable Increment/decrement of the Control Latch
Notes: “1/0” = data is one or zero
SCL
SDA
1
0
0
0
0
0
0
0
0
A
C
K
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
W
W
C
R
3
W
W
C
R
1
W
C
R
0
S
T
0
1
0
1
0
A1 A0 R/W A
C
0
0
0
0
A
C
K
S
T
O
P
C
R
4
C
R
2
A
K
R
T
DEVICE TYPE
IDENTIFIER
LEFT POT
DATA BYTE
RIGHT POT
DATA BYTE
FIGURE 4. THREE-BYTE COMMAND SEQUENCE (READ, SINGLE DEVICE ON THE 2-WIRE BUS ONLY)
SCL
SDA
0
0
0
0
0
0
0
1
0
1
0
0
0
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
0
1
0
1
0
A1 A0 R/W A I3 I2
I1 I0
ZD RT LT
A
C
K
A
C
K
S
T
O
P
C
K
A
R
T
DEVICE TYPE
IDENTIFIER
RIGHT or LEFT POT
DATA BYTE
INSTRUCTION BYTE
FIGURE 5. THREE-BYTE COMMAND SEQUENCE (WRITE)
FN8203.2
October 17, 2005
7
X9460
SCL
SDA
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
W W
W
C
R
2
W
C
R
1
W
C
R
0
W W
W
C
R
2
W
C
R
1
W
C
R
0
C
R
4
C
R
3
S
T
A
R
0
1
0
1
0
A1 A0 R/W A I3 I2 I1 I0
ZD RT LT
A
C
K
C
R
4
C
R
3
0
A
C
K
A
C
K
S
T
O
P
C
K
DEVICE TYPE
IDENTIFIER
LEFT POT
RIGHT POT
DATA BYTE
T
INSTRUCTION BYTE
DATA BYTE
FIGURE 6. FOUR-BYTE COMMAND SEQUENCE (WRITE)
SCL
SDA
0
0
0
0
0
1
0
S
0
1
0
1
0
A1 A0 R/W
A
I3
I2
I1 I0
ZD
RT LT
A
C
K
I
N
C
I
D
E
C
S
T
O
I
D
T
A
C
K
N
C
2
N
C
n
E
C
n
R
T
1
1
P
DEVICE TYPE
IDENTIFIER
INSTRUCTION BYTE
INC and DEC ACTIVE
FIGURE 7. INCREMENT/DECREMENT COMMAND SEQUENCE (WRITE)
INC/DEC
CMD
ISSUED
t
WRID
SCL
SD A
VOLTAGE OUT
R
W
Wiper can move within 10µs after the falling edge of SCL
FIGURE 8. INCREMENT/DECREMENT TIMING LIMITS
FN8203.2
October 17, 2005
8
X9460
Instruction Formats
Read Wiper Counter Register (Single device on 2-wire bus only)
device type
identifier
device
addresses
Left wiper position
(sent by slave on SDA)
Right wiper position
(sent by slave on SDA)
S
T
A
R
T
S
A
C
K
M
A
C
K
M S
A T
C O
K P
L
L
L
L
L
R R R R R
0 0 0 D D D D D
A A
0
1
0
1
0
0
0
0 D D D D D
1
0
4
3
2
1
0
4 3 2 1 0
Write Wiper Counter Register
Left or Right wiper
position
(sent by master on SDA)
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
S
T
A
R
T
S
A
C
K
S
S S
A T
C O
K P
A
C
K
A A
Z R L
D D D D D
4 3 2 1 0
0
1
0
1
0
1
0
1
0
0
0 0 0
1
0
D T
T
Write Both Wiper Counter Registers
Left wiper position
(sent by master on
SDA)
Right wiper position
(sent by master on
SDA)
device type
identifier
device
addresses
instruction
opcode addresses
wiper
S
T
A
R
T
S
A
C
K
S
S
S S
A T
C O
K P
A
C
K
A
C
K
L L L L L
0 0 0 D D D D D
4 3 2 1 0
R R R R R
0 0 0 D D D D D
4 3 2 1 0
A A
1 0
Z
0 1 0 1 0
1 0 1 0 0
1 1
D
Increment/Decrement Wiper Counter Register
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
increment/decrement
(sent by master on SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
0
A1 A0
0
0
1
0
0 ZD RT LT
I/D I/D
.
.
.
.
I/D I/D
Definitions:
1. “MACK”/“SACK”: stands for the acknowledge sent by the master/slave.
2. “A1 ~ A0”: stands for the device addresses sent by the master.
3. “I”: stands for the increment operation, SDA held high during active SCL phase (high).
4. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
FN8203.2
October 17, 2005
9
X9460
Absolute Maximum Ratings
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SDA, SCL or any Address Input
Recommended Operating Conditions
Temperature Range (Industrial). . . . . . . . . . . . . . . . . .-40°C to 85°C
X9460V14-2.7
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
V- Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-5.5V to -2.7V
V+ Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7V to +5.5V
with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6V
Voltage on V+ (referenced to VSS). . . . . . . . . . . . . . . . . . . . . . . .+6V
Voltage on V- (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . -6V
(V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Any RH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+
Any RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C
I
W max (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Analog Specifications Over the recommended operating conditions unless otherwise specified (Note 1)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE (Notes 2, 3)
Control Range
-62
0
dB
dB
dB
dB
Mute Mode
@1V rms
-92
-96
-95
SNR
Signal Noise Ratios (Unweighted)
Total Harmonic Distortion + Noise
@1V rms @ 1kHz, Tap = -6dB
@1V rms @ 1kHz, Tap = -6dB
THD + N
XTalk
DCP Isolation
@1kHz, tap = -6dB
tap = -6dB
-102
-105
dB
dB
Digital Feedthrough
(Peak Component)
-3db Cutoff Frequency
100
kHz
DC ACCURACY
Step Size
Steps of -1, -2, -3, -4 dB
For -1dB steps
-1
-4
dB
dB
dB
dB
dB
dB
Step Size Error
Step Size Error
Step Size Error
Step Size Error
DCP to DCP Matching
-0.2
-0.4
-0.6
-0.8
-0.1
+0.2
+0.4
+0.6
+0.8
0.1
For -2dB steps
For -3dB steps
For -4dB steps
NOTES:
1. VCC = | V- |
V
CC Ramp up timing 0.2V/ms < Vcc Ramp Rate < 50V/ms
2. This parameter is guaranteed by design and characterization
3. TA = 25oC, VCC = 5.0V; 2 Hz to 20kHz Measurement Bandwidth with 80kHz filter, input signal 1Vrms, 1kHz Sine Wave.
Analog Specifications Over the recommended operating conditions unless otherwise specified (Note 1)
ANALOG INPUTS
SYMBOL
VTERM
PARAMETER
Voltage on RL, RW, and RH pins
End to End Resistance
TEST CONDITIONS
MIN
V-
TYP
MAX
V+
UNIT
V
%
RTOTAL
Typical 33kΩ
-20
+20
Cin (Note 4) Input Capacitance RL, RH, RW
W (NOte 2) Wiper Current
TA = 25oC
25
pF
mA
Ω
I
-3
+3
RW
V-
Wiper Resistance
Voltage on V- pin
Wiper Current = ±3mA
100
200
-2.7
-5.5
V
FN8203.2
October 17, 2005
10
X9460
Analog Specifications Over the recommended operating conditions unless otherwise specified (Note 1) (Continued)
ANALOG INPUTS
SYMBOL
PARAMETER
Voltage on V+ pin
Noise
TCR (Note 2) Temperature Coefficient of resistance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V+
+2.7
+5.5
20Hz to 20kHz, Grounded Input @ -6dB tap
2
µVrms
PPM/°C
-300
DC Electrical Specifications Over the recommended operating conditions unless otherwise specified. (Note 1)
LIMITS
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
ICC1
VCC Supply Current (Move Wiper, fSCL = 400kHz, SDA = Open,
200
300
µA
Write, Read)
Other Inputs = VSS
ISB
ILI
VCC Current (Standby)
Input Leakage Current
Analog Input Leakage
SCL = SDA = VCC, Addr. = VSS
VIN = VSS to VCC
3
1
µA
µA
µA
10
Iai
V
IN = V- to V+ with all other
0.1
analog inputs floating
ILO
VIH
VIL
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output LOW Voltage
VOUT = VSS to VCC
10
µA
V
VCC x 0.7
-0.5
VCC + 0.5
VCC x 0.1
0.4
V
VOL
IOL = 3mA
V
Capacitance
SYMBOL
TEST
TEST CONDITIONS
MAX
UNITS
C
I/O (Note 4)
CIN (NOte 4)
NOTE:
Input/Output Capacitance (SDA)
VI/O = 0V
VIN = 0V
8
6
pF
pF
Input Capacitance (A0, A1, A2 and SCL)
4. This parameter is not 100% tested.
FN8203.2
11
October 17, 2005
X9460
Equivalent A.C. Load Circuit
A.C. Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
10ns
5V
Input Rise and Fall Times
Input and Output Timing Level
1533Ω
VCC x 0.5
SDA OUTPUT
100pF
AC TIMING Over recommended operating conditions
SYMBOL
PARAMETER
MIN
MAX
UNITS
kHz
ns
fSCL
tCYC
Clock Frequency
400
Clock Cycle Time
Clock High Time
2500
600
1300
600
600
600
500
50
tHIGH
ns
tLOW
Clock Low Time
ns
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
tHD:DAT
Start Setup Time
ns
Start Hold Time
ns
Stop Setup Time
ns
SDA Data Input Setup Time
SDA Data Input Hold Time
ns
ns
t
R (Note 2) SCL and SDA Rise Time
300
300
900
ns
tF (Note 2) SCL and SDA Fall Time
ns
t
AA (Note 2) SCL Low to SDA Data Output Valid Time
ns
t
DH (Note 2) SDA Data Output Hold Time
TI (Note 2) Noise Suppression Time Constant at SCL and SDA inputs
BUF (Note 2) Bus Free Time (Prior to Any Transmission)
50
50
ns
ns
t
1300
0
ns
tSU:WPA
tHD:WPA
A0, A1 (Note 2)
A0, A1 (Note 2)
ns
0
ns
DC Timing (Note 2)
SYMBOL
PARAMETER
MIN
MAX
10
UNITS
µs
tWRPO
tWRL
Wiper Response Time After The Third (Last) Power Supply Is Stable
Wiper Response Time After Instruction Issued (All Load Instructions)
Wiper Response Time From An Active SCL Edge (Increment/Decrement Instruction)
10
µs
tWRID
10
µs
FN8203.2
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October 17, 2005
X9460
Timing Diagrams
(START)
(STOP)
t
t
F
R
t
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
R
F
SDA
FIGURE 9. START AND STOP TIMING
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
FIGURE 10. INPUT TIMING
SCL
SDA
t
t
DH
AA
FIGURE 11. OUTPUT TIMING
(STOP)
SCL
SDA
VWx
LSB
t
WRL
FIGURE 12. DCP TIMING (FOR ALL LOAD INSTRUCTIONS)
FN8203.2
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October 17, 2005
X9460
Typical Performance Characteristics
(Vcc, V+ = 5.0V, V- = -5.0V, TA = + 25 °C, unless otherwise noted)
FFT Spectrum
(with 1kHz 1Vrms input, tap = -6dB)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
V
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
H z
FIGURE 13. SINGLE TONE FREQUENCY RESPONSE
THD+N vs Frequency
(with 80kHz low-pass filter, tap = -6dB)
-6 0
-6 5
-7 0
-7 5
-8 0
-8 5
d
B
-9 0
-9 5
-1 00
-1 05
-1 10
-1 15
-1 20
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
FIGURE 14. THD + N
FN8203.2
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October 17, 2005
X9460
Typical Performance Characteristics
(Vcc, V+ = 5.0V, V- = -5.0V, TA = + 25 °C, unless otherwise noted)
Mute Mode
+0
-10
-20
-30
-40
-50
-60
d
B
V
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
Hz
1k
2k
5k
10k
20k
FIGURE 15. MUTE
FN8203.2
October 17, 2005
15
X9460
Packaging Information
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8203.2
16
October 17, 2005
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