X9460KV14I [XICOR]
Digital Potentiometer, 2 Func, 33000ohm, 2-wire Serial Control Interface, 32 Positions, CMOS, PDSO14, PLASTIC, TSSOP-14;
| 型号： | X9460KV14I |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 2 Func, 33000ohm, 2-wire Serial Control Interface, 32 Positions, CMOS, PDSO14, PLASTIC, TSSOP-14 光电二极管 转换器 电阻器 |
| 文件： | 总17页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Typical Applications:
–Set Top Boxes
New Feature
–DVD Players
–Stereo Amplifiers
–Portable Audio Products
Zero Amplitude
Wiper Switching
PRELIMINARY
Low Noise, Low Cost, High End Features,
Dual Audio Log Potentiometer
X9460
Dual Audio Control Digitally Controlled Potentiometer (XDCPTM)
FEATURES
DESCRIPTION
• Dual audio control – Two 32 taps Log pots
• Zero Amplitude Wiper Switching
• 2-wire serial interface
4 cascadable slave byte addresses [A1,A0]
• Total resistance: 33KΩ each XDCP (Typical)
• Dual Voltage Operation
The X9460 integrates two digitally controlled
potentiometer (XDCP) on
a
monolithic CMOS
integrated circuit. The two XDCPs can be used as
stereo gain controls in audio applications. Read/Write
operations can directly access each channel
independently or both channels simultaneously.
Increment/ Decrement can adjust each channel
independently or both channels simultaneously.
V+/V- = 2ꢀ. to ꢁꢀꢁV
• Temp Range = -40oC to +8ꢁ oC
• Package Options
The X9460 contains a zero amplitude wiper switching
circuit that delays wiper changes until the next zero
crossing of the audio signal.
14-Lead TSSOP
AUDIO PERFORMANCE
The digitally controlled potentiometer is implemented
using 31 polysilicon resistors in a log array. Between
each of the resistors are tap points connected to the
wiper terminal through switches. The XDCPs are
designed to minimize wiper noise to avoid pops and
clicks during audio volume transitions. The position of
the wiper on the array is controlled by the user through
the 2-wire serial bus interface.
• 0 to - 62dB volume control
• -92dB Mute
—Power up to mute position
• SNR -96dB
• THD+N: -9ꢁdB @1k HZ
• Crosstalk rejection: -102dB @ 1k HZ
• Channel-to-channel variation: 0ꢀ1dB
• 3dB-cutoff: 100kHz
Power up reset the wiper to the mute position.
SIMPLIFIED
FUNCTIONAL DIAGRAM
R
R
H-Left
H-Right
V
V+
CC
62dB total
Power On
Recall
Step Size # of Steps
mute
-1dB
-2dB
-3dB
-4dB
Mute
11
10
5
data
select
inc / dec
address
BUS
POT
Left
I2C
bus
POT
Right
INTERFACE
CONTROL &
REGISTER
4
1
V
R
R
R
R
L-Right
V-
SS
W-Left
L-Left
W-Right
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X9460
DETAILED FUNCTIONAL DIAGRAM
V
V+
CC
Power On
Recall
R
H-Left
WIPER
COUNTER
REGISTER
(WCR)
mute
SCL
R
R
L-Left
INTERFACE
AND
SDA
A0
POT Left
W-Left
CONTROL
8
CIRCUITRY
R
A1
W-Right
DATA
R
H-Right
WIPER
COUNTER
REGISTER
(WCR)
R
L-Right
POT Right
V
V-
SS
TYPICAL APPLICATION
X9460
2 XDCP
Audio
Amplifier
Left
Audio
DAC
Gain / Volume Control
Left Channel Control
Right Channel Control
Audio => R
R
Simultaneous Left and Right Channel
Control
HL, HR
R
, R
=> Amplifier
WR
WL
Audio
Amplifier
Right
Power up in Muteꢀ
µController
Serial Bus
EEPROM
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X9460
PIN CONFIGURATION
TSSOP
SDA
SCL
14
13
12
11
10
1
2
3
4
5
6
7
V-
R
H-right
V
CC
R
R
L-right
X9460
V+
W-right
V
SS
R
R
R
H-left
L-left
W-left
A1
A0
9
8
PIN ASSIGNMENTS
Pin
(TSSOP)
Symbol
Function
1
2
SDA
SCL
Serial Data
Serial Clock
3
V
System Supply Voltage
Positive Analog Supply
System Ground
CC
4
V+
5
V
SS
6
A1
Device Address
7
A0
Device Address
8
R
Wiper terminal of the Left Potentiometer
Negative terminal of the Left Potentiometer
Positive terminal of the Left Potentiometer
Wiper terminal of the Right Potentiometer
Negative terminal of the Right Potentiometer
Positive terminal of the Right Potentiometer
Negative Analog Supply
W-left
9
R
L-left
H-left
10
11
12
13
14
R
R
W-right
R
L-right
R
H-right
V-
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X9460
DETAILED PIN DESCRIPTION:
Host Interface Pins
Power Up and Down Recommendations
There are no restrictions on the power-up condition of
V
, V+ and V- and the voltages applied to the potenti-
CC
ometer pins provided that the Vcc and V+ are more
positive or equal to the voltage at RH, RL , and Rw, ie.
Vcc, V+ > RH, RL, Rw. At all times, the voltages on the
potentiometer pins must be less than V+ and more
than V-.
SERIAL CLOCK (SCL)
The SCL input clocks data into and out of the X9460.
SERIAL DATA (SDA)
The following V ramp rate spec is always in effect.
CC
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs. An open drain output requires the use of
a pull-up resistor. For selecting typical values, refer to
the guidelines for calculating typical values on the bus
pull-up resistors graph.
0.2 V/ms < V ramp < 50 V/ms
CC
The V
pin is always connected to the system com-
SS
mon or ground. V , V , V are the voltages on the R ,
H
L
W
H
R , and R potentiometer pins.
L
W
X9460 PRINCIPLES OF OPERATION
DEVICE ADDRESS (A - A )
1
0
The X9460 is a highly integrated microcircuit incorpo-
rating two resistor arrays with their associated regis-
ters, counters and the serial interface logic providing
direct communication between the host and the DCP
potentiometers. This section provides detailed descrip-
tion as following:
The Address inputs are used to set the least significant
2 bits of the 8-bit Slave Byte Address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9460. Up to 4 X9460s may be directly con-
nected to a single I2C serial bus. If left floating, these
pins are internally pulled to ground.
– Resistor Array Description
– Serial Interface Description
– Command Set and Register Information Description
Slave Byte (bits, MSB-LSB) = 0101 0 A A R/W
1
0
RESISTOR ARRAY DESCRIPTION
Potentiometer Pins
H-LEFT, RL-LEFT, RH-RIGHT, R
The X9460 is comprised of two resistor arrays. Each
array contains 31 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
R
L-RIGHT
The R and R inputs are equivalent to the terminal
H
L
connections on either end of a mechanical potentio-
meter.
potentiometer (R and R inputs). Tables 1 and 2 pro-
H
L
vide a description of the step size and tap positions.
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
R
W-LEFT, R
W-RIGHT
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
(R ) output. Within each individual array only one
W
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
five bits of the WCR are decoded to select, and enable,
one of thirty-two switches.
Supply Pins
ANALOG SUPPLY V- AND V+
Table 1ꢀ Total -62dB range Plus Mute Position
The positive power supply for the DCP analog control
section is connected to V+. The negative power supply
for the DCP analog control section is connected to V-.
Step Size
-1 dB
# of Steps
11 steps
10 steps
5 steps
- 2 dB
- 3 dB
- 4 dB
Mute
Digital Supplies V , V
CC SS
The power supplies for the digital control sections.
4 steps
1 step
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X9460
Table 2ꢀ Wiper Tap Position vs dBꢀ
Start Condition
All commands to the X9460 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9460 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is met.
Tap Position, n
for n = 20 to 31
for n = 10 to 19
for n = 5 to 9
for n = 1 to 4
n = 0
dB
Min/Max dB
-11 / 0
n - 31
2n-51
3n-61
4n-66
-92
-31 / -13
-46 / -34
-62 / -50
-92
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
SERIAL INTERFACE DESCRIPTION
Serial Interface
The X9460 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
The X9460 is a slave device in all applications.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and dur-
ing this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop condi-
tions.
The X9460 will respond with an acknowledge: 1) after
recognition of a start condition and after an identifica-
tion and slave address byte, and 2) again after each
successful receipt of the instruction or databyte. See
Figure 1.
Invalid Commands
For any invalid commands or unrecognizable
addresses, the X9460 will NOT acknowledge and
return the X9460 to the idle state.
Figure 1ꢀ Acknowledge Response from Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
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X9460
COMMAND SET AND REGISTER DESCRIPTION
DEVICE ADDRESSING
this circuit is disabled. The last two bits, LT (left POT
enable) and RT (right POT enable), select which of the
two potentiometers is affected by the instruction.
Following a start condition the master must output the
Slave Byte Address of the slave it is accessing. The
most significant four bits of the slave address are the
device type identifier (refer to Figure 2 below). For the
X9460 this is fixed as 0101.
Several instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9460. These instructions are: Read
Wiper Counter Register, Write Wiper Counter Register.
The sequence of operations is shown in Figure 4 and
5. The four-byte command is used for write command
for both right and left pots (Figure 6).
Figure 2ꢀ Slave Byte Address
Special Commands
DEVICE TYPE
IDENTIFIER
Increment / Decrement Instruction. The Increment/
Decrement command is different from the other com-
mands. Once the command is issued and the X9460
has responded with an acknowledge, the master can
clock the selected wiper up and/or down. For each
0
1
0
1
0
A1
A0
R/W
DEVICEADDRESS
SCL clock pulse (t
) while SDA is HIGH, the
HIGH
selected wiper will move one resistor segment towards
the R terminal. Similarly, for each SCL clock pulse
while SDA is LOW, the selected wiper will move one
H
The next three bits of the Slave Byte Address are the
device address. The device address is defined by the
resistor segment towards the R terminal. A detailed
L
A –A inputs. The X9460 compares the serial data
1
0
illustration of the sequence and timing for this opera-
tion are shown in Figures 7 and 8 respectively.
stream with the Slave Byte Address; a successful com-
pare is required for the X9460 to respond with an
acknowledge. The A –A inputs can be actively driven
1
0
Wiper Counter Register
by CMOS input signals or tied to V
or V . The R/W
CC
SS
The X9460 contains two Wiper Counter Registers. The
Wiper Counter Register output is decoded to select
one of thirty-two switches along its resistor array. The
Write Wiper Counter Register command directly sets
the WCR to a value. The Increment/Decrement
instruction steps the register value up or down one to
multiple times.
bit sets the device for read or write operations.
Command Set
After a Slave Byte Address match, the next byte sent
contains the Command and register pointer informa-
tion. The four most significant bits are the Command.
The next bit is a “X” (don’t care) set to zero.
The WCR is a volatile register (Table 3) and is reset to
the mute position (tap 0, “zero”) at power-up.
Figure 3ꢀ Command Byte Format
this bit not used, set to 0
Table 3ꢀ Wiper Counter Registers, ꢁ-bit - volatile:
WCR4
(MSB)
WCR3
WCR2
WCR1
WCR0
(LSB)
I3
I2
I1
I0
0
Z
RT
LT
D
The X9460 contains one 5-bit Wiper Counter Register
for each DCP. (Two 5-bit registers in total.)
WIPER COUNTER
SELECT
INSTRUCTIONS
The Z bit enables and disables the Zero Amplitude
D
Wiper Switching circuit. When Z =1, the wiper
D
switches will turn on when close-to-zero amplitude is
detected across the potentiometer pins. When Z =0,
D
Characteristics subject to change without notice. 6 of 17
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X9460
Table 2aꢀ Command Set
Instruction Set
Instruction
I
I
I
I
X
Z
D
RT LT
Operation
3
2
1
0
Read Wiper
LSB of Slave Byte=1, no command required
Slave will return Left then Right Data
Write Left Wiper
Counter
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1/0
1/0
1/0
0
1
1
1
0
1
Write new value to the Wiper Counter Register
Write new value to the Wiper Counter Register
Write new value to the Wiper Counter Register
Write Right Wiper
Counter
Write Both Wiper
Counters
Inc/Dec Left Wiper
Counter
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1/0
1/0
1/0
0
1
1
1
0
1
Enable Increment/decrement of the Control Latch
Enable Increment/decrement of the Control Latch
Enable Increment/decrement of the Control Latch
Inc/Dec Right Wiper
Counter
Inc/Dec Both Wiper
Counters
Notes: “1/0” = data is one or zero
Figure 4ꢀ Three-Byte Command Sequence (Read)
SCL
SDA
1
0
0
0
0
0
0
0
0
A
C
K
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
W
W
C
W
W
C
R
1
W
C
R
0
S
T
A
R
T
0
1
0
1
0
A1 A0 R/W A
C
0
0
0
0
A
C
K
S
T
C
R
4
C
R
2
R
3
O
P
K
DEVICE TYPE
IDENTIFIER
LEFT POT
RIGHT POT
DATA BYTE
DATA BYTE
Figure ꢁꢀ Three-Byte Command Sequence (Write)
SCL
SDA
0
0
0
0
0
0
0
1
0
1
0
0
0
W
C
W
C
W
C
W
W
S
T
A
R
T
0
1
0
1
0
A1 A0 R/W A I3 I2
I1 I0
ZD RT LT
A
C
K
A
C
K
S
T
C
R
1
C
R
0
C
K
R
4
R
3
R
2
O
P
DEVICE TYPE
IDENTIFIER
RIGHT or LEFT POT
INSTRUCTION BYTE
DATA BYTE
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X9460
Figure 6ꢀ Four-Byte Command Sequence (Write)
SCL
SDA
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
W W W W W
W W W W W
C C
R R
C
R
2
C
R
1
C
R
0
S
T
A
R
T
0
1
0
1 0 A1 A0 R/WA I3 I2 I1 I0 0 ZD RTLT A
C C
R R
C
R
2
C
R
1
C
R
0
A
C
K
A S
C T
K O
P
C
K
C
K
4
3
4
3
DEVICE TYPE
IDENTIFIER
LEFT POT
RIGHT POT
DATA BYTE
INSTRUCTION BYTE
DATA BYTE
Figure .ꢀ Increment/Decrement Command Sequence (Write)
SCL
SDA
0
0
0
0
0
1
0
S
T
A
R
T
0
1
0
1
0
A1 A0 R/W A I3 I2
I1 I0
ZD RT LT
A
C
K
I
I
D
E
C
1
S
T
I
D
C
K
N
C
1
N
C
2
N
C
n
E
C
n
O
P
DEVICE TYPE
IDENTIFIER
INSTRUCTION BYTE
INC and DEC active
Figure 8ꢀ Increment/Decrement Timing Limits
INC/DEC
CMD
ISSUED
t
WRID
SCL
SDA
VOLTAGE OUT
R
W
Wiper can move within 10µsecs after the falling edge of SCL
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X9460
INSTRUCTION FORMATS
Read Wiper Counter Register
device type
identifier
device
addresses
Left wiper position
(sent by slave on SDA)
Right wiper position
(sent by slave on SDA)
S
T
A
R
T
S
A
C
K
M
A
C
K
M S
A T
C O
K P
L
L
L
L
L
R R R R R
0 0 0 D D D D D
A A
0
1
0
1
0
0
0
0 D D D D D
1
0
4
3
2
1
0
4 3 2 1 0
Write Wiper Counter Register
Left or Right wiper
position
(sent by master on SDA)
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
S
T
A
R
T
S
A
C
K
S
S S
A T
C O
K P
A
C
K
A A
Z R L
D T T
D D D D D
4 3 2 1 0
0
1
0
1
0
1
0
1
0
0
0 0 0
1
0
Write Both Wiper Counter Registers
Left wiper position
(sent by master on
SDA)
Right wiper position
(sent by master on
SDA)
device type
identifier
device
addresses
instruction
opcode addresses
wiper
S
T
A
R
T
S
A
C
K
S
A
C
K
S
S S
A T
C O
K P
A
C
K
L L L L L
0 0 0 D D D D D
4 3 2 1 0
R R R R R
0 0 0 D D D D D
4 3 2 1 0
A A
1 0
Z
0 1 0 1 0
1 0 1 0 0
1 1
D
Increment/Decrement Wiper Counter Register
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
increment/decrement
(sent by master on SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
0
A1 A0
0
0
1
0
0 ZD RT LT
I/D I/D
.
.
.
.
I/D I/D
Definitions:
(1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A1 ~ A0”: stands for the device addresses sent by the master.
(3) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(4) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Characteristics subject to change without notice. 9 of 17
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X9460
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and the functional
operation of the device at these or any other conditions
above those listed in the operational sections of this
specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
Temperature under Bias.................... -65°C to +135°C
Storage Temperature.........................–65°C to +150°C
Voltage on SDA, SCL or any Address Input
with Respect to V ................................–1V to +6V
SS
Voltage on V+ (referenced to V ).........................+6V
SS
Voltage on V- (referenced to V )...........................-6V
SS
(V+) – (V-).............................................................. 12V
Any R ....................................................................V+
H
Any R ...................................................................... V-
L
Lead Temperature (Soldering, 10 seconds) ...... 300°C
I
max (10 secs)............................................... 3mA
W
RECOMMENDED OPERATING CONDITIONS
Temp
Minꢀ
Maxꢀ
Industrial
–40°C
+85°C
Device
X9460V14–2.7
Supply Voltage (V
)
V- Limits
-5.5V to -2.7V
V+ Limits
+2.7V to +5.5V
CC
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)(1)
Symbol Parameter Minꢀ Typꢀ Maxꢀ Unit Test Conditions
Dynamic Performance(2)(3)
Control Range
-62
0
dB
dB
dB
dB
dB
dB
Mute Mode
-92
-96
@1V rms
SNR
Signal Noise Ratios (Unweighted)
@1V rms @ 1kHz, Tap = -6dB
@1V rms @ 1kHz, Tap = -6dB
@1kHz, tap = -6dB
THD + N Total Harmonic Distortion + Noise
-95
XTalk
DCP Isolation
-102
-105
Digital Feedthrough
(Peak Component)
tap = -6dB
-3db Cutoff Frequency
100
kHz
DC Accuracy
Step Size
-1
-4
dB
dB
dB
dB
dB
dB
Steps of -1, -2, -3, -4 dB
For -1dB steps
Step Size Error
Step Size Error
Step Size Error
Step Size Error
DCP to DCP Matching
-0.2
-0.4
-0.6
-0.8
-0.1
+0.2
+0.4
+0.6
+0.8
0.1
For -2dB steps
For -3dB steps
For -4dB steps
Notes: (1) V = | V- |
CC
V
Ramp up timing 0.2 V/ms < Vcc Ramp Rate < 50 V/ms
CC
(2) This parameter is guaranteed by design and characterization
(3) T = 25oC, V = 5.0V; 20 Hz to 20kHz Measurement Bandwidth with 80kHZ filter, input signal 1Vrms, 1kHz Sine Wave.
A
CC
Characteristics subject to change without notice. 10 of 17
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X9460
ANALOG CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)(1)
ANALOG INPUTS
Symbol
Parameter
Voltage on R , R , and R pins
Minꢀ Typꢀ Maxꢀ
Unit
V
Test Conditions
Typical 33KΩ
V
V-
V+
TERM
L
W
H
R
End to End Resistance
Input Capacitance R , R , R
W
-20
+20
%
TOTAL
Cin(4)
25
pF
T = 25oC
L
H
A
(2)
I
Wiper Current
Wiper Resistance
Voltage on V- pin
Voltage on V+ pin
Noise
-3
+3
mA
Ω
W
R
100
200
-2.7
+5.5
Wiper Current = 3mA
W
V-
-5.5
V
V+
+2.7
V
2
µVrms
20 HZ to 20KHZ, Grounded Input
@ -6dB tap
(2)
TC
Temperature Coefficient of re-
sistance
-300
PPM/°C
R
DꢀCꢀ OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)(1)
Limits
Symbol
Parameter
Minꢀ
Typꢀ
Maxꢀ
Units
Test Conditions
I
V
Supply Current (Move
200
300
µA
f = 400kHz, SDA = Open,
SCL
Other Inputs = V
SS
CC1
CC
Wiper, Write, Read)
I
I
V
Current (Standby)
3
1
µA
µA
µA
SCL = SDA = V , Addr. = V
CC SS
SB
CC
Input Leakage Current
Analog Input Leakage
10
10
V
= V to V
SS CC
LI
IN
Iai
0.1
V
= V- to V+ with all other
IN
analog inputs floating
I
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output LOW Voltage
µA
V
V
OUT
= V to V
LO
SS
CC
V
V
V
V
x 0.7
V
+ 0.5
IH
IL
CC
CC
–0.5
V
x 0.1
V
CC
0.4
V
I
= 3mA
OL
OL
CAPACITANCE
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2 and SCL)
Maxꢀ
Units
pF
Test Conditions
(4)
C
C
8
6
V
= 0V
= 0V
I/O
I/O
(4)
pF
V
IN
IN
Notes: (4) This parameter is not 100% tested.
Characteristics subject to change without notice. 11 of 17
REV 4.0.13 6/25/02
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X9460
AꢀCꢀ TEST CONDITIONS
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
Input Rise and Fall Times
Input and Output Timing Level
10ns
V
x 0.5
CC
EQUIVALENT AꢀCꢀ LOAD CIRCUIT
5V
1533Ω
SDA OUTPUT
100pF
AC TIMING (Over recommended operating conditions)
Symbol Parameter
Minꢀ Maxꢀ Units
f
t
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCL
Clock Cycle Time
2500
600
1300
600
600
600
500
50
CYC
Clock High Time
HIGH
Clock Low Time
LOW
Start Setup Time
SU:STA
HD:STA
SU:STO
SU:DAT
HD:DAT
Start Hold Time
Stop Setup Time
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
(2)
300
300
900
R
(2)
F
(2)
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
AA
(2)
50
50
1300
0
DH
T (2)
Noise Suppression Time Constant at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1(2)
I
(2)
t
t
t
BUF
SU:WPA
HD:WPA
A0, A1(2)
0
DCP TIMING(2)
Symbol
Parameter
Minꢀ Maxꢀ Units
t
t
t
Wiper Response Time After The Third (Last) Power Supply Is Stable
Wiper Response Time After Instruction Issued (All Load Instructions)
Wiper Response Time From An Active SCL Edge (Increment/Decrement Instruction)
10
10
10
µs
µs
µs
WRPO
WRL
WRID
Characteristics subject to change without notice. 12 of 17
REV 4.0.13 6/25/02
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X9460
TIMING DIAGRAMS
Figure 9ꢀ START and STOP Timing
(START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
R
F
SDA
Figure 10ꢀ Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Figure 11ꢀ Output Timing
SCL
SDA
t
t
DH
AA
Figure 12ꢀ DCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
VWx
LSB
t
WRL
Characteristics subject to change without notice. 13 of 17
REV 4.0.13 6/25/02
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X9460
TYPICAL PERFORMANCE CHARACTERISTICS
(V ,V+ = 5.0V,V- = -5.0V, T = + 25 °C, unless otherwise noted)
CC
A
FFT Spectrum
(with 1kHz 1Vrms input, tap = -6dB)
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
d
B
V
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
H z
Figure 13ꢀ Single Tone Frequency Response
THD+N vs Frequency
(with 80kHz low-pass filter, tap = -6dB)
-6 0
-6 5
-7 0
-7 5
-8 0
-8 5
d
B
-9 0
-9 5
-1 00
-1 05
-1 10
-1 15
-1 20
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 14ꢀ THD + N
Characteristics subject to change without notice. 14 of 17
REV 4.0.13 6/25/02
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X9460
TYPICAL PERFORMANCE CHARACTERISTICS
(V ,V+ = 5.0V,V- = -5.0V, T = + 25 °C, unless otherwise noted)
CC
A
Mute Mode
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
d
B
V
-100
-110
-120
-130
-140
20
50
100
200
500
Hz
1k
2k
5k
10k
20k
Figure 15. Mute
Characteristics subject to change without notice. 15 of 17
REV 4.0.13 6/25/02
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X9460
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 16 of 17
REV 4.0.13 6/25/02
www.xicor.com
X9460
ORDERING INFORMATION
T
V
X9460
K
P
V
Limits
CC
Device
Blank = 5V 10ꢀ
-2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I= Industrial = –40°C to +85°C
Package
V14 = 14-Lead TSSOP
Potentiometer Organization
Left Pot
33KΩ 20ꢀ
Right Pot
33KΩ 20ꢀ
K =
X9460 TSSOP 14L Top Mark Instructions
Commercial
Industrial
X9460KV
EYWW I
X9460KV
EYWW
5.0 volt
2.7 volt
X9460KV
EYWW G
X9460KV
EYWW F
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 17 of 17
REV 4.0.13 6/25/02
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