X9470 [XICOR]
RF Power Amplifier (PA) Bias Controller; 射频功率放大器（ PA）偏置控制器
| 型号： | X9470 |
| 厂家： | 
XICOR INC. |
| 描述： | RF Power Amplifier (PA) Bias Controller |
| 文件： | 总25页 (文件大小：542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
RF Power Amplifier (PA) Bias Controller
X9470
FEATURES
DESCRIPTION
• Programmable Bias Controller IC for Class A and
AB LDMOS Power Amplifiers
• Adaptive System on Chip Solution
• Bias Current Calibration to better than 4ꢀ
using Reference Trim DCP
The Xicor X9470 RF PA Bias Controller contains all of
the necessary analog components to sense the PA
drain current through an external sense resistor and
automatically control the gate bias voltage of an
LDMOS PA. The external sense resistor voltage is
amplified by an instrumentation amplifier and the out-
put of the amplifier along with an external reference
voltage is fed to the inputs of a comparator. The com-
parator output indicates which direction the LDMOS
gate bias voltage will move in the next calibration
cycle. System calibration is accomplished by enabling
the X9470 and providing a clock to the SCL pin. The
LDMOS drain current can be maintained constant over
temperature and aging changes by periodic calibra-
tion. The VOUT pin can be used to monitor the aver-
age power by tracking the drain current. Up to eight
X9470 or additional Xicor Digital Potentiometers can
be controlled via a two-wire serial bus.
• Automatic Bias Point Tracking and Calibration
— I
Sensing and Tracking
DQ
—Programmable Instrumentation Amplifier to
Scale Wide Range of I
DQ
—Programmable Gate Bias Driver
—All Programmable settings are Nonvolatile
—All Settings Recalled at Power Up.
• 28V Maximum V
DD
• 2 Wire Interface for Programming Bias Setting
and Optimizing I Set Point
DQ
• Bias Level Comparator
• Shutdown Control pin for PA Signal
• Slave address to allow for multiple devices
• 24-pin TSSOP Package
• Applications: Cellular Base Stations (GSM,
UMTS, CDMA, EDGE),TDD applications, Point-
to-multipoint, and other RF power transmission
systems
TYPICAL APPLICATION
V
DD
RW
RH
RL
REF
V+
AGND
V
OUT
INC/DEC
REF
REF
V
SENSE+
C
A2
A1
BULK
R
REF
V
REF
∆V
R
SENSE
V
SENSE–
choke
Comparator
Instrumentation
Amplifier
A0
VP
SDA
SCL
VREF
control
I2C
interface
RBIAS
Vbias
V
BIAS
control
+
FILTER
RF
out
–
Control &
Status Registers
RF PA in
Matching
RF Impedance
EEPROM
Class A Example
VCC
VSS
CS
RH
RW
RL
BIAS
SHDN
BIAS
BIAS
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Preliminary Information
X9470
PIN CONFIGURATION
TSSOP
X9470
V
V
24
23
22
sense-
sense+
1
2
3
4
5
6
SHDN
RH
RL
REF
REF
INC/DEC
21
20
19
18
17
16
V
RW
AGND
OUT
REF
V+
VSS
CS
SCL
V
CC
V
7
8
CC
V
BIAS
SDA
VSS
9
RH
RW
A2
10
11
12
BIAS
BIAS
15
14
13
A1
RL
A0
BIAS
ORDERING INFORMATION
Part Number
Temperature Range
Package
X9470V24I
-40°C TO 85°C
24-Lead TSSOP
PIN DESCRIPTIONS
TSSOP pin Symbol
Brief Description
1
2
V
Positive sense voltage input terminal
SENSE+
RH
Upper Terminal of Potentiometer, called the R
upper voltage limit of the adjustment for the Up/Down threshold of the comparator.
potentiometer. The voltage applied to this pin will determine the
REF
REF
3
4
RL
Lower Terminal of Potentiometer, called the R
potentiometer. The voltage applied to this pin will determine the
REF
REF
lower voltage limit of the adjustment for the Up/Down threshold of the comparator.
RW
Wiper Terminal of Potentiometer, called the R potentiometer. The voltage on this pin will be the threshold for
the Up/Down comparator. Also referred to as the V
REF
REF
of the comparator.
REF
5
6
7
AGND
VSS
CS
Analog ground to allow single point grounding external to the package to minimize digital noise.
System (Digital) Ground Reference
Chip Select. This input enables bias calibration adjustments to the R
pull-down.
potentiometer. CMOS input with internal
BIAS
8
SCL
SDA
Dual function. Function 1: The increment control input. Increments or decrements the R
Function 2: Serial Data Clock Input. Requires external pull-up.
potentiometer.
BIAS
9
Serial Data Input. Bi-directional 2-wire interface. Requires external pull-up.
10
RH
Upper Terminal of Potentiometer, called the R
potentiometer. The voltage applied to this pin will determine the
pin).
BIAS
BIAS
BIAS
upper limit of the bias voltage to the PA (or V
11
12
13
14
15
RW
Wiper Terminal of Potentiometer, called the R
potentiometer. This voltage is the equivalent to the unbuffered
BIAS
BIAS
BIAS
voltage that will appear at the V
pin.
BIAS
RL
A0
A1
A2
Lower Terminal of Potentiometer, called the R
lower limit of the bias voltage to the PA (or V
potentiometer. The voltage applied to this pin will determine the
pin).
BIAS
BIAS
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
16
17
18
19
20
21
22
VSS
System (Digital) Ground Reference
V
V
V
This is the bias output voltage pin and is used to drive the filter network to the PA gate.
System (Digital) Supply Voltage
BIAS
CC
System (Digital) Supply Voltage
CC
V +
Positive voltage supply for the instrumentation amplifier and other analog circuits.
Instrumentation Amplifier output that is 20x or 50x the voltage across the Rsense pins.
V
OUT
INC/DEC Status output that indicates the state of the comparator. When this pin is HIGH, the RBIAS potentiometer will in-
crement; when the pin is LOW, the RBIAS potentiometer will decrement. This pin is open drain and requires ex-
ternal resistor pull-up.
23
24
SHDN
Shutdown the output op amp. When SHDN is active (HIGH), the V
Negative sense voltage Input terminal
pin is pulled LOW.
BIAS
V
SENSE-
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Preliminary Information
X9470
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those listed in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
Voltage on V+ (referenced to AGND)....................... 7V
Voltage on VCC (reference to VSS)......................... 7V
Voltage on all RH, RW, RL pins
(reference to AGND): ........................................... 7V
Voltage on Vsense+ or
Vsense- (reference to AGRND).......................... 30V
Voltage on SDA, CS, SCL, SHDN
(reference to AGND) ............... -0.3V to (Vcc + 0.3V)
Current into Output Pin:.......................................... 5mA
Continuous Power Dissipation:........................ 500mW
Operating Temperature range: ...............-40°C to +85°C
Junction Temperature:........................................... 150°C
Storage Temperature......................... -65°C to +150°C
Lead Temperature (Soldering, 10 seconds): ..... 300°C
ELECTRICAL CHARACTERISTICS
INSTRUMENTATION AMPLIFIER
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C,
A
unless otherwise noted.)
Limits
Symbol
Parameter
Min. Typ. Max. Units
Test Conditions/Notes
(10)
V
Common Mode Input Voltage on
20
28
V
IN
V
and V
pins
SENSE+
SENSE-
(2)
Gain 1
Gain 2
Gain from V
to V
20
50
V/V Measured with Status
Register bit SR0=0
SENSE
SENSE
OUT
OUT
(2)
Gain from V
to V
V/V Measured with Status
Register bit SR0=1
V
Differential voltage sense range be-
tween V and V for gain 1
60
90
60
mV Gain = 20
RANGE1
RANGE2
SENSE+
SENSE-
V
Differential voltage sense range be-
tween V and V for gain 2
40
mV Gain = 50
SENSE+
SENSE-
V
Input Offset Voltage
0.5
1.5
mV
%
V
= 40mV to 90mV
SENSE
OS
T = 25°C
A
Av1
Av2
Avt1
Gain 1 Error
Gain = 20 (4)
V
= 60mV to 90mV
SENSE
T = 25 to 85°C, Gain = 20
A
Gain 2 Error
Gain = 50 (4)
1.5
%
V
= 40mV to 60mV
SENSE
T = 25 to 85°C, Gain = 50
A
Total Error, Gain 1
Gain = 20 (5)
-6
-6
1.5
10
1.5
10
2
6
6
%
%
%
%
%
V
= 60mV to 90mV
SENSE
T = 85°C, Gain = 20
A
V
= 60mV to 90mV
SENSE
T = 25 to 85°C, Gain = 20
A
Avt2
At
Total Error, Gain 2
Gain = 50 (5)
V
= 40mV to 60mV
SENSE
T = 85°C, Gain = 50
A
V
= 40mV to 60mV
SENSE
T = 25 to 85°C, Gain = 50
A
Long Term Drift
Avt1 or Avt2
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Preliminary Information
X9470
ELECTRICAL CHARACTERISTICS
INSTRUMENTATION AMPLIFIER (CONTINUED)
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C,
A
unless otherwise noted.)
Limits
Symbol
Parameter
Min. Typ. Max. Units
Test Conditions/Notes
SR(10)
Slew Rate of Instrumentation Amp
0.2
V/µS ∆V
= 20mV step,
Cout = 10pF Measured at
SENSE
(1,3)
V
OUT
(10)
T
Setting time of Instrumentation Amp
5.0
µS
∆V
= 20mV step, Cout =
settle
SENSE
10pF, settling to 1% of final value
(1,3)
Measured at V
OUT
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
40
55
dB
dB
V
For both Gain 1 and Gain 2
For both Gain 1 and Gain 2
Gain = 20
V
V
Voltage Swing
0.3
0.3
1.8
3.0
OUT
OUT
Range
V
Gain = 50
V
V
V
Voltage Noise, rms
3
mV Gain = 20
OUT
OUT
Noise(10)
(10)
I
, V
Input Bias
, V Input
SENSE+ SENSE-
250
10
µA
pF
T = 25°C
A
VSENSE
SENSE+ SENSE-
Current
(10)
C
V
Each Input
VSENSE
Capacitance
COMPARATOR
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V;Vsense+, Vsense- = 26V;T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
VOL
Io(10)
Parameter
Min. Typ. Max. Units
Test Conditions/Notes
IOL = 1mA
Output Voltage Low on the INC/DEC pin
0.4
3
V
Output sink Current
mA INC/DEC pin, open drain
mV Vcc = 5 V
Vos(10) Input Hysteresis
Tpd(10) Response Time for propagation delay
20
2
µS
INC/DEC pin with 2KΩ pull up
VREF DCP CIRCUIT BLOCK
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C,
A
unless otherwise noted.)
Limits
Symbol
Parameter
End to End Resistance
Number Taps or Positions
Min.
Typ. Max. Units
Test Conditions/Notes
R
8
10
12
64
KΩ
TOTAL
V
RH
Terminal Voltage
Terminal Voltage
AGND
AGND
AGND
V
V
V
V
V
AGND = 0V
AGND = 0V
AGND = 0V
RH
REF
+
+
+
V
RL
RL
REF
V
RW
Terminal Voltage
V
RW
REF
Power Rating(10)
2.5
mW
R
=10 KΩ
TOTAL
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Preliminary Information
X9470
VREF DCP CIRCUIT BLOCK
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C,
A
unless otherwise noted.)
Limits
Symbol
Parameter
Min.
Typ. Max. Units
Test Conditions/Notes
Resolution(10)
1.6
%
Absolute Linearity(6)
Relative Linearity(7)
-0.2
-0.2
+0.2
+0.2
MI(8)
MI(8)
R
Temperature Coefficient(10)
300
10
ppm/°C
TOTAL
Ratiometric Temperature Coefficient(10)
-20
+20 ppm/°C
pF
(10)
C
Potentiometer Capacitances on RH
and RL
IN
REF
REF
BIAS ADJUSTMENT DCP CIRCUIT BLOCK
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V;Vsense+, Vsense- = 26V;T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
End to End Resistance Variation
Number Taps or Positions
Min.
Typ. Max. Units
Test Conditions/Notes
R
8
10
12
KΩ
with 20% variation
TOTAL
256
V
Voltage at the RH
Terminal Voltage AGND
V
V
V
V
V
AGND = 0V
AGND = 0V
AGND = 0V
RH
BIAS
+
+
+
V
Voltage at the RL
Terminal Voltage
AGND
RL
BIAS
V
Voltage at the RW
Power Rating(10)
Resolution(10)
Terminal Voltage AGND
V
RW
BIAS
2.5
0.4
mW
R
=10 KΩ
TOTAL
%
Absolute Linearity(6)
Relative Linearity(7)
-1.0
-1.0
+1.0
+1.0
MI(8)
MI(8)
ppm/°C
ppm/°C
pF
R
Temperature Coefficient(10)
300
10
TOTAL
Ratiometric Temperature Coefficient(10)
-50
50
(10)
C
Potentiometer Capacitances on RH
IN
BIAS
and RL
BIAS
VBIAS OUTPUT VOLTAGE FOLLOWER
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C,
A
unless otherwise noted.)
Limits
Symbol
Parameter
Min. Typ.
Max.
Units
Test Conditions/Notes
V
Input Offset Voltage
10
10
mV
OS
(10)
V
Offset Voltage Temperature
Coefficient
µV/°C T = -40 to +85°C
A
OSDRIFT
SR
Output Slew Rate on V
0.5
V/µS
R = 10kΩ, 1nF, ∆V
=
BIAS
L
BIAS
20mV
V
Voltage Output Swing
1.5
V
– 0.5
V
I
= 10mA
OUT
BIAS
CC
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Preliminary Information
X9470
VBIAS OUTPUT VOLTAGE FOLLOWER
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C,
A
unless otherwise noted.)
Limits
Symbol
Parameter
Settling Time
Min. Typ.
Max.
Units
Test Conditions/Notes
Final value 1%, R = 10kΩ,
(10)
T
2
µs
S
L
1nF, ∆V
= 20mV
BIAS
t
Time for SHDN pin (delay) valid
Power Supply Rejection Ratio
0.1
1.0
µs
SHDN
PSRR
45
55
dB
VCC supply V = 4.75 to
CC
5.25V
Input Voltage Range
Load Capacitance
1.5
V
– 0.5
V
nF
pF
Ω
CC
(10)
C
1
10
3
L
(10)
C
Capacitances on Shutdown Pin
Output Impedance
IN
(10)
R
at 5MHz, 1nF load
OUT
D.C. OPERATING CHARACTERISTICS
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V;Vsense+, Vsense- = 26V;T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
V+ Active Current
Active Current
Min.
Typ.
Max.
3
Units
mA
Test Conditions
CS = V – 0.3V, and SCL
CYC, SDA = CC
0.3V, SHDN inactive
(9)
I
1
5
CC1
CC
@ max. t
V
–
(9)(10)
I
V
25
mA
CC2
CC
(9)
I
Standby Supply Current
(V , V+)
CC
1.5
mA
CS = V , and SCL inactive
SB
IL
(no clock)
active
V , SHDN
, SDA = IL
I
CS, SDA, SCL, SHDN RH, RL, RW,
INC/DEC VOUT, Input Leakage
-10
10
µA
V
V
= VSS to V
CC
LI
IN
(10)
V
V
CS, SDA, SCL, SHDN, A0, A1, A2
HIGH Voltage
V
x 0.7
V
+ 0.5
CC
IH
CC
(10)
CS, SDA, SCL, SHDN, A0, A1, A2
LOW Voltage
–0.5
V
x 0.3
CC
V
IL
(10)
C
CS, SDA, SCL, SHDN, A0, A1, A2
Capacitance
10
pF
V
= 5V, V = VSS,
CC IN
IN
T = 25°C, f = 1MHz
A
Notes: (1) V
is a high impedance output intended for light loads only.
OUT
(2) Gain at V
is set to 20 by default.
OUT
(3) Value given is for V
. The V
output will depend on the V
potentiometer which is initially loaded with a zero value, then
BIAS
OUT
BIAS
followed by the loading of the final value from E2 memory.
(4) Gain Error excludes the contribution of the input offset voltage error
(5) Total Error includes the contributions of gain error and input offset voltage error.
(6) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage = (V
(actual) – V
(expected))
w(n)
w(n)
(7) Relative Linearity is a measure of the error in step size between taps = V
– [V
+ Ml]
w(n)
W(n+1)
(8) 1 Ml = Minimum Increment = R
/63 or R
/255.
TOT
TOT
(9) Typical values are for T = 25°C and nominal supply voltage, VCC = 5V
A
(10) This parameter is not 100% tested.
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Preliminary Information
X9470
BIAS ADJUSTMENT CIRCUIT BLOCK
A.C. OPERATING CHARACTERISTICS
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V;Vsense+, Vsense- = 26V;T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
CS to SCL Setup
Min.
Typ.(9)
Max.
Units
ns
t
t
100
Cl
lD
Vsense Change to INC/DEC Change
SCL LOW Period
5
µs
t
1.5
1.5
100
µs
lL
t
SCL HIGH Period
µs
lH
(10)
t
SCL Inactive to CS Inactive
ns
lC
(10)(11)
t
SCL to V
Change
BIAS
3
µs
IW
t
SCL Cycle Time
3
µs
CYC
(10)
t
t
SCL Input Rise and Fall Time
500
ns
,
R
F
A.C. TIMING
CS
t
CYC
t
t
t
t
IC
CI
IL
IH
90% 90%
10%
SCL
t
t
t
R
ID
F
INC/DEC
t
IW
V
BIAS
(Vsense+ –
Vsense-)
Note: (11) MI in the A.C. timing diagram refers to the minimum incremental change in the V
output due to a change in the wiper position.
BIAS
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Preliminary Information
X9470
AC SPECIFICATIONS
Symbol
Parameter
Min.
0
Max. Unit
f
SCL Clock Frequency
400
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
ns
ns
pF
SCL
(10)
t
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
50
IN
(10)
t
0.1
1.3
1.3
0.6
0.6
0.6
200
200
0.6
50
0.9
AA
(10)
t
BUF
t
LOW
t
Clock HIGH Time
HIGH
t
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
SU:STA
HD:STA
SU:DAT
HD:DAT
t
t
t
t
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SU:STO
(10)
t
DH
(10)
t
SDA and SCL Rise Time
20 +.1Cb(12) 300
20 +.1Cb(12) 300
400
R
(10)
t
SDA and SCL Fall Time
F
Cb(10)
Capacitive load for each bus line
Note: (12) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
t
t
t
t
R
F
HIGH
LOW
SCL
SDA IN
t
SU:DAT
t
t
t
SU:STO
SU:ST
HD:DAT
t
HD:STA
t
t
t
BUF
AA
DH
SDA OUT
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Preliminary Information
X9470
Write Cycle Timing
SCL
8th Bit of Last Byte
ACK
SDA
t
WC
Stop
Start
Condition
Condition
Power Up Timing
Symbol
Parameter
Min.
Max.
50
Unit
(10)
t V
V Power-up rate
CC
0.2
V/ms
r
CC
Note: Delays are measured from the time V
is stable until the specified operation can be initiated. These parameters are not 100% tested.
CC
Proper recall of stored wiper setting requires a V
power-up ramp that is monotonic and with noise or glitches < 100mV. It is important
CC
to correctly sequence voltages in an LDMOS amplifier circuit. For the X9470 typical application, the V , then V+ pins should be pow-
CC
ered before the V
of the LDMOS to prevent LDMOS damage. Under no circumstances should the V
be applied to the LDMOS
DD
DD
device before V and V+ are applied to the X9470.
CC
DCP Default Power-up Tap Positions (shipped from factory)
VREF DCP
0
0
Bias Adjust DCP
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
10
Unit
(10)
t
Write Cycle Time
5
ms
WC
Note:
t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
WC
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
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Preliminary Information
X9470
DETAILED PIN DESCRIPTIONS
Supply Pins
matically update with either an increment or decrement
of one tap position according to INC/DEC signal from
the comparator.
Digital Supplies VCC, VSS
The positive power supply and ground for the DCP dig-
ital control sections. VSS is normally tied to digital
ground. The X9470 is provided with separate digital
and analog power supply pins to better isolate digital
noise from the analog section.
When CS is LOW (disabled), the wiper counter of the
XDCP will hold the last wiper position until CS is
enabled again and the wiper position is updated.
INC/DEC Monitor Pin
The Up or Down Monitor pin (INC/DEC) indicates the
state of the comparator. This signal indicates that the
Instrumentation Amplifier output voltage is higher or
Analog Supplies V+, AGND
The positive analog supply and ground for the Instru-
mentation Amplifier (IA). The analog supply ground is
kept separate to allow an external single point connec-
tion. V+ can be a separate supply voltage from VCC, or
VCC can be filtered before connection to V+.
lower than the voltage level set by the RW
pin. The
REF
output is used to indicate the direction that the gate
bias voltage needs to move to reach the target bias
voltage.
Bias Adjustment Circuit Block Pins
Sense and Scale Block Pins
RH
, RL
, and RW
for VBIAS Adjust-
BIAS
BIAS
BIAS
V
and V
SENSE-
SENSE+
ments.
These pins are the connections to a Xicor Digitally
Controlled Potentiometer (XDCPTM) or R
potenti-
ometer. RH
ence, and the RL
These are the input pins to the IA circuit. These pins
are used to determine the change in voltage across the
the external drain sense resistor of an RF power ampli-
fier.
BIAS
is connected to the most positive refer-
BIAS
is connected to the least positive
BIAS
reference voltage. The potentiometer has a resolution
of 256-taps and typical R of 10kohm. So for
RH
, RL
, and RW
. PA Bias Set Point.
REF
REF
REF
TOTAL
The PA Bias reference voltage is controlled by a 64-tap
(10k ohm typical R ) potentiometer, called the
example, to provide 4mV resolution, the voltage differ-
ence applied to the RH and RL pins must be
TOTAL
BIAS
BIAS
R
potentiometer. The voltages applied to RH
REF
REF
1.024V. The RW
value can be stored in non-vola-
BIAS
and RL
will determine the range of adjustment of
REF
tile memory and recalled upon power up.
the reference voltage level (VREF) for the Comparator.
The resolution of the comparator reference is the differ-
ence of the voltages applied to RH
divided by 63. The position of the wiper (RW
controlled via serial bus. The RW
Serial Clock (SCL).
and RL
REF
REF
) is
This is a dual function input pin.The state of the CS pin
determines the functionality.
REF
value can be
REF
stored in non-volatile memory and recalled upon power
up.
Function 1: SCL is a negative edge-triggered control
pin of the R
potentiometer. Toggling SCL will
BIAS
either increment or decrement the wiper in the
direction indicated by the logic level on the INC/DEC
pin. CS must be high for this function.
RW
is also an input signal used as a scaling volt-
REF
age (VREF) to set the appropriate I
amplifier.V
of an RF power
DQ
can be derived from an external voltage
REF
divider or from a baseband processor or similar micro-
controller. V can be set permanently or changed
dynamically using the potentiometer for various PA
operating points.
Function 2: SCL is the serial bus clock for serial bus
interface. CS must be low for this function.
REF
Chip Select (CS). Calibration Enable.
The CS input is the enable bias adjustments. When the
CS is HIGH (enabled) and a SCL pulse is present, the
wiper position on the R
potentiometer will auto-
BIAS
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Preliminary Information
X9470
V
TYPICAL APPLICATION
OUT
This pin is the output of the IA, which reflects a 20x or
50x gain of the input signal (voltage across the Vsense
pins). It can be used to indicate the magnitude of the
drain current envelope when RF is present.
The X9470 can be used along with a microprocessor
and transmit control chips to control and coordinate
FET biasing (see Figure 1). The CS, SCL, and SDA
signals are required to control the X9470 Bias Adjust-
ment Circuit Block. An internal R
voltage is pro-
WREF
Output Block Pins
vided via a programmable voltage divider between the
RH and RL pins and is used to set the voltage
REF
REF
V
BIAS
reference of the comparator. The shutdown (SHDN)
and bias voltage indicators (INC/DEC) are additional
functions that offer FET control, monitoring, and pro-
tection.
The V
is the gate bias voltage output. It is buffered
BIAS
with a unity gain amplifier and is capable of driving 1nF
(typical) capacitive loads.
This pin is intended to be connected through an RF fil-
ter to the gate of an LDMOS power transistor. The volt-
Typically, the closed loop setup of the X9470 allows for
final calibration of a power amplifier at production test.
The CS and SCL pins are used to perform this calibra-
tion function. Once in a base station, the amplifier can
then be re-calibrated any time that there is no RF sig-
nal present. The bias setting block can also be used
open loop to adjust gate bias or can be shutdown
using the SHDN pin. The sense and scale block can be
used for amplifier power monitoring diagnostics as
well.
age of V
is determined by the XDCP’s value of the
BIAS
R
resistor.
BIAS
Other Pins
SHDN
SHDN is an input pin that is used to shutdown the
V
output voltage follower. When the SHDN pin is
BIAS
HIGH, the V
is shutdown, the current R
pin is pulled to VSS. When the device
BIAS
The range of the drain bias current operating point of
the LDMOS FET is set by an external reference across
the reference potentiometer. The wiper of the potenti-
wiper position will be
BIAS
maintained in the wiper counter register. When shut-
down is disabled, the wiper returns to the same wiper
position before shutdown was invoked. Note that when
the device is taken out of shutdown mode (SHDN goes
from HIGH to LOW), the CS input must be cycled once
to enable calibration.
ometer sets the trip point for comparison with V , the
P
amplified voltage across R
, the drain resistor.
SENSE
The output of the comparator causes the R
poten-
BIAS
tiometer to increment or decrement automatically on
the next SCL clock cycle. This R potentiometer is
BIAS
configured as a voltage divider with a buffered wiper
output which drives the gate voltage of an external
LDMOS FET.
SDA
Serial bus data input/output. Bi-directional. External
pullup is required.
Once the optimum bias point is reached, the R
BIAS
value is latched into a wiper counter register. Again,
the V gate voltage can be updated continuously or
periodically depending on the system requirements.
A0, A1, A2
BIAS
Serial bus slave address pins. These pins are used to
defined a hardware slave address. This will allow up to
8 of the X9470’s to be shared on one two-wire bus.
These are useful if several X9470’s are used to control
the bias voltages of several LDMOS Power Transistors
in a single application. Default hardware slave address
is “000” if left unconnected due to internal pull-down
resistor.
Both terminals of the R potentiometer are access-
BIAS
ible and can be driven by external reference voltages
to achieve a desired I vs. gate voltage resolution, as
DQ
well as supporting temperature compensation circuitry.
In summary, the X9470 provides full flexibility on set-
ting the operating bias point and range of an external
RF power amplifier for GSM, EDGE, UMTS, CDMA or
other similar applications.
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Preliminary Information
X9470
Figure 1. Typical Application
V
DD
RW
RH
RL
REF
V+
AGND
V
OUT
INC/DEC
REF
REF
V
SENSE+
C
A2
BULK
R
REF
V
REF
A1
A0
∆V
R
SENSE
V
SENSE–
choke
Comparator
Instrumentation
Amplifier
VP
SDA
SCL
VREF
control
I2C
interface
RBIAS
Vbias
V
BIAS
control
+
FILTER
RF
out
–
Control &
Status Registers
RF PA in
Matching
RF Impedance
EEPROM
Class A Example
VCC
VSS
CS
RH
RW
RL
BIAS
SHDN
BIAS
BIAS
X9470 FUNCTIONAL DESCRIPTION
the Sense and Scale Block will set the Bias Adjustment
Circuit Block to operate in a given voltage range (mV)
vs. drain current adjustment (mA).
This section provides detail description of the following:
– Sense and Scale Block Description
– Bias Adjustment Control Block Description
– Output Block Description
V
REF
I
DQ ꢀ
(1)
K * R
1
SENSE
K is fixed 50x for the internal comparator input.
1
– Bias Adjustment and Storage Description
The output of the IA is also available at the pin Vout to
enable drain current monitoring. The gain at Vout is
SENSE AND SCALE BLOCK
fixed at a factor of K , lower than K so that high I
2
1
DQ
The Sense and Scale Circuit Block (Figure 2) implements
currents will not cause saturation of the Vout signal.
The equation for Vout is given as:
an instrumentation amplifier whose inputs (V
and
SENSE+
V
) are across an external sense resistor in the
SENSE-
∆V = I
* R
SENSE
DQ
drain circuit of an RF Power FET. V
is connected
SENSE+
to V , the drain voltage source for the RF power FET,
V
= K * ∆V
2
DD
OUT
and V
pin is connected to the other end the exter-
SENSE-
K is fixed to 20x for the Vout pin
2
nal sense resistor.
An internal instrumentation amplifier (IA) will sense the
BIAS ADJUSTMENT CIRCUIT BLOCK
∆V and amplify it by a gain factor of K (see Equation
1
There are three sections of this block (Figure 3): the
input control, counter and decode section (1), the
resistor array (2); and the non-volatile register (3). The
input control section operates just like an up/down
counter. The input of the counter is driven from the out-
put of the comparator in the Sense and Scale Block
and is clocked by the SCL signal. The output of this
counter is decoded to select one of the taps of a 256-
tap digital potentiometer.
1). The resulting output is compared with V
at the
REF
comparator. V
can be a fixed reference voltage or
REF
adjusted by using the 64-tap digital potentiometer. The
output of the comparator is used to increment or decre-
ment the R
potentiometer in the Bias Adjustment
BIAS
Circuit Block. The gain factor K is designed such that
1
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Preliminary Information
X9470
Figure 2. Sense and Scale Block Diagram
V
DD
R
SENSE
V
V
SENSE–
SENSE+
V
INC/DEC
RW
RH
RL
REF
OUT
REF
REF
I
DQ
Cint~2pF 10%
∆V
10kΩ
64-tap
K = 20X
2
~1kohm
RF
V
PA
REF
choke
Out
Precision
I-Amp
Comparator
INC/DEC
K = 50X
1
V
gate
RF PA in
The wiper of the digital potentiometer acts like its
mechanical equivalent and does not move beyond the
last position. That is, the counter does not wrap around
when clocked to either extreme. The electronic
switches in the potentiometer operate in a “make
before break” mode when the wiper changes tap posi-
tions. If the wiper is moved several positions, multiple
Storing Bias Resistor Values in Memory. Wiper val-
ues are stored to VOLATILE memory automatically
when CS is HIGH and INC/DEC either transitions from
HIGH to LOW or from LOW to HIGH. Wiper values are
stored to NON-VOLATILE memory during Byte Write
or as described in the following section.
taps are connected to the wiper for t
(SCL to
Table 1. Mode Selection
INC /
IW
RW
change).
BIAS
SDA CS* SCL DEC
Mode
When the device is powered-up, the X9470 will load
the last saved value from the non-volatile memory into
the WCR. Note that the current wiper position can be
saved into non-volatile memory register by using the
SCL and CS pins as shown in Figure 4.
H
H
H
H
H
H
H
L
VBIAS is incremented
one tap position.
VBIAS is decremented
one tap position.
X
X
Lock Wiper Position.
Save to volatile
memory. (BiasLock™)
Important note: the factory setting of the wiper counter
register is the ZERO-position (0 of 255 taps). This is
the default wiper position.
or
X
X
L
Open Loop.
Bias Adjustment Block Instructions and Program-
ming. The SCL, INC/DEC (internal signal) and CS
inputs control the movement of the wiper along the
resistor array. (See Table 1) With CS set HIGH, the
device is selected and enabled to respond to the INC/
DEC and SCL inputs. HIGH to LOW transitions on SCL
* When coming out of shutdown, the CS pin must be cycled once before bias
adjustment is enabled.
will increment or decrement R
(depending on the
BIAS
state of the INC/DEC input). The INC/DEC input is
derived from the output of the comparator of the Sense
and Scale Block.
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Preliminary Information
X9470
Figure 3. Bias Adjustment Block Diagram
Gate Bias
Op Amp
–
V
BIAS
to LDMOS gate
V
(unbuffered)
2
BIAS
RW
+
BIAS
R
BIAS
RH
RL
BIAS
SHDN
10Kohm
256-tap
BIAS
XDCP
Memory and Control
INC/DEC is logic HIGH or LOW
from Sense/Scale Block
Legend
and is used to increment or
decrement the Rbias resistor
(XDCP) to adjust the gate voltage.
WCR (Rbias)
External pin/signal
Internal node/signal
Bias Register
non-volatile
3
Power On Recall
(POR)
1
INC/DEC
U/D
SCL
CS
INC
CS
Note:
1) WCR = Wiper Control Register
NON-VOLATILE STORE OF THE BIAS POSITION
did not rise up to the desired setting indicated by V
REF
while a logic LOW at the INC/DEC pin indicates that
the IDQ is higher than the desired setting.
The following procedure will store the values for the
Rref and Rbias wiper positions in Non-Volatile memory.
This sequence is intended to be performed after a
BiasLock calibration sequence to simplify storage. If
BiasLock has not been achieved, then the Rbias wiper
position may change when the CS pin is brought high
and SCL begins clocking. See Figure 4 for the actual
sequence.
INC/DEC is used as an internal control signal as well.
As an example, when INC/DEC is LOW, the Bias
Adjustment Circuit Block will start to move the Rbias
resistor wiper towards the RL
terminal end when
BIAS
CS is HIGH and SCL is clocking. Consequently, the
voltage will decrease, and the I decreases to
V
BIAS
DQ
meet the desired V
setting.
REF
1. Set the WEL bit with a write command (02h to regis-
ter 0Fh)
2. Peform a calibration and achieve BiasLock. Leave
CS pin high.
3. Write the address byte only (START, followed by
device/slave address and a 0 for a write, see page
20).
The INC/DEC signal can also be used to detect a dam-
aged RF power FET. For instance, If INC/DEC stays
HIGH during and after a calibration sequence it may
indicate that the RF power FET has failed. This indica-
tor can also be used with a level sense on the V
to perform diagnostics.
pin
OUT
4. Perform a STOP command.
5. With SCL still low, bring the CS low.The falling edge
of the CS will initiate the NV write.
SHUTDOWN MECHANISM
This hardware control shutdown pin (SHDN) will pull
the voltage of V to VSS with an internal pull down
BIAS
The WEL bit may be reset afterwards to prevent further
NV writes.
resistor. When shutdown is disabled (V
when SHDN is LOW), the V
is active
voltage will move to
BIAS
BIAS
the previous desired bias voltage.
INC/DEC FUNCTION
The INC/DEC pin is an open-drain logic output that
tracks the activity of the increment/decrement compar-
It will take less than a microsecond to enable the inter-
nal output buffer depending on the loading condition at
ator. A logic HIGH at INC/DEC indicates that the I
the V
pin.
DQ
BIAS
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Preliminary Information
X9470
OUTPUT (V
)
A single pole filter should be placed in between the
BIAS
V
output and the RF input signal to isolate any
BIAS
V
is a buffered output of RW
(wiper output). It
BIAS
BIAS
high frequency noise.
can deliver a high current for driving up to typically 1nF
capacitive loading with stable performance and fast
settling time.
Figure 4. Non-Volatile Store of the Bias Position
Calibration
Set
Stop
4
and Bias Lock Address Byte
Set WEL
bit
Initiates
high voltage write
cycle
CS
3
1
2
5
SCL
SDA
t
WR
R
non-volatile register
BIAS
Stored in
Non-volatile
memory
Non-volatile Write of R
and R
value Using SDA, SCL and CS pins
REF
BIAS
X9470 PRINCIPLES OF OPERATION
State 0: Monitor Mode
The V and INC/DEC outputs of the X9470 can be
The X9470 is a Bias Controller that contains all the
necessary analog components for closed-loop DC bias
control of LDMOS Transistors in RF Applications. The
X9470 provides a mechanism to periodically set DC
bias operating points of Class A or AB-type amplifiers
OUT
used for monitoring and diagnostic purposes. Since
has a lower gain (20x, default) than the internal IA
V
OUT
output, it can handle higher drain sense current while
keeping the output below the rail.This allows normal PA
power monitoring, and over-current sensing using an
external comparator. The INC/DEC pin can be moni-
tored during calibration to see if there is no change,
which indicates LDMOS functional problems. Note that
the INC/DEC status is also available in the status regis-
ter for software status reads.
to account for V
drift and temperature variations.
GS
The following is an example of X9470 operation.
The X9470 incorporates an instrumentation amplifier,
comparator and buffer amplifier along with resistor
arrays and their associated registers and counters.The
serial interface provides direct communication between
the host and the X9470. This section provides a
detailed example of how the X9470 can be used to cal-
ibrate and dynamically set the optimum bias operating
point of an RF power amplifier (see Figure 5):
State 1: DC-bias Setting When No RF is Present
[Calibration]
At calibration, the DC bias operating point of the
LDMOS Power Amplifier must be set. As soon as the
Bias Adjustment Circuit Block is enabled (CS enabled,
SDA high, and SCL pulse provided), the X9470 will
automatically calibrate the external Power Amplifier by
continually sampling the drain current of the external
Power Amplifier and make adjustments to the gate
voltage of the amplifier (See Figure 6).
– State 0: Power on Monitor Mode
– State 1: DC-bias Setting When No RF is Present
[Calibration]
– State 2: Calibration Disable When RF is Present
– State 3: PA Standby Mode. Dynamic Adjustment for
V
drift and Temperature variation
GS
– State 4: Power Off (Shutdown) Mode [Turn off the
Power Amplifier]
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Preliminary Information
X9470
Figure 5. Operating modes X9470
PA
State 0
State 1
State 2
PA Enabled, Vout and INC/DEC Monitored for status
Monitor Mode
PA
Choose Vref to scale IDQ, perform calibration,
Latch bias point for DC bias current in wiper counter
Calibration Mode
PA
Disable Bias Adjustment,
Transmit Mode
Recalibrate bias point for drift and temperature.
Rbias resistor will automatically increment or decrement
for optimal operating point continuously
PA
State 3
State 4
Standby Mode
PA
Off Mode
Turn off PA
When no RF signal is present, the instrumentation
amplifier of the X9470 senses the drain current as a
On edge transitions of the INC/DEC signal, the X9470 will
latch the current wiper position—this is known as “Bias
Lock™” mode. This is shown in Figure 6. When BiasLock
occurs, the comparator hysteresis will allow INC/DEC to
change state only after the IA output changes by more
voltage drop, ∆V, across an external drain R
resis-
sense
tor. The ∆V is amplified and compared to an external
scaling voltage, V . Any difference between ∆V and
REF
V
results in a resistive increment or decrement of
than 20mV. This will prevent toggling of the V
output
REF
BIAS
the internal R
potentiometer.
unless the drain bias current is constantly changing.
BIAS
The R
with the RH
potentiometer is used as a voltage divider
BIAS
State 2: DC-bias Disable When RF is Present
(optional)
and RL
terminals setting the
BIAS
BIAS
upper and lower voltage limits of the unbuffered
RW voltage. The resolution of the R potenti-
When an RF signal is present, the X9470 is put into
standby mode (open loop). The X9470 is in standby
mode when the CS pin is disabled so that the R
potentiometer holds the last wiper position. The pres-
ence of an RF signal at the input of a Class A or AB
BIAS
BIAS
ometer resistor is 0.4% of the difference of voltage
across the RH and RL terminals. The R
is typically 10KΩ with 256-taps. So, for example, if the
difference between the RH and RL terminals
BIAS
BIAS
BIAS
TOTAL
BIAS
BIAS
amplifier increases the current across the R
resis-
sense
is 1.024V, then the step accuracy is 4mV.
tor. Over a period of time, the temperature of the
LDMOS also increases and the LDMOS also experi-
The voltage at the RW
pin is then fed into the
BIAS
V
voltage follower. The V
pin is a buffered out-
ences V
drift. Therefore the DC biasing point that
BIAS
BIAS
GS
put that is used to drive the gate of an LDMOS transis-
tor.
was set during State 1 (calibration) is not optimal.
Adjustments to the gate voltage will need to be made
to optimize the operation of the LDMOS PA. This is
done in State 3.
The scaling voltage, V
eter, sets the calibrated operating point of the LDMOS
Amplifier.
, set by the R
potentiom-
REF
REF
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Preliminary Information
X9470
State 3: PA Standby Mode, DC Bias Adjustment
Figure 6 illustrates how the X9470 can be used for
dynamic biasing. Upon the presence of an RF signal,
the CS pin is pulled LOW. This will prevent the X9470
[Compensation for V
Variation]
Drift and Temperature
GS
from changing the V
rents. Once the RF signal is no longer present, the CS
pin can be enabled (closed loop), SDA high and the
voltage during I
peak cur-
BIAS
DQ
When the Power Amplifier is in Standby Mode the
X9470 allows for dynamic adjustment of the DC bias-
ing point to take into account both V
drift and tem-
GS
X9470 Bias Adjustment Circuit moves the V
volt-
BIAS
perature variation. Dynamic biasing is achieved with
the X9470 by using the CS, and SCL pins. For exam-
ple, the SCL pin can be a steady clock and the CS pin
can be used as a control signal to enable/disable the
Bias Adjustment Block.
age (the gate voltage of the FET) to meet the average
bias point for optimum amplifier performance.
I
DQ
State 4: Power Off Mode
During power saving or power-off modes the X9470
can be shut down via the SHDN pin. This pin pulls the
output of the V
pin LOW.
BIAS
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Preliminary Information
X9470
Figure 6. Dynamic Biasing Technique: Automatic DC Bias Operating Point Adjustment
State 3
State 0
Monitor
Mode
State 4
State 1
State 2
RF present
Recalibrate bias
point for drift
shut
Calibration
down
(no RF present)
and temperature
RF signal
Set Operating Range Scale for Bias Adjustment
V
REF
Bias Adjustment ON
Bias Adjustment ON
CS
Bias Adjustment OFF
SCL
Saves wiper position to
volatile memory
BiasLock
INC/DEC
BiasLock
SHDN
6
Shut
down
V
BIAS
3
4
5
RF present
Turn off
R
increase/decrease
bias
2
IDQ vs. gate
voltage bias
optimized
after RF present due to
R
default is
bias
Bias
Latch R
bias
DC point
temperature increase &
zero point of R
total
Adjustment
in calibration vs V
V
-threshold drift
REF
GS
1
Automatic Bias Adjustment
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Preliminary Information
X9470
X9470 STATUS REGISTER (SR) AND CONTROL REGISTER (CR) INFORMATION
Table 2. Status Register (SR)
Byte
Addr
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
0F hex
SHDN
INC/DEC
0
CS
0
0
WEL
Gain
STATUS REGISTER (SR)
SR1: WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the registers during
a write operation. This bit is a volatile latch that powers
up in the LOW (disabled) state. While the WEL bit is
set LOW, Nonvolatile writes to the registers will be
ignored, and all writes to registers will be volatile. The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the Status Register. Once
this write operation is completed and a STOP com-
mand is issued, nonvolatile writes will then occur for all
NOVRAM registers and control bits. Once set, the,
WEL bit remains set until either reset to 0 (by writing a
“0” to the WEL bit and zeroes to the other bits of the
Status Register) or until the part powers up again.
The Status Register is located at address 0F<hex>.
This is a register used to control the write enable
latches, and monitor status of the SHDN, INC/DEC,
and CS pin. This register is separate from the Control
Register.
SR7: SHDN:Vbias SHDN Flag. Read Only—Volatile.
The bit keeps status of the shutdown pin, SHDN. When
this bit is HIGH, the SHDN pin is active and the V
BIAS
output is disabled. When this bit is LOW, the SHDN pin
is low and V
output is enabled.
BIAS
SR6: INC/DEC : Read Only—Volatile. This bit keeps
status of the INC/DEC pin. When this bit is HIGH the
counter is in increment mode, when this bit is LOW the
counter is in decrement mode.
SR0: Gain - NOVRAM
Selects V
and IA gain.When SR0=0, V
gain=20x,
OUT
OUT
SR4: CS: Read Only—Volatile. This bit keeps status
on the CS pin. When this bit is HIGH, the X9470 is in
closed loop mode (Rbias adjustment enabled). When
this bit is LOW the x9470 is in open loop mode (no
Rbias adjustments).
IA gain=50x. When SR0=1, V
gain=20x. Default setting is 0.
gain=50x, and IA
OUT
CONTROL REGISTERS (CR)
The control registers are organized for byte operations.
Each byte has a unique byte address as shown in
Table 3 below.
SR2, SR3, SR5: Read only
For internal test usage, should be set to 0 during SR
writes.
Table 3. Control Registers (CR)
Byte
Bit
Addr.
Reg
<HEX> Description Name
7
Vb7
X
6
Vb6
X
5
4
3
2
1
0
Memory Type
NOVRAM
00 hex DCP for Vbias Vbias
Vb5
Vr5
Vb4
Vr4
Vb3 Vb2 Vb1
Vr3 Vr2 Vr1
Vb0
Vr0
01 hex
DCP for
VREF
Vref
NOVRAM
Note: 02H to 0EH are reserved for internal manufacturing use.
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Preliminary Information
X9470
X9470 BUS INTERFACE INFORMATION
Figure 7. Slave Address, Word Address, and Data Bytes - Write Mode
Slave Address
Device Identifier
Slave Address Byte
R/W=0
A0
S2
A3
D3
S1
S0
0
1
0
1
Byte 0
0Fh : SR
Byte Address
A7
D7
A6
D6
A5
D5
A4
D4
A2
A1
D1
00h : V
01h : V
Byte 1
BIAS
REF
Data Byte
D2
D0
Byte 2
Figure 8. Slave Address, Word Address, and Data Bytes - Read Mode
Slave Address
Device Identifier
Slave Address Byte
R/W
D0
S2
D3
D3
S1
S0
0
1
0
1
Byte 0
Data Byte
D7
D7
D6
D6
D5
D5
D4
D4
D2
D1
D1
Byte 1
Data Byte
D2
D0
Byte 2
Slave Address, Byte Address, and Data Byte
Start Condition
The byte communication format for the serial bus is
shown in Figures 7 and 8 above. The first byte, BYTE
0, defines the device indentifier, 0101 in the upper half;
and the device slave address in the low half of the byte.
The slave address is determined by the logic values of
the A0, A1, and A2 pins of the X9470. This allows for
up to 8 unique addresses for the X9470. The next byte,
BYTE 1, is the Byte Address. The Byte Address identi-
fies a unique address for the Status or Control Regis-
ters as shown in Table 3. The following byte, Byte 2, is
the data byte that is used for READ and WRITE opera-
tions.
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 9.
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Preliminary Information
X9470
Stop Condition
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 9.
Acknowledge
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 10.
– The 2nd Data Byte of a Status Register Write Opera-
tion (only 1 data byte is allowed)
Figure 9. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Figure 10. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Figure 11. Valid Data Changes on the SDA Bus
SCL
Acknowledge
SDA
Data Change
Data Stable
Data Stable
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Preliminary Information
X9470
WRITE OPERATIONS
Byte Write
X9470 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X9470 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X9470 has com-
pleted the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 15.
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array.
Upon receipt of each address byte, the X9470
responds with an acknowledge. After receiving the
address bytes the X9470 awaits the eight bits of data.
After receiving the 8 data bits, the X9470 again
responds with an acknowledge. The master then termi-
nates the transfer by generating a stop condition. The
X9470 then begins an internal write cycle of the data to
the nonvolatile memory. During the internal write cycle,
the device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 12.
READ OPERATIONS
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X9470 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address is initial-
ized to 0h. In this way, a current address read immedi-
ately after the power on reset can download the entire
contents of memory starting at the first location. Upon
receipt of the Slave Address Byte with the R/W bit set
to one, the X9470 issues an acknowledge, then trans-
mits eight data bits. The master terminates the read
operation by not responding with an acknowledge dur-
ing the ninth clock and issuing a stop condition. Refer
to Figure 13 for the address, acknowledge, and data
transfer sequence.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the write
command, the X9470 will not initiate an internal write
cycle, and will continue to ACK commands.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X9470 resets itself without per-
forming the write. The contents of the array are not
affected.
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
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Preliminary Information
X9470
Figure 12. Byte Write Sequence
S
t
S
t
o
p
Slave
Address
Device
ID
Signals from
the Master
a
r
Byte
Address 0
Data
t
SDA Bus
1 0 1 A2
A0
0
A1
0
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Figure 13. Current Address Read Sequence
S
S
t
o
p
Slave
Address
Device
ID
t
a
r
Signals from the
Master
t
SDA Bus
1 0 1 A2
A0
0
A1
1
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 14. Random Address Read Sequence
S
S
S
t
o
p
Signals from the
Master
t
a
r
Slave
Address
Device
ID
t
a
r
Byte
Address 0
Slave
Address
Device
ID
t
t
SDA Bus
1 0 1
0
1 0 1 A2
A2
A0 0
0
A1 1
A0
A1
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
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Preliminary Information
X9470
Figure 15. Acknowledge Polling Sequence
Random Read
Random read operations allows the master to access
any location in the X9470. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
Byte load completed
by issuing STOP.
Enter ACK Polling
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt of
each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issu-
ing a stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
Issue START
Issue Slave
Address Byte
(Read or Write)
Issue STOP
NO
ACK
returned?
YES
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 14. The X9470 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
nonvolatile write
Cycle complete.
Continue command
sequence?
NO
Issue STOP
YES
Continue normal
Read or Write
command
sequence
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
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Preliminary Information
X9470
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.002 (.06)
.0118 (.30)
.005 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.020 (.50)
.030 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
©Xicor, Inc. 2003 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, BiasLock and XDCP are also trademarks of
Xicor, Inc. All others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 25 of 25
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