X9470V24I [INTERSIL]
RF Power Amplifier (PA) Bias Controller; 射频功率放大器（ PA）偏置控制器
| 型号： | X9470V24I |
| 厂家： | 
Intersil |
| 描述： | RF Power Amplifier (PA) Bias Controller |
| 文件： | 总24页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9470
®
Data Sheet
March 8, 2005
FN8204.0
PRELIMINARY
DESCRIPTION
RF Power Amplifier (PA) Bias Controller
The Intersil X9470 RF PA Bias Controller contains all of
the necessary analog components to sense the PA
drain current through an external sense resistor and
automatically control the gate bias voltage of an
LDMOS PA. The external sense resistor voltage is am-
plified by an instrumentation amplifier and the output of
the amplifier along with an external reference voltage is
fed to the inputs of a comparator. The comparator out-
put indicates which direction the LDMOS gate bias volt-
age will move in the next calibration cycle. System
calibration is accomplished by enabling the X9470 and
providing a clock to the SCL pin. The LDMOS drain cur-
rent can be maintained constant over temperature and
aging changes by periodic calibration. The VOUT pin
can be used to monitor the average power by tracking
the drain current. Up to eight X9470 or additional Inter-
sil Digital Potentiometers can be controlled via a two-
wire serial bus.
FEATURES
• Programmable Bias Controller IC for Class A
and AB LDMOS Power Amplifiers
• Adaptive System on Chip Solution
• Bias Current Calibration to better than ±4%
using Reference Trim DCP
• Automatic Bias Point Tracking and Calibration
— I Sensing and Tracking
DQ
—Programmable Instrumentation Amplifier to
Scale Wide Range of I
—Programmable Gate Bias Driver
—All Programmable settings are Nonvolatile
—All Settings Recalled at Power-up.
• 28V Maximum V
• 2 Wire Interface for Programming Bias Setting
and Optimizing I Set Point
DQ
DD
DQ
• Bias Level Comparator
• Shutdown Control pin for PA Signal
• Slave address to allow for multiple devices
• 24-pin TSSOP Package
• Applications: Cellular Base Stations (GSM,
UMTS, CDMA, EDGE), TDD applications, Point-
to-multipoint, and other RF power transmission
systems
TYPICAL APPLICATION
VDD
RWREF RHREF RLREF
INC/DEC
V+
AGND
VOUT
VSENSE+
CBULK
RSENSE
A2
RREF
VREF
A1
∆V
VSENSE–
Comparator
Instrumentation
Amplifier
A0
VP
SDA
SCL
choke
VREF
control
I2C
interface
RBIAS
Vbias
control
VBIAS
+
–
FILTER
RF
out
Control &
Status Registers
RF PA in
Matching
RF Impedance
EEPROM
Class A Example
VCC
VSS
CS
RHBIAS RWBIAS RLBIAS SHDN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X9470
PIN CONFIGURATION
TSSOP
Vsense-
Vsense+
24
23
22
1
2
3
4
5
6
SHDN
INC/DEC
VOUT
V+
RHREF
RLREF
21
20
19
18
17
16
RWREF
AGND
X9470
VSS
CS
SCL
VCC
VCC
7
8
VBIAS
VSS
SDA
9
RHBIAS
RWBIAS
A2
10
11
12
15
14
13
A1
A0
RLBIAS
ORDERING INFORMATION
Part Number
Temperature Range
Package
X9470V24I
-40°C TO 85°C
24-Lead TSSOP
PIN DESCRIPTIONS
TSSOP pin Symbol
Brief Description
Positive sense voltage input terminal
1
2
VSENSE+
RHREF
Upper Terminal of Potentiometer, called the RREF potentiometer. The voltage applied to this pin will determine
the upper voltage limit of the adjustment for the Up/Down threshold of the comparator.
Lower Terminal of Potentiometer, called the RREF potentiometer. The voltage applied to this pin will determine
the lower voltage limit of the adjustment for the Up/Down threshold of the comparator.
3
4
RLREF
Wiper Terminal of Potentiometer, called the RREF potentiometer. The voltage on this pin will be the threshold
for the Up/Down comparator. Also referred to as the VREF of the comparator.
RWREF
Analog ground to allow single point grounding external to the package to minimize digital noise.
System (Digital) Ground Reference
5
6
7
AGND
VSS
CS
Chip Select. This input enables bias calibration adjustments to the RBIAS potentiometer. CMOS input with in-
ternal pull-down.
Dual function. Function 1: The increment control input. Increments or decrements the RBIAS potentiometer.
Function 2: Serial Data Clock Input. Requires external pull-up.
8
SCL
Serial Data Input. Bi-directional 2-wire interface. Requires external pull-up.
9
SDA
Upper Terminal of Potentiometer, called the RBIAS potentiometer. The voltage applied to this pin will determine
the upper limit of the bias voltage to the PA (or VBIAS pin).
10
RHBIAS
Wiper Terminal of Potentiometer, called the RBIAS potentiometer. This voltage is the equivalent to the unbuf-
fered voltage that will appear at the VBIAS pin.
11
12
RWBIAS
RLBIAS
Lower Terminal of Potentiometer, called the RBIAS potentiometer. The voltage applied to this pin will determine
the lower limit of the bias voltage to the PA (or VBIAS pin).
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
13
14
15
A0
A1
A2
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
External address pin which allows for a hardware slave address selection of this device.
This pin has an internal pull-down.
System (Digital) Ground Reference
16
17
18
19
20
21
22
VSS
This is the bias output voltage pin and is used to drive the filter network to the PA gate.
System (Digital) Supply Voltage
VBIAS
VCC
System (Digital) Supply Voltage
VCC
Positive voltage supply for the instrumentation amplifier and other analog circuits.
Instrumentation Amplifier output that is 20x or 50x the voltage across the Rsense pins.
V +
VOUT
INC/DEC
Status output that indicates the state of the comparator. When this pin is HIGH, the RBIAS potentiometer
will increment; when the pin is LOW, the RBIAS potentiometer will decrement. This pin is open drain and
requires external resistor pull-up.
Shutdown the output op amp. When SHDN is active (HIGH), the VBIAS pin is pulled LOW.
Negative sense voltage Input terminal
23
24
SHDN
VSENSE-
FN8204.0
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March 8, 2005
X9470
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those listed in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
Voltage on V+ (referenced to AGND)......................7V
Voltage on VCC (reference to VSS) ........................7V
Voltage on all RH, RW, RL pins
(reference to AGND): ...........................................7V
Voltage on Vsense+ or
Vsense- (reference to AGRND)..........................30V
Voltage on SDA, CS, SCL, SHDN
(reference to AGND) ............... -0.3V to (Vcc + 0.3V)
Current into Output Pin:.......................................... ±5mA
Continuous Power Dissipation: .......................500mW
Operating Temperature range:.............. -40°C to +85°C
Junction Temperature: ..........................................150°C
Storage Temperature ........................ -65°C to +150°C
Lead Temperature (Soldering, 10 seconds):..... 300°C
ELECTRICAL CHARACTERISTICS
INSTRUMENTATION AMPLIFIER
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
Min. Typ. Max. Units
Test Conditions/Notes
(10)
VIN
Common Mode Input Voltage on
VSENSE+ and VSENSE- pins
20
28
V
(2)
Gain 1
Gain 2
VRANGE1
VRANGE2
VOS
Gain from VSENSE to VOUT
20
50
V/V Measured with Status
Register bit SR0 = 0
(2)
Gain from VSENSE to VOUT
V/V Measured with Status
Register bit SR0 = 1
Differential voltage sense range between
VSENSE+ and VSENSE- for gain 1
60
90
60
mV Gain = 20
Differential voltage sense range between
VSENSE+ and VSENSE- for gain 2
40
mV Gain = 50
Input Offset Voltage
0.5
1.5
mV VSENSE = 40mV to 90mV
TA = 25°C
Av1
Gain 1 Error
Gain = 20 (4)
%
VSENSE = 60mV to 90mV
TA = 25 to 85°C, Gain = 20
Av2
Gain 2 Error
Gain = 50 (4)
1.5
%
VSENSE = 40mV to 60mV
TA = 25 to 85°C, Gain = 50
Avt1
Total Error, Gain 1
Gain = 20 (5)
-6
-6
1.5
10
6
6
%
%
%
%
%
VSENSE = 60mV to 90mV
TA = 85°C, Gain = 20
VSENSE = 60mV to 90mV
TA = 25 to 85°C, Gain = 20
Avt2
Total Error, Gain 2
Gain = 50 (5)
1.5
10
VSENSE = 40mV to 60mV
TA = 85°C, Gain = 50
VSENSE = 40mV to 60mV
TA = 25 to 85°C, Gain = 50
At
Long Term Drift
2
Avt1 or Avt2
SR(10)
Slew Rate of Instrumentation Amp
0.2
V/µS ∆VSENSE = 20mV step,
Cout = 10pF Measured at
(1,3)
VOUT
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X9470
ELECTRICAL CHARACTERISTICS
INSTRUMENTATION AMPLIFIER (CONTINUED)
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
Min. Typ. Max. Units
Test Conditions/Notes
(10)
Tsettle
Setting time of Instrumentation Amp
5.0
µS
∆VSENSE = 20mV step, Cout =
10pF, settling to 1% of final value
(1,3)
Measured at VOUT
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
40
55
dB
dB
V
For both Gain 1 and Gain 2
For both Gain 1 and Gain 2
Gain = 20
V
OUT Range VOUT Voltage Swing
0.3
0.3
1.8
3.0
V
Gain = 50
VOUT
Noise(10)
VOUT Voltage Noise, rms
3
mV Gain = 20
(10)
IVSENSE
VSENSE+, VSENSE- Input Bias
Current
250
10
µA
pF
TA = 25°C
Each Input
(10)
CVSENSE
VSENSE+, VSENSE- Input
Capacitance
COMPARATOR
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
VOL
Io(10)
Parameter
Output Voltage Low on the INC/DEC pin
Output sink Current
Min. Typ. Max. Units
Test Conditions/Notes
IOL = 1mA
0.4
3
V
mA
mV
µS
INC/DEC pin, open drain
Vcc = 5 V
Vos(10) Input Hysteresis
Tpd(10) Response Time for propagation delay
20
2
INC/DEC pin with 2kΩ pull up
VREF DCP CIRCUIT BLOCK
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
Min.
Typ.
Max. Units
Test Conditions/Notes
RTOTAL End to End Resistance
Number Taps or Positions
8
10
12
64
V+
V+
V+
kΩ
VRH
VRL
RHREF Terminal Voltage
RLREF Terminal Voltage
RWREF Terminal Voltage
Power Rating(10)
AGND
AGND
AGND
V
V
AGND = 0V
AGND = 0V
AGND = 0V
VRW
V
2.5
1.6
mW
%
RTOTAL =10kΩ
Resolution(10)
Absolute Linearity(6)
Relative Linearity(7)
-0.2
-0.2
+0.2
+0.2
MI(8)
MI(8)
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X9470
VREF DCP CIRCUIT BLOCK
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
Min.
Typ.
Max. Units
ppm/°C
Test Conditions/Notes
RTOTAL Temperature Coefficient(10)
Ratiometric Temperature Coefficient(10)
±300
-20
+20 ppm/°C
pF
(10)
CIN
Potentiometer Capacitances on RHREF
and RLREF
10
BIAS ADJUSTMENT DCP CIRCUIT BLOCK
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
Min.
Typ.
Max. Units
Test Conditions/Notes
RTOTAL End to End Resistance Variation
Number Taps or Positions
8
10
12
256
V+
kΩ
with ±20% variation
VRH
VRL
Voltage at the RHBIAS Terminal Voltage
Voltage at the RLBIAS Terminal Voltage
Voltage at the RWBIAS Terminal Voltage
Power Rating(10)
AGND
AGND
AGND
V
V
AGND = 0V
AGND = 0V
AGND = 0V
V+
VRW
V+
V
2.5
0.4
mW
RTOTAL =10 KΩ
Resolution(10)
%
Absolute Linearity(6)
Relative Linearity(7)
RTOTAL Temperature Coefficient(10)
Ratiometric Temperature Coefficient(10)
-1.0
-1.0
+1.0
+1.0
MI(8)
MI(8)
ppm/°C
ppm/°C
pF
±300
10
-50
50
(10)
CIN
Potentiometer Capacitances on RHBIAS
and RLBIAS
VBIAS OUTPUT VOLTAGE FOLLOWER
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
Min.
Typ.
10
Max.
Units
Test Conditions/Notes
VOS
Input Offset Voltage
mV
(10)
VOSDRIFT
Offset Voltage Temperature
Coefficient
10
µV/°C TA = -40 to +85°C
SR
Output Slew Rate on V
0.5
2
V/µS
RL = 10kΩ, 1nF, ∆VBIAS =
20mV
BIAS
VBIAS
Voltage Output Swing
Settling Time
1.5
45
VCC - 0.5
V
IOUT = ±10mA
(10)
TS
µs
Final value ±1%, RL = 10kΩ,
1nF, ∆VBIAS = 20mV
t
Time for SHDN pin (delay) valid
Power Supply Rejection Ratio
0.1
55
1.0
µs
SHDN
PSRR
dB
VCC supply VCC = 4.75 to
5.25V
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March 8, 2005
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X9470
VBIAS OUTPUT VOLTAGE FOLLOWER
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
Input Voltage Range
Load Capacitance
Min.
Typ.
Max.
Units
V
Test Conditions/Notes
1.5
VCC - 0.5
(10)
CL
1
10
3
nF
pF
Ω
(10)
CIN
Capacitances on Shutdown Pin
Output Impedance
(10)
ROUT
at 5MHz, 1nF load
D.C. OPERATING CHARACTERISTICS
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
Symbol
Parameter
V+ Active Current
Min.
Typ.
Max.
3
Units
mA
Test Conditions
(9)
ICC1
1
5
CS = VCC - 0.3V, and SCL
@ max. tCYC, SDA = VCC
0.3V, SHDN inactive
-
(9)(10)
ICC2
VCC Active Current
25
mA
(9)
ISB
Standby Supply Current
(VCC, V+)
1.5
mA
CS = VIL, and SCL inactive
(no clock), SDA =VIL, SHDN
active
ILI
CS, SDA, SCL, SHDN RH, RL, RW,
INC/DEC VOUT, Input Leakage
-10
10
µA
V
VIN = VSS to VCC
(10)
VIH
CS, SDA, SCL, SHDN, A0, A1, A2
HIGH Voltage
VCC x 0.7
VCC + 0.5
(10)
VIL
CS, SDA, SCL, SHDN, A0, A1, A2
LOW Voltage
-0.5
VCC x 0.3
V
(10)
CIN
CS, SDA, SCL, SHDN, A0, A1, A2
Capacitance
10
pF
VCC = 5V, VIN = VSS,
TA = 25°C, f = 1MHz
Notes: (1) VOUT is a high impedance output intended for light loads only.
(2) Gain at VOUT is set to 20 by default.
(3) Value given is for VOUT. The VBIAS output will depend on the VBIAS potentiometer which is initially loaded with a zero value, then fol-
lowed by the loading of the final value from E2 memory.
(4) Gain Error excludes the contribution of the input offset voltage error.
(5) Total Error includes the contributions of gain error and input offset voltage error.
(6) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage = (V
(actual) - V
(expected))
w(n)
w(n)
(7) Relative Linearity is a measure of the error in step size between taps = V
[V
+ Ml]
W(n+1) - w(n)
(8) 1 Ml = Minimum Increment = R /63 or R /255.
TOT TOT
(9) Typical values are for TA = 25°C and nominal supply voltage, VCC = 5V.
(10) This parameter is not 100% tested.
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X9470
BIAS ADJUSTMENT CIRCUIT BLOCK
A.C. OPERATING CHARACTERISTICS
Recommended Operating Conditions: (Vcc, V+ = 4.75 to 5.25V; Vsense+, Vsense- = 26V; T = -40°C to +85°C, unless
A
otherwise noted.)
Limits
(9)
Symbol
Parameter
CS to SCL Setup
Min.
Typ.
Max.
Units
ns
tCl
tlD
tlL
100
Vsense Change to INC/DEC Change
SCL LOW Period
5
µs
1.5
1.5
µs
tlH
SCL HIGH Period
µs
(10)
tlC
SCL Inactive to CS Inactive
100
ns
(10)(11)
tIW
SCL to V
Change
3
µs
BIAS
tCYC
SCL Cycle Time
3
µs
(10)
tR
t
SCL Input Rise and Fall Time
500
ns
,
F
A.C. TIMING
CS
tCYC
tCI
tIL
tIH
tIC
90%
90%
SCL
10%
tID
tF
tR
INC/DEC
tIW
VBIAS
(Vsense+ –
Vsense-)
Note: (11) MI in the A.C. timing diagram refers to the minimum incremental change in the VBIAS output due to a change in the wiper position.
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X9470
AC SPECIFICATIONS
Symbol
Parameter
Min.
0
Max. Unit
fSCL
SCL Clock Frequency
400
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
ns
ns
pF
(10)
tIN
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
50
(10)
(10)
tAA
0.1
1.3
1.3
0.6
0.6
0.6
200
200
0.6
50
0.9
tBUF
tLOW
tHIGH
Clock HIGH Time
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
(10)
tDH
(10)
tR
SDA and SCL Rise Time
20 +.1Cb(12) 300
20 +.1Cb(12) 300
400
(10)
tF
SDA and SCL Fall Time
Cb(10)
Capacitive load for each bus line
Note: (12) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
SDA IN
tSU:DAT
tSU:ST
tHD:DAT
tSU:STO
tHD:STA
tAA
tDH
tBUF
SDA OUT
Write Cycle Timing
SCL
8th Bit of Last Byte
ACK
SDA
tWC
Stop
Condition
Start
Condition
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March 8, 2005
X9470
Power-up Timing
Symbol
Parameter
Min.
Max.
Unit
(10)
tr VCC
VCC Power-up rate
0.2
50
V/ms
Note: Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100% tested.
Proper recall of stored wiper setting requires a VCC power-up ramp that is monotonic and with noise or glitches < 100mV. It is important to
correctly sequence voltages in an LDMOS amplifier circuit. For the X9470 typical application, the VCC, then V+ pins should be powered
before the VDD of the LDMOS to prevent LDMOS damage. Under no circumstances should the VDD be applied to the LDMOS device
before VCC and V+ are applied to the X9470.
DCP Default Power-up Tap Positions (shipped from factory)
VREF DCP
0
0
Bias Adjust DCP
Nonvolatile Write Cycle Timing
Symbol
(1)
Parameter
Write Cycle Time
Min.
Typ.
Max.
Unit
(10)
tWC
5
10
ms
Note: tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8204.0
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March 8, 2005
X9470
DETAILED PIN DESCRIPTIONS
Supply Pins
When CS is LOW (disabled), the wiper counter of the
XDCP will hold the last wiper position until CS is
enabled again and the wiper position is updated.
Digital Supplies VCC, VSS
The positive power supply and ground for the DCP
digital control sections. VSS is normally tied to digital
ground. The X9470 is provided with separate digital
and analog power supply pins to better isolate digital
noise from the analog section.
INC/DEC Monitor Pin
The Up or Down Monitor pin (INC/DEC) indicates the
state of the comparator. This signal indicates that the
Instrumentation Amplifier output voltage is higher or
lower than the voltage level set by the RW
pin. The
REF
Analog Supplies V+, AGND
output is used to indicate the direction that the gate
bias voltage needs to move to reach the target bias
voltage.
The positive analog supply and ground for the Instru-
mentation Amplifier (IA). The analog supply ground is
kept separate to allow an external single point connec-
tion. V+ can be a separate supply voltage from VCC, or
VCC can be filtered before connection to V+.
Sense and Scale Block Pins
V
and V
SENSE-
SENSE+
Bias Adjustment Circuit Block Pins
These are the input pins to the IA circuit. These pins
are used to determine the change in voltage across
the the external drain sense resistor of an RF power
amplifier.
RH
, RL
, and RW
for VBIAS Adjust-
BIAS
BIAS
BIAS
ments.
These pins are the connections to a Intersil Digitally
Controlled Potentiometer (XDCP™) or R potenti-
RH
, RL
, and RW
. PA Bias Set Point.
REF
REF
REF
BIAS
ometer. RH
erence, and the RL
is connected to the most positive ref-
The PA Bias reference voltage is controlled by a 64-
tap (10kΩ typical R ) potentiometer, called the
BIAS
is connected to the least
BIAS
TOTAL
positive reference voltage. The potentiometer has a
resolution of 256-taps and typical R of 10kΩ. So
R
potentiometer. The voltages applied to RH
will determine the range of adjustment of
REF
REF REF
and RL
TOTAL
for example, to provide 4mV resolution, the voltage dif-
ference applied to the RH and RL pins must
the reference voltage level (VREF) for the Compara-
tor. The resolution of the comparator reference is the
BIAS
BIAS
be 1.024V. The RW
value can be stored in non-
difference of the voltages applied to RH
and RL
BIAS
REF REF
volatile memory and recalled upon power-up.
divided by 63. The position of the wiper (RW
) is
REF
controlled via serial bus. The RW
value can be
REF
Serial Clock (SCL).
stored in non-volatile memory and recalled upon
power-up.
This is a dual function input pin. The state of the CS
pin determines the functionality.
RW
is also an input signal used as a scaling volt-
REF
age (VREF) to set the appropriate I of an RF power
DQ
Function 1: SCL is a negative edge-triggered control
amplifier. V
can be derived from an external volt-
REF
pin of the R
potentiometer. Toggling SCL will
BIAS
age divider or from a baseband processor or similar
microcontroller. V can be set permanently or
either increment or decrement the wiper in the
direction indicated by the logic level on the INC/DEC
pin. CS must be high for this function.
REF
changed dynamically using the potentiometer for vari-
ous PA operating points.
Function 2: SCL is the serial bus clock for serial bus
interface. CS must be low for this function.
V
OUT
This pin is the output of the IA, which reflects a 20x or
50x gain of the input signal (voltage across the Vsense
pins). It can be used to indicate the magnitude of the
drain current envelope when RF is present.
Chip Select (CS). Calibration Enable.
The CS input is the enable bias adjustments. When
the CS is HIGH (enabled) and a SCL pulse is present,
the wiper position on the R
potentiometer will
BIAS
automatically update with either an increment or dec-
rement of one tap position according to INC/DEC sig-
nal from the comparator.
FN8204.0
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X9470
Output Block Pins
TYPICAL APPLICATION
The X9470 can be used along with a microprocessor
and transmit control chips to control and coordinate
FET biasing (see Figure 1). The CS, SCL, and SDA sig-
nals are required to control the X9470 Bias Adjustment
V
BIAS
The V
is the gate bias voltage output. It is buffered
BIAS
with a unity gain amplifier and is capable of driving 1nF
(typical) capacitive loads.
Circuit Block. An internal R
voltage is provided via
WREF
a programmable voltage divider between the RH
REF
This pin is intended to be connected through an RF fil-
ter to the gate of an LDMOS power transistor. The
and RL
pins and is used to set the voltage reference
REF
of the comparator. The shutdown (SHDN) and bias volt-
age indicators (INC/DEC) are additional functions that
offer FET control, monitoring, and protection.
voltage of V
is determined by the XDCP’s value of
BIAS
the R
resistor.
BIAS
Other Pins
Typically, the closed loop setup of the X9470 allows for
final calibration of a power amplifier at production test.
The CS and SCL pins are used to perform this calibra-
tion function. Once in a base station, the amplifier can
then be re-calibrated any time that there is no RF signal
present. The bias setting block can also be used open
loop to adjust gate bias or can be shutdown using the
SHDN pin. The sense and scale block can be used for
amplifier power monitoring diagnostics as well.
SHDN
SHDN is an input pin that is used to shutdown the
V
output voltage follower. When the SHDN pin is
BIAS
HIGH, the V
is shutdown, the current R
pin is pulled to VSS. When the device
BIAS
wiper position will be
BIAS
maintained in the wiper counter register. When shut-
down is disabled, the wiper returns to the same wiper
position before shutdown was invoked. Note that when
the device is taken out of shutdown mode (SHDN
goes from HIGH to LOW), the CS input must be cycled
once to enable calibration.
The range of the drain bias current operating point of
the LDMOS FET is set by an external reference
across the reference potentiometer. The wiper of the
potentiometer sets the trip point for comparison with
V , the amplified voltage across R
, the drain
P
SENSE
SDA
resistor. The output of the comparator causes the
potentiometer to increment or decrement auto-
Serial bus data input/output. Bi-directional. External
pullup is required.
R
BIAS
matically on the next SCL clock cycle. This R
BIAS
potentiometer is configured as a voltage divider with a
buffered wiper output which drives the gate voltage of
an external LDMOS FET.
A0, A1, A2
Serial bus slave address pins. These pins are used to
defined a hardware slave address. This will allow up to
8 of the X9470’s to be shared on one two-wire bus.
These are useful if several X9470’s are used to control
the bias voltages of several LDMOS Power Transis-
tors in a single application. Default hardware slave
address is “000” if left unconnected due to internal
pull-down resistor.
Once the optimum bias point is reached, the R
BIAS
value is latched into a wiper counter register. Again,
the V gate voltage can be updated continuously or
BIAS
periodically depending on the system requirements.
Both terminals of the R potentiometer are access-
BIAS
ible and can be driven by external reference voltages to
achieve a desired I vs. gate voltage resolution, as
DQ
well as supporting temperature compensation circuitry.
In summary, the X9470 provides full flexibility on set-
ting the operating bias point and range of an external
RF power amplifier for GSM, EDGE, UMTS, CDMA or
other similar applications.
FN8204.0
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March 8, 2005
X9470
Figure 1. Typical Application
VDD
VSENSE+
RWREF RHREF RLREF
V+
AGND
VOUT
INC/DEC
CBULK
A2
A1
RREF
VREF
∆V
RSENSE
VSENSE–
Comparator
Instrumentation
Amplifier
A0
VP
SDA
I2C
choke
VREF
control
interface
SCL
RBIAS
Vbias
control
VBIAS
+
–
FILTER
RF
out
Control &
Status Registers
RF PA in
Matching
RF Impedance
EEPROM
Class A Example
VCC
VSS
CS
RHBIAS RWBIAS RLBIAS SHDN
X9470 FUNCTIONAL DESCRIPTION
The output of the IA is also available at the pin Vout to
enable drain current monitoring. The gain at Vout is
This section provides detail description of the following:
fixed at a factor of K , lower than K so that high I
2
1
DQ
currents will not cause saturation of the Vout signal.
The equation for Vout is given as:
– Sense and Scale Block Description
– Bias Adjustment Control Block Description
– Output Block Description
∆V = I * R
DQ
SENSE
V
= K * ∆V
2
OUT
– Bias Adjustment and Storage Description
K is fixed to 20x for the Vout pin
2
SENSE AND SCALE BLOCK
The Sense and Scale Circuit Block (Figure 2) imple-
ments an instrumentation amplifier whose inputs
BIAS ADJUSTMENT CIRCUIT BLOCK
There are three sections of this block (Figure 3): the
input control, counter and decode section (1), the
resistor array (2); and the non-volatile register (3). The
input control section operates just like an up/down
counter. The input of the counter is driven from the
output of the comparator in the Sense and Scale Block
and is clocked by the SCL signal. The output of this
counter is decoded to select one of the taps of a 256-
tap digital potentiometer.
(V
and V
) are across an external sense
SENSE+
SENSE-
resistor in the drain circuit of an RF Power FET. V
SENSE+
is connected to V , the drain voltage source for the RF
DD
power FET, and V
pin is connected to the other
SENSE-
end the external sense resistor.
An internal instrumentation amplifier (IA) will sense the
∆V and amplify it by a gain factor of K (see Equation
1
1). The resulting output is compared with V
at the
REF
comparator. V
can be a fixed reference voltage or
REF
adjusted by using the 64-tap digital potentiometer. The
output of the comparator is used to increment or dec-
rement the R
potentiometer in the Bias Adjust-
BIAS
ment Circuit Block. The gain factor K is designed
1
such that the Sense and Scale Block will set the Bias
Adjustment Circuit Block to operate in a given voltage
range (mV) vs. drain current adjustment (mA).
V
REF
I
≅
(1)
DQ
K * R
1
SENSE
K is fixed 50x for the internal comparator input.
1
FN8204.0
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March 8, 2005
X9470
Figure 2. Sense and Scale Block Diagram
VDD
RSENSE
VSENSE+
VSENSE–
VOUT
INC/DEC
RWREF RHREF RLREF
IDQ
Cint~2pF ±10%
∆V
10kΩ
64-tap
K2 = 20X
~1kΩ
RF
VREF
PA
choke
Out
Precision
I-Amp
Comparator
INC/DEC
K1 = 50X
Vgate
RF PA in
The wiper of the digital potentiometer acts like its
mechanical equivalent and does not move beyond the
last position. That is, the counter does not wrap
around when clocked to either extreme. The electronic
switches in the potentiometer operate in a “make
before break” mode when the wiper changes tap posi-
tions. If the wiper is moved several positions, multiple
Storing Bias Resistor Values in Memory. Wiper val-
ues are stored to VOLATILE memory automatically
when CS is HIGH and INC/DEC either transitions from
HIGH to LOW or from LOW to HIGH. Wiper values are
stored to NON-VOLATILE memory during Byte Write
or as described in the following section.
taps are connected to the wiper for t
(SCL to
Table 1. Mode Selection
INC /
IW
RW
change).
BIAS
SDA CS* SCL DEC
Mode
When the device is powered-up, the X9470 will load
the last saved value from the non-volatile memory into
the WCR. Note that the current wiper position can be
saved into non-volatile memory register by using the
SCL and CS pins as shown in Figure 4.
H
H
H
H
H
H
H
L
VBIAS is incremented
one tap position.
VBIAS is decremented
one tap position.
Important note: the factory setting of the wiper counter
register is the ZERO-position (0 of 255 taps). This is
the default wiper position.
X
X
Lock Wiper Position.
Save to volatile
memory. (BiasLock™)
or
X
X
L
Open Loop.
Bias Adjustment Block Instructions and Program-
ming. The SCL, INC/DEC (internal signal) and CS
inputs control the movement of the wiper along the
resistor array. (See Table 1) With CS set HIGH, the
device is selected and enabled to respond to the
INC/DEC and SCL inputs. HIGH to LOW transitions on
* When coming out of shutdown, the CS pin must be cycled once before bias
adjustment is enabled.
SCL will increment or decrement R
(depending on
BIAS
the state of the INC/DEC input). The INC/DEC input is
derived from the output of the comparator of the
Sense and Scale Block.
FN8204.0
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March 8, 2005
X9470
Figure 3. Bias Adjustment Block Diagram
Gate Bias
Op Amp
–
VBIAS
to LDMOS gate
VBIAS (unbuffered)
2
RWBIAS
+
RBIAS
RHBIAS
RLBIAS
SHDN
10kΩ
256-tap
XDCP
Memory and Control
INC/DEC is logic HIGH or LOW
from Sense/Scale Block
Legend
and is used to increment or
decrement the Rbias resistor
(XDCP) to adjust the gate voltage.
WCR (Rbias)
External pin/signal
Bias Register
non-volatile
3
Internal node/signal
Power-On Recall
(POR)
1
INC/DEC
U/D
SCL
CS
INC
CS
Note:
1) WCR = Wiper Control Register
NON-VOLATILE STORE OF THE BIAS POSITION
INC/DEC is used as an internal control signal as well.
As an example, when INC/DEC is LOW, the Bias
Adjustment Circuit Block will start to move the Rbias
The following procedure will store the values for the
Rref and Rbias wiper positions in Non-Volatile mem-
ory. This sequence is intended to be performed after a
BiasLock calibration sequence to simplify storage. If
BiasLock has not been achieved, then the Rbias wiper
position may change when the CS pin is brought high
and SCL begins clocking. See Figure 4 for the actual
sequence.
resistor wiper towards the RL
terminal end when
BIAS
CS is HIGH and SCL is clocking. Consequently, the
voltage will decrease, and the I decreases to
V
BIAS
DQ
meet the desired V
setting.
REF
The INC/DEC signal can also be used to detect a
damaged RF power FET. For instance, If INC/DEC
stays HIGH during and after a calibration sequence it
may indicate that the RF power FET has failed. This
indicator can also be used with a level sense on the
1. Set the WEL bit with a write command (02h to reg-
ister 0Fh)
2. Peform a calibration and achieve BiasLock. Leave
CS pin high.
V
pin to perform diagnostics.
OUT
3. Write the address byte only (START, followed by
device/slave address and a 0 for a write, see page
19).
4. Perform a STOP command.
5. With SCL still low, bring the CS low. The falling
edge of the CS will initiate the NV write.
SHUTDOWN MECHANISM
This hardware control shutdown pin (SHDN) will pull
the voltage of V
to VSS with an internal pull down
BIAS
resistor. When shutdown is disabled (V
when SHDN is LOW), the V
the previous desired bias voltage.
is active
voltage will move to
BIAS
BIAS
The WEL bit may be reset afterwards to prevent fur-
ther NV writes.
It will take less than a microsecond to enable the inter-
nal output buffer depending on the loading condition at
the V
pin.
BIAS
INC/DEC FUNCTION
The INC/DEC pin is an open-drain logic output that
tracks the activity of the increment/decrement compar-
OUTPUT (V
)
BIAS
V
is a buffered output of RW
(wiper output). It
BIAS
BIAS
ator. A logic HIGH at INC/DEC indicates that the I
DQ
can deliver a high current for driving up to typically 1nF
capacitive loading with stable performance and fast
settling time.
did not rise up to the desired setting indicated by V
REF
while a logic LOW at the INC/DEC pin indicates that
the IDQ is higher than the desired setting.
FN8204.0
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March 8, 2005
X9470
A single pole filter should be placed in between the
output and the RF input signal to isolate any
V
BIAS
high frequency noise.
Figure 4. Non-Volatile Store of the Bias Position
Calibration
Set
Stop
4
and Bias Lock Address Byte
Set WEL
bit
Initiates
high voltage write
cycle
CS
3
1
2
5
SCL
SDA
tWR
RBIAS non-volatile register
Stored in
Non-volatile
memory
Non-volatile Write of RBIAS and RREF value Using SDA, SCL and CS pins
X9470 PRINCIPLES OF OPERATION
State 0: Monitor Mode
The V and INC/DEC outputs of the X9470 can be
The X9470 is a Bias Controller that contains all the
necessary analog components for closed-loop DC
bias control of LDMOS Transistors in RF Applications.
The X9470 provides a mechanism to periodically set
DC bias operating points of Class A or AB-type ampli-
OUT
used for monitoring and diagnostic purposes. Since
has a lower gain (20x, default) than the internal
V
OUT
IA output, it can handle higher drain sense current
while keeping the output below the rail. This allows nor-
mal PA power monitoring, and over-current sensing us-
ing an external comparator. The INC/DEC pin can be
monitored during calibration to see if there is no
change, which indicates LDMOS functional problems.
Note that the INC/DEC status is also available in the
status register for software status reads.
fiers to account for V
drift and temperature varia-
GS
tions. The following is an example of X9470 operation.
The X9470 incorporates an instrumentation amplifier,
comparator and buffer amplifier along with resistor
arrays and their associated registers and counters. The
serial interface provides direct communication between
the host and the X9470. This section provides a
detailed example of how the X9470 can be used to cali-
brate and dynamically set the optimum bias operating
point of an RF power amplifier (see Figure 5):
State 1: DC-bias Setting When No RF is Present
[Calibration]
At calibration, the DC bias operating point of the
LDMOS Power Amplifier must be set. As soon as the
Bias Adjustment Circuit Block is enabled (CS enabled,
SDA high, and SCL pulse provided), the X9470 will
automatically calibrate the external Power Amplifier by
continually sampling the drain current of the external
Power Amplifier and make adjustments to the gate
voltage of the amplifier (See Figure 6).
– State 0: Power-on Monitor Mode
– State 1: DC-bias Setting When No RF is Present
[Calibration]
– State 2: Calibration Disable When RF is Present
– State 3: PA Standby Mode. Dynamic Adjustment for
V
drift and Temperature variation
GS
– State 4: Power Off (Shutdown) Mode [Turn off the
Power Amplifier]
FN8204.0
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March 8, 2005
X9470
Figure 5. Operating modes X9470
PA
State 0
PA Enabled, Vout and INC/DEC Monitored for status
Monitor Mode
PA
Choose Vref to scale IDQ, perform calibration,
State 1
State 2
Latch bias point for DC bias current in wiper counter
Calibration Mode
PA
Disable Bias Adjustment,
Transmit Mode
Recalibrate bias point for drift and temperature.
Rbias resistor will automatically increment or decrement
for optimal operating point continuously
PA
State 3
State 4
Standby Mode
PA
Off Mode
Turn off PA
When no RF signal is present, the instrumentation
amplifier of the X9470 senses the drain current as a
On edge transitions of the INC/DEC signal, the X9470
will latch the current wiper position - this is known as
“Bias Lock™” mode. This is shown in Figure 6. When
BiasLock occurs, the comparator hysteresis will allow
INC/DEC to change state only after the IA output
changes by more than 20mV. This will prevent toggling
voltage drop, ∆V, across an external drain R
sense
resistor. The ∆V is amplified and compared to an
external scaling voltage, Any difference
between ∆V and V results in a resistive increment
V
.
REF
REF
or decrement of the internal R
potentiometer.
of the V
output unless the drain bias current is con-
BIAS
BIAS
stantly changing.
The R
potentiometer is used as a voltage divider
BIAS
with the RH
and RL
terminals setting the
BIAS
BIAS
State 2: DC-bias Disable When RF is Present
(optional)
upper and lower voltage limits of the unbuffered
RW voltage. The resolution of the R potenti-
BIAS
BIAS
When an RF signal is present, the X9470 is put into
standby mode (open loop). The X9470 is in standby
mode when the CS pin is disabled so that the R
potentiometer holds the last wiper position. The pres-
ence of an RF signal at the input of a Class A or AB
ometer resistor is 0.4% of the difference of voltage
across the RH and RL terminals. The R
is typically 10kΩ with 256-taps. So, for example, if the
difference between the RH
is 1.024V, then the step accuracy is 4mV.
BIAS
BIAS
TOTAL
BIAS
and RL
terminals
BIAS
BIAS
amplifier increases the current across the R
resis-
sense
The voltage at the RW
voltage follower. The V
pin is then fed into the V
BIAS
pin is a buffered output that is
tor. Over a period of time, the temperature of the
LDMOS also increases and the LDMOS also experi-
BIAS
BIAS
used to drive the gate of an LDMOS transistor.
ences V
drift. Therefore the DC biasing point that
GS
was set during State 1 (calibration) is not optimal.
Adjustments to the gate voltage will need to be made
to optimize the operation of the LDMOS PA. This is
done in State 3.
The scaling voltage, V , set by the R potentiom-
eter, sets the calibrated operating point of the LDMOS
Amplifier.
REF
REF
FN8204.0
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March 8, 2005
X9470
State 3: PA Standby Mode, DC Bias Adjustment
Figure 6 illustrates how the X9470 can be used for
dynamic biasing. Upon the presence of an RF signal,
the CS pin is pulled LOW. This will prevent the X9470
[Compensation for V Drift and Temperature
GS
Variation]
from changing the V
rents. Once the RF signal is no longer present, the CS
pin can be enabled (closed loop), SDA high and the
voltage during I
peak cur-
BIAS
DQ
When the Power Amplifier is in Standby Mode the
X9470 allows for dynamic adjustment of the DC bias-
ing point to take into account both V
drift and tem-
GS
X9470 Bias Adjustment Circuit moves the V
volt-
BIAS
perature variation. Dynamic biasing is achieved with
the X9470 by using the CS, and SCL pins. For exam-
ple, the SCL pin can be a steady clock and the CS pin
can be used as a control signal to enable/disable the
Bias Adjustment Block.
age (the gate voltage of the FET) to meet the average
bias point for optimum amplifier performance.
I
DQ
State 4: Power Off Mode
During power saving or power-off modes the X9470
can be shut down via the SHDN pin. This pin pulls the
output of the V
pin LOW.
BIAS
Figure 6. Dynamic Biasing Technique: Automatic DC Bias Operating Point Adjustment
State 3
State 0
Monitor
Mode
State 4
shut
down
State 1
State 2
RF present
Recalibrate bias
point for drift
Calibration
(no RF present)
and temperature
RF signal
Set Operating Range Scale for Bias Adjustment
VREF
Bias Adjustment ON
Bias Adjustment ON
CS
Bias Adjustment OFF
SCL
Saves wiper position to
volatile memory
BiasLock
INC/DEC
BiasLock
SHDN
6
Shut
down
VBIAS
3
4
5
RF present
Turn off
R
bias increase/decrease
2
IDQ vs. gate
voltage bias
optimized
after RF present due to
temperature increase &
VGS-threshold drift
Rbias default is
zero point of Rtotal
Bias
Latch Rbias DC point
in calibration vs VREF
Adjustment
1
Automatic Bias Adjustment
FN8204.0
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March 8, 2005
X9470
X9470 STATUS REGISTER (SR) AND CONTROL REGISTER (CR) INFORMATION
Table 2. Status Register (SR)
Byte
Addr
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
0F hex
SHDN
INC/DEC
0
CS
0
0
WEL
Gain
STATUS REGISTER (SR)
SR1: WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the registers dur-
ing a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL
bit is set LOW, Nonvolatile writes to the registers will
be ignored, and all writes to registers will be volatile.
The WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the Status Register. Once
this write operation is completed and a STOP com-
mand is issued, nonvolatile writes will then occur for all
NOVRAM registers and control bits. Once set, the,
WEL bit remains set until either reset to 0 (by writing a
“0” to the WEL bit and zeroes to the other bits of the
Status Register) or until the part powers up again.
The Status Register is located at address 0F<hex>.
This is a register used to control the write enable
latches, and monitor status of the SHDN, INC/DEC,
and CS pin. This register is separate from the Control
Register.
SR7: SHDN: Vbias SHDN Flag. Read Only—Vola-
tile. The bit keeps status of the shutdown pin, SHDN.
When this bit is HIGH, the SHDN pin is active and the
V
output is disabled. When this bit is LOW, the
BIAS
SHDN pin is low and V
output is enabled.
BIAS
SR6: INC/DEC : Read Only—Volatile. This bit keeps
status of the INC/DEC pin. When this bit is HIGH the
counter is in increment mode, when this bit is LOW the
counter is in decrement mode.
SR0: Gain - NOVRAM
Selects VOUT and IA gain. When SR0=0, VOUT
gain = 20x, IA gain = 50x. When SR0 = 1, VOUT
gain = 50x, and IA gain = 20x. Default setting is 0.
SR4: CS: Read Only—Volatile. This bit keeps status
on the CS pin. When this bit is HIGH, the X9470 is in
closed loop mode (Rbias adjustment enabled). When
this bit is LOW the x9470 is in open loop mode (no
Rbias adjustments).
CONTROL REGISTERS (CR)
The control registers are organized for byte opera-
tions. Each byte has a unique byte address as shown
in Table 3 below.
SR2, SR3, SR5: Read only
For internal test usage, should be set to 0 during SR
writes.
Table 3. Control Registers (CR)
Byte
Bit
Addr.
Reg
<HEX> Description Name
7
Vb7
X
6
Vb6
X
5
4
3
2
1
0
Memory Type
NOVRAM
00 hex DCP for Vbias Vbias
Vb5
Vr5
Vb4
Vr4
Vb3
Vr3
Vb2
Vr2
Vb1
Vr1
Vb0
Vr0
01 hex DCP for VREF
Vref
NOVRAM
Note: 02H to 0EH are reserved for internal manufacturing use.
FN8204.0
March 8, 2005
18
X9470
X9470 BUS INTERFACE INFORMATION
Figure 7. Slave Address, Word Address, and Data Bytes - Write Mode
Slave Address
Device Identifier
Slave Address Byte
R/W=0
A0
S1
S0
0
S2
A3
D3
1
0
1
Byte 0
0Fh : SR
Byte Address
A7
D7
A6
D6
A5
D5
A4
D4
A2
A1
D1
00h : VBIAS
01h : VREF
Byte 1
Data Byte
D2
D0
Byte 2
Figure 8. Slave Address, Word Address, and Data Bytes - Read Mode
Slave Address
Device Identifier
Slave Address Byte
R/W
D0
S2
D3
D3
S1
S0
0
1
0
1
Byte 0
Data Byte
D7
D7
D6
D6
D5
D5
D4
D4
D2
D1
D1
Byte 1
Data Byte
D2
D0
Byte 2
Slave Address, Byte Address, and Data Byte
Start Condition
The byte communication format for the serial bus is
shown in Figures 7 and 8 above. The first byte, BYTE
0, defines the device indentifier, 0101 in the upper
half; and the device slave address in the low half of the
byte. The slave address is determined by the logic val-
ues of the A0, A1, and A2 pins of the X9470. This
allows for up to 8 unique addresses for the X9470. The
next byte, BYTE 1, is the Byte Address. The Byte
Address identifies a unique address for the Status or
Control Registers as shown in Table 3. The following
byte, Byte 2, is the data byte that is used for READ
and WRITE operations.
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 9.
FN8204.0
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March 8, 2005
X9470
Stop Condition
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 9.
Acknowledge
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 10.
– The 2nd Data Byte of a Status Register Write Oper-
ation (only 1 data byte is allowed)
Figure 9. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Figure 10. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Figure 11. Valid Data Changes on the SDA Bus
SCL
Acknowledge
SDA
Data Change
Data Stable
Data Stable
FN8204.0
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X9470
WRITE OPERATIONS
Byte Write
READ OPERATIONS
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the
array. Upon receipt of each address byte, the X9470
responds with an acknowledge. After receiving the
address bytes the X9470 awaits the eight bits of data.
After receiving the 8 data bits, the X9470 again
responds with an acknowledge. The master then ter-
minates the transfer by generating a stop condition.
The X9470 then begins an internal write cycle of the
data to the nonvolatile memory. During the internal
write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 12.
Current Address Read
Internally the X9470 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address is initial-
ized to 0h. In this way, a current address read immedi-
ately after the power-on reset can download the entire
contents of memory starting at the first location. Upon
receipt of the Slave Address Byte with the R/W bit set
to one, the X9470 issues an acknowledge, then trans-
mits eight data bits. The master terminates the read
operation by not responding with an acknowledge dur-
ing the ninth clock and issuing a stop condition. Refer
to Figure 13 for the address, acknowledge, and data
transfer sequence.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X9470 will not initiate an internal
write cycle, and will continue to ACK commands.
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and it’s associated ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the X9470 resets itself without performing the
write. The contents of the array are not affected.
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X9470 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do
this, the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X9470 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X9470 has com-
pleted the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 15.
FN8204.0
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X9470
Figure 12. Byte Write Sequence
S
t
S
t
o
p
Slave
Address
Device
ID
Signals from
the Master
a
r
Byte
Address 0
Data
t
SDA Bus
1 0 1 A2
A0
0
A1
0
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Figure 13. Current Address Read Sequence
S
S
t
o
p
Slave
Address
Device
ID
t
a
r
Signals from the
Master
t
SDA Bus
1 0 1
A2
A0
0
A1
1
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 14. Random Address Read Sequence
S
S
S
t
o
p
Signals from the
Master
t
a
r
Slave
Address
Device
ID
t
a
r
Byte
Address 0
Slave
Address
Device
ID
t
t
SDA Bus
1 0 1
0
1 0 1 A2
A2
A0
0
A1 1
A0
0
A1
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
FN8204.0
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March 8, 2005
X9470
Figure 15. Acknowledge Polling Sequence
Random Read
Random read operations allows the master to access
any location in the X9470. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
Byte load completed
by issuing STOP.
Enter ACK Polling
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt
of each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issu-
ing a stop condition. Refer to Figure 13 for the
address, acknowledge, and data transfer sequence.
Issue START
Issue Slave
Address Byte
(Read or Write)
Issue STOP
NO
ACK
returned?
YES
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 14. The X9470 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
NO
nonvolatile write
Cycle complete.
Continue command
sequence?
Issue STOP
YES
Continue normal
Read or Write
command
sequence
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
FN8204.0
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X9470
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.002 (.06)
.0118 (.30)
.005 (.15)
.010 (.25)
Gage Plane
0° - 8 °
Seating Plane
.020 (.50)
.030 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8204.0
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March 8, 2005
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