LS80C86_技术文档

80C86

CMOS 16-Bit Microprocessor

March 1997

Features

Description

• Compatible with NMOS 8086

The Intersil 80C86 high performance 16-bit CMOS CPU is

manufactured using a self-aligned silicon gate CMOS pro-

cess (Scaled SAJI IV). Two modes of operation, minimum for

small systems and maximum for larger applications such as

multiprocessing, allow user conﬁguration to achieve the

highest performance level. Full TTL compatibility (with the

exception of CLOCK) and industry standard operation allow

use of existing NMOS 8086 hardware and software designs.

• Completely Static CMOS Design

[ /Title

(80C86

)

/Sub-

ject

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86)

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)

• Low Power Operation

- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500µA Max

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ

(CMO

S 16-

Bit

Ordering Information

• 1MByte of Direct Memory Addressing Capability

• 24 Operand Addressing Modes

PKG.

NO.

PACKAGE TEMP. RANGE

5MHz

8MHz

Micro-

proces-

sor)

/Autho

r ()

/Key-

words

(Inter-

sil

Corpo-

ration,

Inter-

sil

• Bit, Byte, Word and Block Move Operations

o

PDIP

0 C to +70 C CP80C86

CP80C86-2 E40.6

IP80C86-2 E40.6

CS80C86-2 N44.65

IS80C86-2 N44.65

CD80C86-2 F40.6

ID80C86-2 F40.6

o

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

- Binary, or Decimal

-40 C to +85 C lP80C86

o

PLCC

CERDIP

0 C to +70 C CS80C86

o

- Multiply and Divide

-40 C to +85 C lS80C86

o

0 C to +70 C CD80C86

• Wide Operating Temperature Range

- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0^oC to +70^oC

- l80C86 . . . . . . . . . . . . . . . . . . . . . . . . . -40^oC to +85^oC

- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55^oC to +125^oC

o

-40 C to +85 C ID80C86

o

-55 C to +125 C MD80C86/B MD80C86- F40.6

2/B

o

SMD#

CLCC

-55 C to +125 C 8405201QA 8405202QA F40.6

o

-55 C to +125 C MR80C86/B MR80C86- J44.A

2/B

o

SMD#

-55 C to +125 C 8405201XA 8405202XA J44.A

Corpo-

ration,

16 Bit

uP,

micro-

proces-

sor,

8086,

PC)

/Cre-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 2957.1

80C86

Pinouts

80C86 (DIP)

TOP VIEW

MAX

(MIN)

GND

AD14

AD13

AD12

AD11

AD10

AD9

1

2

3

4

5

6

7

8

9

40 V_CC

39 AD15

38 A16/S3

37 A17/S4

36 A18/S5

35 A19/S6

34 BHE/S7

33 MN/MX

32 RD

AD8

AD7

AD6 10

AD5 11

AD4 12

AD3 13

AD2 14

AD1 15

AD0 16

NMI 17

INTR 18

CLK 19

GND 20

31 RQ/GT0 (HOLD)

30 RQ/GT1 (HLDA)

29 LOCK

28 S2

(WR)

(M/IO)

(DT/R))

(DEN)

(ALE)

(INTA)

27 S1

26 S0

25 QS0

24 QS1

23 TEST

22 READY

21 RESET

80C86 (PLCC, CLCC)

TOP VIEW

MAX MODE

80C86

MIN MODE

80C86

44

43 42 41 40

6

5

4

3

2

1

7

39

38

37

36

35

34

33

32

31

30

29

AD10

AD9

AD10

AD9

NC

A19/S6

8

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD8

AD7

AD6

AD5

AD4

AD3

AD2

9

BHE/S7

MN/MX

RD

BHE/S7

MN/MX

RD

10

11

12

13

14

15

16

17

HOLD

HLDA

WR

RQ/GT0

RQ/GT1

LOCK

S2

M/IO

AD1

AD0

AD1

AD0

DT/R

DEN

S1

S0

18 19 20 21 22 23 24 25 26 27 28

MIN MODE

80C86

MAX MODE

80C86

3-142

80C86

Functional Diagram

EXECUTION UNIT

REGISTER FILE

BUS INTERFACE UNIT

RELOCATION

REGISTER FILE

DATA POINTER

AND

INDEX REGS

(8 WORDS)

SEGMENT REGISTERS

AND

INSTRUCTION POINTER

(5 WORDS)

BHE/S7

A19/S6

A16/S3

16-BIT ALU

FLAGS

4

AD15-AD0

16

3

BUS INTERFACE UNIT

INTA, RD, WR

DT/R, DEN, ALE, M/IO

4

6-BYTE

INSTRUCTION

QUEUE

TEST

INTR

NMI

LOCK

2

QS0, QS1

S2, S1, S0

CONTROL AND TIMING

RQ/GT0, 1

2

HOLD

HLDA

3

CLK

RESET READY MN/MX GND

V_CC

MEMORY INTERFACE

C-BUS

INSTRUCTION

STREAM BYTE

QUEUE

B-BUS

ES

CS

SS

BUS

INTERFACE

UNIT

DS

IP

EXECUTION UNIT

CONTROL SYSTEM

A-BUS

AH

AL

BL

CL

DL

ARITHMETIC/

LOGIC UNIT

BH

CH

DH

EXECUTION

UNIT

SP

BP

SI

FLAGS

DI

3-143

80C86

Pin Description

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is

the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).

SYMBOL

NUMBER

TYPE

DESCRIPTION

AD15-AD0

2-16, 39

I/O

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and

data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-

D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory

or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-

dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-

ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”

or “grant sequence”.

A19/S6

A18/S5

A17/S4

A16/S3

35-38

O

ADDRESS/STATUS: During T1, these are the four most signiﬁcant address lines for memory op-

erations. During I/O operations these lines are LOW. During memory and I/O operations, status

information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of

the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3

are encoded as shown.

This information indicates which segment register is presently being used for data accessing.

These lines are held at high impedance to the last valid logic level during local bus “hold ac-

knowledge” or “grant sequence”.

S4

0

S3

0

CHARACTERISTICS

Alternate Data

Stack

0

1

0

Code or None

Data

1

BHE/S7

34

O

BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to

enable data onto the most signiﬁcant half of the data bus, pins D15-D8. Eight bit oriented devices

tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE

is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-

ferred on the high portion of the bus. The S7 status information is available during T2, T3 and

T4. The signal is active LOW, and is held at high impedance to the last valid logic level during

interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during

T1 for the ﬁrst interrupt acknowledge cycle.

BHE

A0

0

CHARACTERISTICS

Whole Word

0

1

Upper Byte From/to Odd Address

Lower Byte From/to Even address

None

0

1

RD

32

22

O

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-

pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on

the 80C86 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-

teed to remain HIGH in T2 until the 80C86 local bus has ﬂoated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-

quence”.

READY

I

READY: is the acknowledgment from the addressed memory or I/O device that will complete the

data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gener-

ator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.

Correct operation is not guaranteed if the Setup and Hold Times are not met.

3-144

80C86

Pin Description (Continued)

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is

the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).

SYMBOL

NUMBER

TYPE

DESCRIPTION

INTR

18

I

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle

of each instruction to determine if the processor should enter into an interrupt acknowledge op-

eration. A subroutine is vectored to via an interrupt vector lookup table located in system mem-

ory. It can be internally masked by software resetting the interrupt enable bit.

lNTR is internally synchronized. This signal is active HIGH.

TEST

NMI

23

17

I

TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,

otherwise the processor waits in an “Idle” state. This input is synchronized internally during each

clock cycle on the leading edge of CLK.

NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A

subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is

not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the

end of the current instruction. This input is internally synchronized.

RESET

21

I

RESET: causes the processor to immediately terminate its present activity. The signal must tran-

sition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution,

as described in the Instruction Set description, when RESET returns LOW. RESET is internally

synchronized.

CLK

VCC

19

40

CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a

33% duty cycle to provide optimized internal timing.

VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for de-

coupling.

GND

1, 20

33

GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is rec-

ommended for decoupling.

MN/MX

I

MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are

discussed in the following sections.

Minimum Mode System

The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V ). Only the pin functions which are unique to

CC

minimum mode are described; all other pin functions are as described below.

SYMBOL

NUMBER

TYPE

DESCRIPTION

M/IO

28

O

STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-

ory access from an I/O access. M/lO becomes valid in the T4 preceding a bus cycle and remains

valid until the ﬁnal T4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic

one during local bus “hold acknowledge”.

WR

INTA

ALE

29

24

25

O

WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending

on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active

LOW, and is held to high impedance logic one during local bus “hold acknowledge”.

INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is

active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never

ﬂoated.

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the

82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle.

Note that ALE is never ﬂoated.

3-145

80C86

Minimum Mode System (Continued)

The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V ). Only the pin functions which are unique to

CC

minimum mode are described; all other pin functions are as described below.

SYMBOL

NUMBER

TYPE

DESCRIPTION

DT/R

27

O

DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus

transceiver. It is used to control the direction of data ﬂow through the transceiver. Logically,

DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,

R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.

DEN

26

O

DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system which

uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cy-

cles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for a

write cycle it is active from the beginning of T2 until the middle of T4. DEN is held to a high im-

pedance logic one during local bus “hold acknowledge”.

HOLD

HLDA

31, 30

I

O

HOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged,

HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge”

(HLDA) in the middle of a T4 or TI clock cycle. Simultaneously with the issuance of HLDA, the

processor will ﬂoat the local bus and control lines. After HOLD is detected as being LOW, the

processor will lower HLDA, and when the processor needs to run another cycle, it will again drive

the local bus and control lines.

HOLD is not an asynchronous input. External synchronization should be provided if the system

cannot otherwise guarantee the setup time.

Maximum Mode System

The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are

unique to maximum mode are described below.

SYMBOL

NUMBER

TYPE

DESCRIPTION

S0

S1

S2

26

27

28

O

STATUS: is active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during T3

or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate

all memory and I/O access control signals. Any change by S2, S1 or S0 during T4 is used to

indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to

indicate the end of a bus cycle.

These signals are held at a high impedance logic one state during “grant sequence”.

S2

0

S1

0

S0

0

CHARACTERISTICS

Interrupt Acknowledge

0

1

Read I/O Port

Write I/O Port

Halt

0

1

0

1

0

Code Access

Read Memory

Write Memory

Passive

1

0

1

0

1

3-146

80C86

Maximum Mode System (Continued)

The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are

unique to maximum mode are described below.

SYMBOL

NUMBER

TYPE

DESCRIPTION

RQ/GT0

RQ/GT1

31, 30

I/O

REQUEST/GRANT: pins are used by other local bus masters to force the processor to release

the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with

RQ/GTO having higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so

it may be left unconnected. The request/grant sequence is as follows (see RQ/GT Sequence

Timing)

1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”)

to the 80C86 (pulse 1).

2. During a T4 or TI clock cycle, a pulse 1 CLK wide from the 80C86 to the requesting master

(pulse 2) indicates that the 80C86 has allowed the local bus to ﬂoat and that it will enter the

“grant sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logi-

cally from the local bus during “grant sequence”.

3. A pulse 1 CLK wide from the requesting master indicates to the 80C86 (pulse 3) that the

“hold” request is about to end and that the 80C86 can reclaim the local bus at the next CLK.

The CPU then enters T4 (or TI if no bus cycles pending).

Each Master-Master exchange of the local bus is a sequence of 3 pulses. There must be one

idle CLK cycle after each bus exchange. Pulses are active low.

If the request is made while the CPU is performing a memory cycle, it will release the local

bus during T4 of the cycle when all the following conditions are met:

1. Request occurs on or before T2.

2. Current cycle is not the low byte of a word (on an odd address).

3. Current cycle is not the ﬁrst acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing.

If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next cycle.

2. A memory cycle will start within three clocks. Now the four rules for a currently active memory

cycle apply with condition number 1 already satisﬁed.

LOCK

29

O

LOCK: output indicates that other system bus masters are not to gain control of the system bus

while LOCK is active LOW. The LOCK signal is activated by the “LOCK” preﬁx instruction and

remains active until the completion of the next instruction. This signal is active LOW, and is held

at a high impedance logic one state during “grant sequence”. In MAX mode, LOCK is automat-

ically generated during T2 of the ﬁrst INTA cycle and removed during T2 of the second INTA

cycle.

QS1, QSO

24, 25

QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue opera-

tion is performed.

QS1 and QS0 provide status to allow external tracking of the internal 80C86 instruction queue.

Note that QS1, QS0 never become high impedance.

QSI

0

QSO

0

1

0

1

No Operation

0

First byte of op code from queue

Empty the queue

1

Subsequent byte from queue

3-147

80C86

code, data, extra and stack segments of up to 64K bytes

each, with each segment falling on 16-byte boundaries. (See

Figure 1).

Functional Description

Static Operation

All 80C86 circuitry is of static design. Internal registers,

counters and latches are static and require no refresh as

with dynamic circuit design. This eliminates the minimum

operating frequency restriction placed on other microproces-

sors. The CMOS 80C86 can operate from DC to the speci-

ﬁed upper frequency limit. The processor clock may be

stopped in either state (HIGH/LOW) and held there indeﬁ-

nitely. This type of operation is especially useful for system

debug or power critical applications.

FFFFFH

64K-BIT

CODE SEGMENT

XXXXOH

STACK SEGMENT

DATA SEGMENT

+ OFFSET

The 80C86 can be single stepped using only the CPU clock.

This state can be maintained as long as is necessary. Single

step clock operation allows simple interface circuitry to pro-

vide critical information for bringing up your system.

SEGMENT

REGISTER FILE

CS

SS

DS

ES

Static design also allows very low frequency operation

(down to DC). In a power critical situation, this can provide

extremely low power operation since 80C86 power dissipa-

tion is directly related to operating frequency. As the system

frequency is reduced, so is the operating power until, ulti-

mately, at a DC input frequency, the 80C86 power require-

ment is the standby current, (500µA maximum).

EXTRA SEGMENT

00000H

Internal Architecture

FIGURE 1. 80C86 MEMORY ORGANIZATION

TABLE 1.

The internal functions of the 80C86 processor are parti-

tioned logically into two processing units. The ﬁrst is the Bus

Interface Unit (BlU) and the second is the Execution Unit

(EU) as shown in the CPU functional diagram.

TYPE OF

MEMORY

REFERENCE

DEFAULT

SEGMENT

BASE

ALTERNATE

SEGMENT

BASE

These units can interact directly, but for the most part perform

as separate asynchronous operational processors. The bus

interface unit provides the functions related to instruction

fetching and queuing, operand fetch and store, and address

relocation. This unit also provides the basic bus control. The

overlap of instruction pre-fetching provided by this unit serves

to increase processor performance through improved bus

bandwidth utilization. Up to 6 bytes of the instruction stream

can be queued while waiting for decoding and execution.

OFFSET

IP

Instruction Fetch

Stack Operation

CS

SS

DS

None

SP

Variable (except

following)

CS, ES, SS

Effective

Address

String Source

DS

ES

SS

CS, ES, SS

None

SI

DI

String Destination

The instruction stream queuing mechanism allows the BIU

to keep the memory utilized very efﬁciently. Whenever there

is space for at least 2 bytes in the queue, the BlU will attempt

a word fetch memory cycle. This greatly reduces “dead-time”

on the memory bus. The queue acts as a First-In-First-Out

(FIFO) buffer, from which the EU extracts instruction bytes

as required. If the queue is empty (following a branch

instruction, for example), the ﬁrst byte into the queue imme-

diately becomes available to the EU.

BP Used As Base

Register

CS, DS, ES

Effective

Address

All memory references are made relative to base addresses

contained in high speed segment registers. The segment

types were chosen based on the addressing needs of pro-

grams. The segment register to be selected is automatically

chosen according to the speciﬁc rules of Table 1. All informa-

tion in one segment type share the same logical attributes

(e.g. code or data). By structuring memory into re-locatable

areas of similar characteristics and by automatically select-

ing segment registers, programs are shorter, faster and

more structured. (See Table 1).

The execution unit receives pre-fetched instructions from the

BlU queue and provides un-relocated operand addresses to

the BlU. Memory operands are passed through the BIU for pro-

cessing by the EU, which passes results to the BIU for storage.

Word (16-bit) operands can be located on even or odd

address boundaries and are thus, not constrained to even

boundaries as is the case in many 16-bit computers. For

address and data operands, the least signiﬁcant byte of the

word is stored in the lower valued address location and the

most signiﬁcant byte in the next higher address location. The

BIU automatically performs the proper number of memory

Memory Organization

The processor provides a 20-bit address to memory, which

locates the byte being referenced. The memory is organized

as a linear array of up to 1 million bytes, addressed as

00000(H) to FFFFF(H). The memory is logically divided into

3-148

80C86

accesses; one, if the word operand is on an even byte 80C86 provides DEN and DT/R to control the transceiver, and

boundary and two, if it is on an odd byte boundary. Except ALE to latch the addresses. This conﬁguration of the minimum

for the performance penalty, this double access is transpar- mode provides the standard demultiplexed bus structure with

ent to the software. The performance penalty does not occur heavy bus buffering and relaxed bus timing requirements.

for instruction fetches; only word operands.

The maximum mode employs the 82C88 bus controller (See

Physically, the memory is organized as a high bank (D15-

D8) and a low bank (D7-D0) of 512K bytes addressed in par-

allel by the processor’s address lines.

Figure 6B). The 82C88 decodes status lines S0, S1 and S2,

and provides the system with all bus control signals.

Moving the bus control to the 82C88 provides better source

and sink current capability to the control lines, and frees the

80C86 pins for extended large system features. Hardware

lock, queue status, and two request/grant interfaces are pro-

vided by the 80C86 in maximum mode. These features allow

coprocessors in local bus and remote bus conﬁgurations.

Byte data with even addresses is transferred on the D7-D0

bus lines, while odd addressed byte data (A0 HIGH) is trans-

ferred on the D15-D8 bus lines. The processor provides two

enable signals, BHE and A₀, to selectively allow reading

from or writing into either an odd byte location, even byte

location, or both. The instruction stream is fetched from

memory as words and is addressed internally by the proces-

sor at the byte level as necessary.

Bus Operation

The 80C86 has a combined address and data bus com-

monly referred to as a time multiplexed bus. This technique

provides the most efﬁcient use of pins on the processor

while permitting the use of a standard 40 lead package. This

“local bus” can be buffered directly and used throughout the

system with address latching provided on memory and I/O

modules. In addition, the bus can also be demultiplexed at

the processor with a single set of 82C82 address latches if a

standard non-multiplexed bus is desired for the system.

In referencing word data, the BlU requires one or two memory

cycles depending on whether the starting byte of the word is

on an even or odd address, respectively. Consequently, in ref-

erencing word operands performance can be optimized by

locating data on even address boundaries. This is an espe-

cially useful technique for using the stack, since odd address

references to the stack may adversely affect the context

switching time for interrupt processing or task multiplexing.

Each processor bus cycle consists of at least four CLK

cycles. These are referred to as T1, T2, T3 and T4 (see Fig-

ure 3). The address is emitted from the processor during T1

and data transfer occurs on the bus during T3 and T4. T2 is

used primarily for changing the direction of the bus during

read operations. In the event that a “NOT READY” indication

is given by the addressed device, “Wait” states (TW) are

inserted between T3 and T4. Each inserted wait state is the

same duration as a CLK cycle. Periods can occur between

80C86 driven bus cycles. These are referred to as idle”

states (T_I) or inactive CLK cycles. The processor uses these

cycles for internal housekeeping and processing.

Certain locations in memory are reserved for speciﬁc CPU

operations (See Figure 2). Locations from address FFFF0H

through FFFFFH are reserved for operations including a jump

to the initial program loading routine. Following RESET, the

CPU will always begin execution at location FFFF0H where

the jump must be located. Locations 00000H through 003FFH

are reserved for interrupt operations. Each of the 256 possible

interrupt service routines is accessed thru its own pair of 16-

bit pointers (segment address pointer and offset address

pointer). The ﬁrst pointer, used as the offset address, is

loaded into the lP and the second pointer, which designates

the base address is loaded into the CS. At this point program

control is transferred to the interrupt routine. The pointer ele-

ments are assumed to have been stored at the respective

places in reserved memory prior to occurrence of interrupts.

During T1 of any bus cycle, the ALE (Address Latch Enable)

signal is emitted (by either the processor or the 82C88 bus

controller, depending on the MN/MX strap). At the trailing

edge of this pulse, a valid address and certain status infor-

mation for the cycle may be latched.

Minimum and Maximum Operation Modes

The requirements for supporting minimum and maximum

80C86 systems are sufﬁciently different that they cannot be

met efﬁciently using 40 uniquely deﬁned pins. Consequently,

the 80C86 is equipped with a strap pin (MN/MX) which

deﬁnes the system conﬁguration. The deﬁnition of a certain

subset of the pins changes, dependent on the condition of the

strap pin. When the MN/MX pin is strapped to GND, the

80C86 deﬁnes pins 24 through 31 and 34 in maximum mode.

When the MN/MX pin is strapped to V_CC, the 80C86 gener-

ates bus control signals itself on pins 24 through 31 and 34.

Status bits S0, S1 and S2 are used by the bus controller, in

maximum mode, to identify the type of bus transaction

according to Table 2.

TABLE 2.

S2

0

S1

0

S0

0

CHARACTERISTICS

Interrupt

0

1

Read I/O

0

1

0

Write I/O

The minimum mode 80C86 can be used with either a multi-

plexed or demultiplexed bus. This architecture provides the

80C86 processing power in a highly integrated form.

0

1

Halt

1

0

Instruction Fetch

Read Data from Memory

Write Data to Memory

Passive (No Bus Cycle)

1

0

1

The demultiplexed mode requires two 82C82 latches (for 64K

addressability) or three 82C82 latches (for a full megabyte of

addressing). An 82C86 or 82C87 transceiver can also be

used if data bus buffering is required. (See Figure 6A.) The

1

0

1

3-149

80C86

Status bits S3 through S7 are time multiplexed with high I/O Addressing

order address bits and the BHE signal, and are therefore

In the 80C86, I/O operations can address up to a maximum

valid during T2 through T4. S3 and S4 indicate which seg-

ment register (see Instruction Set Description) was used for

this bus cycle in forming the address, according to Table 3.

of 64K I/O byte registers or 32K I/O word registers. The I/O

address appears in the same format as the memory address

on bus lines A15-A0. The address lines A19-A16 are zero in

I/O operations. The variable I/O instructions which use regis-

ter DX as a pointer have full address capability while the

direct I/O instructions directly address one or two of the 256

I/O byte locations in page 0 of the I/O address space.

S5 is a reﬂection of the PSW interrupt enable bit. S3 is

always zero and S7 is a spare status bit.

TABLE 3.

S4

0

S3

0

CHARACTERISTICS

I/O ports are addressed in the same manner as memory loca-

tions. Even addressed bytes are transferred on the D7-D0 bus

lines and odd addressed bytes on D15-D8. Care must be taken

to ensure that each register within an 8-bit peripheral located on

the lower portion of the bus be addressed as even.

Alternate Data (Extra Segment)

0

1

Stack

1

0

Code or None

Data

1

FFFFFH

FFFF0H

RESET BOOTSTRAP

PROGRAM JUMP

TYPE 225 POINTER

(AVAILABLE)

3FFH

3FCH

AVAILABLE

INTERRUPT

POINTERS

(224)

TYPE 33 POINTER

(AVAILABLE)

084H

080H

TYPE 32 POINTER

(AVAILABLE)

TYPE 31 POINTER

(AVAILABLE)

07FH

RESERVED

INTERRUPT

POINTERS

(27)

TYPE 5 POINTER

(RESERVED)

014H

010H

TYPE 4 POINTER

OVERFLOW

TYPE 3 POINTER

1 BYTE INT INSTRUCTION

00CH

DEDICATED

TYPE 2 POINTER

NON MASKABLE

INTERRUPT

008H

POINTERS

(5)

TYPE 1 POINTER

SINGLE STEP

004H

TYPE 0 POINTER

DIVIDE ERROR

CS BASE ADDRESS

IP OFFSET

000H

16 BITS

FIGURE 2. RESERVED MEMORY LOCATIONS

3-150

80C86

(4 + NWAIT) = TCY

T3 TWAIT

(4 + NWAIT) = TCY

T3 TWAIT

T1

T2

T4

T1

T2

T4

CLK

GOES INACTIVE IN THE STATE

JUST PRIOR TO T₄

ALE

S2-S0

BHE,

A19-A16

BHE

A19-A16

ADDR/

STATUS

S7-S3

BUS RESERVED

FOR DATA IN

D15-D0

VALID

A15-A0

DATA OUT (D15-D0)

ADDR/DATA

RD, INTA

READY

WAIT

DT/R

DEN

WR

MEMORY ACCESS TIME

FIGURE 3. BASIC SYSTEM TIMING

3-151

80C86

Interrupt Operations

External Interface

Interrupt operations fall into two classes: software or hard-

ware initiated. The software initiated interrupts and software

aspects of hardware interrupts are speciﬁed in the Instruc-

tion Set Description. Hardware interrupts can be classiﬁed

as non-maskable or maskable.

Processor RESET and Initialization

Processor initialization or start up is accomplished with activa-

tion (HIGH) of the RESET pin. The 80C86 RESET is required to

be HIGH for greater than 4 CLK cycles. The 80C86 will termi-

nate operations on the high-going edge of RESET and will

remain dormant as long as RESET is HIGH. The low-going

transition of RESET triggers an internal reset sequence for

approximately 7 clock cycles. After this interval, the 80C86

operates normally beginning with the instruction in absolute

location FFFF0H. (See Figure 2). The RESET input is internally

synchronized to the processor clock. At initialization, the HIGH-

to-LOW transition of RESET must occur no sooner than 50µs

(or 4 CLK cycles, whichever is greater) after power-up, to allow

complete initialization of the 80C86.

Interrupts result in a transfer of control to a new program loca-

tion. A 256-element table containing address pointers to the

interrupt service program locations resides in absolute loca-

tions 0 through 3FFH, which are reserved for this purpose.

Each element in the table is 4 bytes in size and corresponds

to an interrupt “type”. An interrupting device supplies an 8-bit

type number during the interrupt acknowledge sequence,

which is used to “vector” through the appropriate element to

the new interrupt service program location. All ﬂags and both

the Code Segment and Instruction Pointer register are saved

as part of the lNTA sequence. These are restored upon exe-

cution of an Interrupt Return (IRET) instruction.

NMl will not be recognized prior to the second CLK cycle follow-

ing the end of RESET. If NMl is asserted sooner than nine clock

cycles after the end of RESET, the processor may execute one

instruction before responding to the interrupt.

Non-Maskable Interrupt (NMI)

The processor provides a single non-maskable interrupt pin

(NMI) which has higher priority than the maskable interrupt

request pin (INTR). A typical use would be to activate a

power failure routine. The NMI is edge-triggered on a LOW-

to-HIGH transition. The activation of this pin causes a type 2

interrupt.

Bus Hold Circuitry

To avoid high current conditions caused by ﬂoating inputs to

CMOS devices and to eliminate need for pull-up/down resistors,

“bus-hold” circuitry has been used on the 80C86 pins 2-16, 26-

32 and 34-39. (See Figure 4A and Figure 4B). These circuits

will maintain the last valid logic state if no driving source is

present (i.e., an unconnected pin or a driving source which

goes to a high impedance state). To overdrive the “bus hold” cir-

cuits, an external driver must be capable of supplying approxi-

mately 400µA minimum sink or source current at valid input

voltage levels. Since this “bus hold” circuitry is active and not a

“resistive” type element, the associated power supply current is

negligible and power dissipation is signiﬁcantly reduced when

compared to the use of passive pull-up resistors.

NMl is required to have a duration in the HIGH state of

greater than two CLK cycles, but is not required to be syn-

chronized to the clock. Any positive transition of NMI is

latched on-chip and will be serviced at the end of the current

instruction or between whole moves of a block-type instruc-

tion. Worst case response to NMI would be for multiply,

divide, and variable shift instructions. There is no speciﬁca-

tion on the occurrence of the low-going edge; it may occur

before, during or after the servicing of NMI. Another positive

edge triggers another response if it occurs after the start of

the NMI procedure. The signal must be free of logical spikes

in general and be free of bounces on the low-going edge to

avoid triggering extraneous responses.

BOND

PAD

EXTERNAL

OUTPUT

DRIVER

INPUT

BUFFER

Maskable Interrupt (INTR)

INPUT

PROTECTION

CIRCUITRY

The 80C86 provides a single interrupt request input (lNTR)

which can be masked internally by software with the reset-

ting of the interrupt enable ﬂag (IF) status bit. The interrupt

request signal is level triggered. It is internally synchronized

during each clock cycle on the high-going edge of CLK. To

be responded to, lNTR must be present (HIGH) during the

clock period preceding the end of the current instruction or

the end of a whole move for a block type instruction. lNTR

may be removed anytime after the falling edge of the ﬁrst

INTA signal. During the interrupt response sequence further

interrupts are disabled. The enable bit is reset as part of the

response to any interrupt (lNTR, NMI, software interrupt or

single-step), although the FLAGS register which is automati-

cally pushed onto the stack reﬂects the state of the proces-

sor prior to the interrupt. Until the old FLAGS register is

restored, the enable bit will be zero unless speciﬁcally set by

an instruction.

FIGURE 4A. BUS HOLD CIRCUITRY PIN 2-16, 34-39

BOND

PAD

EXTERNAL

V_CC

P

OUTPUT

DRIVER

INPUT

BUFFER

INPUT

PROTECTION

CIRCUITRY

FIGURE 4B. BUS HOLD CIRCUITRY PIN 26-32

3-152

80C86

During the response sequence (Figure 5) the processor exe- External Synchronization Via TEST

cutes two successive (back-to-back) interrupt acknowledge

As an alternative to interrupts, the 80C86 provides a single

cycles. The 80C86 emits the LOCK signal (Max mode only)

from T2 of the ﬁrst bus cycle until T2 of the second. A local

bus “hold” request will not be honored until the end of the

second bus cycle. In the second bus cycle, a byte is supplied

to the 80C86 by the 82C59A Interrupt Controller, which iden-

tiﬁes the source (type) of the interrupt. This byte is multiplied

by four and used as a pointer into the interrupt vector lookup

table. An INTR signal left HIGH will be continually responded

to within the limitations of the enable bit and sample period.

The INTERRUPT RETURN instruction includes a FLAGS

pop which returns the status of the original interrupt enable

bit when it restores the FLAGS.

software-testable input pin (TEST). This input is utilized by

executing a WAIT instruction. The single WAIT instruction is

repeatedly executed until the TEST input goes active (LOW).

The execution of WAIT does not consume bus cycles once

the queue is full.

If a local bus request occurs during WAIT execution, the

80C86 three-states all output drivers while inputs and I/O

pins are held at valid logic levels by internal bus-hold circuits.

If interrupts are enabled, the 80C86 will recognize interrupts

and process them when it regains control of the bus. The

WAIT instruction is then refetched, and re-executed.

T1

T3

T1

T2

T3

T4 TI

T2

T4

TABLE 4. 80C86 REGISTER

ALE

ACCUMULATOR

AH

BH

CH

DH

AL

BL

CL

DL

AX

BX

CX

DX

BASE

COUNT

DATA

LOCK

INTA

SP

BP

SI

STACK POINTER

FLOAT

AD0-

AD15

TYPE

VECTOR

BASE POINTER

SOURCE INDEX

DESTINATION INDEX

DI

FIGURE 5. INTERRUPT ACKNOWLEDGE SEQUENCE

IP

INSTRUCTION POINTER

STATUS FLAG

Halt

FLAGS_HFLAGS_L

When a software “HALT” instruction is executed the proces-

sor indicates that it is entering the “HALT” state in one of two

ways depending upon which mode is strapped. In minimum

mode, the processor issues one ALE with no qualifying bus

control signals. In maximum mode the processor issues

appropriate HALT status on S2, S1, S0 and the 82C88 bus

controller issues one ALE. The 80C86 will not leave the

“HALT” state when a local bus “hold” is entered while in

“HALT”. In this case, the processor reissues the HALT indi-

cator at the end of the local bus hold. An NMI or interrupt

request (when interrupts enabled) or RESET will force the

80C86 out of the “HALT” state.

CS

DS

SS

ES

CODE SEGMENT

DATA SEGMENT

STACK SEGMENT

EXTRA SEGMENT

Basic System Timing

Typical system conﬁgurations for the processor operating in

minimum mode and in maximum mode are shown in Figures

6A and 6B, respectively. In minimum mode, the MN/MX pin

is strapped to VCC and the processor emits bus control sig-

nals (e.g. RD, WR, etc.) directly. In maximum mode, the

MN/MX pin is strapped to GND and the processor emits

coded status information which the 82C88 bus controller

uses to generate MULTIBUS compatible bus control signals.

Figure 3 shows the signal timing relationships.

Read/Modify/Write (Semaphore)

Operations Via Lock

The LOCK status information is provided by the processor

when consecutive bus cycles are required during the execution

of an instruction. This gives the processor the capability of per-

forming read/modify/write operations on memory (via the

Exchange Register With Memory instruction, for example) with-

out another system bus master receiving intervening memory

cycles. This is useful in multiprocessor system conﬁgurations to

accomplish “test and set lock” operations. The LOCK signal is

activated (forced LOW) in the clock cycle following decoding of

the software “LOCK” preﬁx instruction. It is deactivated at the

end of the last bus cycle of the instruction following the “LOCK”

preﬁx instruction. While LOCK is active a request on a RQ/GT

pin will be recorded and then honored at the end of the LOCK.

System Timing - Minimum System

The read cycle begins in T1 with the assertion of the

Address Latch Enable (ALE) signal. The trailing (low-going)

edge of this signal is used to latch the address information,

which is valid on the address/data bus (AD0-AD15) at this

time, into the 82C82/82C83 latch. The BHE and A0 signals

address the low, high or both bytes. From T1 to T4 the M/lO

signal indicates a memory or I/O operation. At T2, the

address is removed from the address/data bus and the bus

is held at the last valid logic state by internal bus hold

3-153

80C86

devices. The read control signal is also asserted at T2. The Bus Timing - Medium Size Systems

read (RD) signal causes the addressed device to enable its

For medium complexity systems the MN/MX pin is con-

data bus drivers to the local bus. Some time later, valid data

will be available on the bus and the addressed device will

drive the READY line HIGH. When the processor returns the

read signal to a HIGH level, the addressed device will again

three-state its bus drivers. If a transceiver (82C86/82C87) is

required to buffer the 80C86 local bus, signals DT/R and

DEN are provided by the 80C86.

nected to GND and the 82C88 Bus Controller is added to the

system as well as an 82C82/82C83 latch for latching the

system address, and an 82C86/82C87 transceiver to allow

for bus loading greater than the 80C86 is capable of han-

dling. Signals ALE, DEN, and DT/R are generated by the

82C88 instead of the processor in this conﬁguration,

although their timing remains relatively the same. The

A write cycle also begins with the assertion of ALE and the 80C86 status outputs (S2, S1 and S0) provide type-of-cycle

emission of the address. The M/IO signal is again asserted information and become 82C88 inputs. This bus cycle infor-

to indicate a memory or I/O write operation. In T2, immedi- mation speciﬁes read (code, data or I/O), write (data or I/O),

ately following the address emission, the processor emits interrupt acknowledge, or software halt. The 82C88 issues

the data to be written into the addressed location. This data control signals specifying memory read or write, I/O read or

remains valid until at least the middle of T4. During T2, T3 write, or interrupt acknowledge. The 82C88 provides two

and TW, the processor asserts the write control signal. The types of write strobes, normal and advanced, to be applied

write (WR) signal becomes active at the beginning of T2 as as required. The normal write strobes have data valid at the

opposed to the read which is delayed somewhat into T2 to leading edge of write. The advanced write strobes have the

provide time for output drivers to become inactive.

same timing as read strobes, and hence, data is not valid at

the leading edge of write. The 82C86/82C87 transceiver

receives the usual T and OE inputs from the 82C88 DT/R

and DEN signals.

The BHE and A0 signals are used to select the proper

byte(s) of the memory/lO word to be read or written accord-

ing to Table 5.

The pointer into the interrupt vector table, which is passed

during the second INTA cycle, can be derived from an

82C59A located on either the local bus or the system bus. If

the master 82C59A Priority Interrupt Controller is positioned

on the local bus, the 82C86/82C87 transceiver must be dis-

abled when reading from the master 82C59A during the

interrupt acknowledge sequence and software “poll”.

TABLE 5.

BHE

A0

0

CHARACTERISTICS

Whole word

0

1

Upper Byte From/To Odd Address

Lower Byte From/To Even Address

None

0

1

I/O ports are addressed in the same manner as memory

location. Even addressed bytes are transferred on the D7-D0

bus lines and odd address bytes on D15-D8.

The basic difference between the interrupt acknowledge

cycle and a read cycle is that the interrupt acknowledge sig-

nal (INTA) is asserted in place of the read (RD) signal and

the address bus is held at the last valid logic state by internal

bus hold devices. (See Figure 4). In the second of two suc-

cessive INTA cycles a byte of information is read from the

data bus (D7-D0) as supplied by the interrupt system logic

(i.e., 82C59A Priority Interrupt Controller). This byte identi-

ﬁes the source (type) of the interrupt. It is multiplied by four

and used as a pointer into an interrupt vector lookup table,

as described earlier.

3-154

80C86

V_CC

MN/MX

M/IO

V_CC

82C8A/85

CLOCK

INTA

RD

CLK

GENERATOR

READY

RESET

WR

RES

RDY

DT/R

DEN

ALE

WAIT

STATE

GENERATOR

GND

80C86

STB

OE

CPU

GND

ADDR/DATA

GND

1

ADDR

AD0-AD15

A16-A19

82C82

LATCH

2 OR 3

C1

C2

V_CC

BHE

GND

20

T

V_CC

40

OE

DATA

82C86

C1 = C2 = 0.1µF

TRANSCEIVER

(2)

A0

E_L

BHE

E_H

W G

E

G

CS

RD WR

OPTIONAL

FOR INCREASED

DATA BUS DRIVE

HM-6516

HM-6616

CMOS PROM (2)

2K x 8 2K x 8

CMOS

82CXX

PERIPHERALS

CMOS RAM

2K x 8

FIGURE 6A. MINIMUM MODE 80C86 TYPICAL CONFIGURATION

V_CC

CLK

GND

MRDC

MWTC

AMWC

IORC

MN/MX

S0

CLK

82C84A/85

CLOCK

S0

82C88

S1

BUS

NC

READY

RESET

S1

S2

GENERATOR/

S2 CTRLR

DEN

RES

RDY

IOWC

AIOWC

INTA

80C86

CPU

DT/R

ALE

NC

LOCK

WAIT

STATE

GENERATOR

GND

STB

OE

GND

ADDR/DATA

GND

ADDR

AD0-AD15

A16-A19

1

82C82

(2 OR 3)

C1

V_CC

BHE

GND

20

C2

T

V_CC

40

OE

82C86

TRANSCEIVER

(2)

DATA

C1 = C2 = 0.1µF

A0

BHE

E

G

CS

RDWR

E_H

E_L

W G

HM-6616

CMOS PROM (2)

2K x 8 2K x 8

CMOS

82CXX

PERIPHERALS

HM-65162

CMOS RAM

2K x 8

FIGURE 6B. MAXIMUM MODE 80C86 TYPICAL CONFIGURATION

3-155

80C86

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance (Typical, Note 1)

θ

( C/W)

θ

( C/W)

JA

JC

Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to V +0.5V

CC

PDIP Package . . . . . . . . . . . . . . . . . . .

PLCC Package . . . . . . . . . . . . . . . . . .

SBDIP Package. . . . . . . . . . . . . . . . . .

CLCC Package . . . . . . . . . . . . . . . . . .

50

46

30

40

N/A

6

o

Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C

Junction Temperature

o

Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C

6

o

Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates

o

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C

(Lead tips only for surface mount packages)

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Operating Conditions

o

Operating Supply Voltage. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range: C80C86/-2 . . . . . . . . 0 C to +70 C

M80C86-2 ONLY. . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V

o

I80C86/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 C to +85 C

o

M80C86/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C

o

DC Electrical Speciﬁcations

V

= 5.0V, ±10%; T = 0 C to +70 C (C80C86, C80C86-2)

CC

A

o

= 5.0V, ±10%; T = -40 C to +85 C (l80C86, I80C86-2)

A

o

= 5.0V, ±10%; T = -55 C to +125 C (M80C86)

A

o

= 5.0V, ±5%; T = -55 C to +125 C (M80C86-2)

A

SYMBOL

PARAMETER

MIN

MAX

UNITS

TEST CONDITION

V

Logical One

Input Voltage

2.0

2.2

V

C80C86, I80C86 (Note 5)

M80C86 (Note 5)

lH

V

Logical Zero Input Voltage

CLK Logical One Input Voltage

CLK Logical Zero Input Voltage

Output High Voltage

0.8

V

IL

V

-0.8

CC

IHC

V

ILC

V

3.0

-0.4

V

l

= -2.5mA

= -100µA

OH

V

CC

V

Output Low Voltage

0.4

1.0

V

l

= +2.5mA

OL

I

Input Leakage Current

-1.0

µA

V

= GND or V DIP

IN CC

I

Pins 17-19, 21-23, 33

l

Input Current-Bus Hold High

Input Current-Bus Hold Low

Output Leakage Current

-40

-400

400

-10.0

500

10

µA

V

= - 3.0V (Note 1)

= - 0.8V (Note 2)

BHH

IN

l

40

-

BHL

IN

I

µA

= GND (Note 4)

OUT

O

I

Standby Power Supply Current

Operating Power Supply Current

-

µA

= - 5.5V (Note 3)

CC

CCSB

CCOP

I

-

mA/MHz

FREQ = Max, V = V or GND,

IN CC

Outputs Open

o

Capacitance T = 25 C

A

SYMBOL

PARAMETER

TYPICAL

UNITS

pF

TEST CONDITIONS

C

Input Capacitance

Output Capacitance

I/O Capacitance

25

FREQ = 1MHz. All measurements are referenced to device GND

IN

C

pF

OUT

C

pF

I/O

NOTES:

2. lBHH should be measured after raising V to V and then lowering to 3.0V on the following pins 2-16, 26-32, 34-39.

IN

CC

3. IBHL should be measured after lowering V to GND and then raising to 0.8V on the following pins: 2-16, 34-39.

IN

4. lCCSB tested during clock high time after halt instruction executed. V = V or GND, V = 5.5V, Outputs unloaded.

IN

CC

5. IO should be measured by putting the pin in a high impedance state and then driving V

to GND on the following pins: 26-29 and 32.

OUT

6. MN/MX is a strap option and should be held to V or GND.

CC

3-156

80C86

o

AC Electrical Speciﬁcations

V

= 5.0V ±10%; T = 0 C to +70 C (C80C86, C80C86-2)

CC

A

o

= 5.0V ±100%; T = -40 C to +85 C (I80C86, I80C86-2)

A

o

= 5.0V ±100%; T = -55 C to +125 C (M80C86)

A

o

= 5.0V ±5%; T = -55 C to +125 C (M80C86-2)

A

MINIMUM COMPLEXITY SYSTEM

80C86

80C86-2

MIN

TEST

SYMBOL

PARAMETER

MIN

MAX

UNITS

CONDITIONS

TIMING REQUIREMENTS

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

TCLCL

TCLCH

TCHCL

Cycle Period

200

118

69

125

68

ns

CLK Low Time

CLK High Time

44

TCH1CH2 CLK Rise Time

10

From 1.0V to 3.5V

From 3.5V to 1.0V

TCL2C1

TDVCL

CLK FaIl Time

Data In Setup Time

30

10

35

20

10

35

TCLDX1 Data In Hold Time

TR1VCL

TCLR1X

RDY Setup Time into 82C84A

(Notes 7, 8)

(9)

RDY Hold Time into 82C84A

(Notes 7, 8)

0

ns

(10)

(11)

(12)

(13)

(14)

TRYHCH READY Setup Time into 80C86

TCHRYX READY Hold Time into 80C86

TRYLCL READY Inactive to CLK (Note 9)

118

30

-8

68

20

-8

ns

THVCH

TINVCH

HOLD Setup Time

35

30

20

15

lNTR, NMI, TEST Setup Time

(Note 8)

(15)

(16)

TILIH

TIHIL

Input Rise Time (Except CLK)

Input FaIl Time (Except CLK)

15

ns

From 0.8V to 2.0V

From 2.0V to 0.8V

TIMING RESPONSES

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

TCLAV

TCLAX

TCLAZ

TCHSZ

TCHSV

TLHLL

TCLLH

TCHLL

Address Valid Delay

Address Hold Time

Address Float Delay

Status Float Delay

Status Active Delay

ALE Width

10

110

10

60

ns

C = 100pF

L

C = 100pF

L

TCLAX

80

TCLAX

50

60

C = 100pF

L

C = 100pF

L

10

110

10

C = 100pF

L

TCLCH-20

TCLCH-10

C = 100pF

L

ALE Active Delay

ALE Inactive Delay

80

85

50

55

C = 100pF

L

C = 100pF

L

3-157

80C86

o

AC Electrical Speciﬁcations

V

= 5.0V ±10%; T = 0 C to +70 C (C80C86, C80C86-2)

CC

A

o

= 5.0V ±100%; T = -40 C to +85 C (I80C86, I80C86-2)

A

o

= 5.0V ±100%; T = -55 C to +125 C (M80C86)

A

o

= 5.0V ±5%; T = -55 C to +125 C (M80C86-2) (Continued)

A

MINIMUM COMPLEXITY SYSTEM

80C86

MIN

80C86-2

MIN

TEST

CONDITIONS

SYMBOL

TLLAX

PARAMETER

Address Hold Time to ALE Inactive

Data Valid Delay

MAX

UNITS

ns

(25)

(26)

(27)

(28)

(29)

(30)

(31)

(32)

(33)

(34)

(35)

(36)

(37)

(38)

(39)

(40)

(41)

NOTES:

TCHCL-10

C = 100pF

L

TCLDV

TCLDX2

TWHDX

TCVCTV

10

110

10

60

ns

C = 100pF

L

Data Hold Time

10

ns

C = 100pF

L

Data Hold Time After WR

Control Active Delay 1

TCLCL-30

ns

C = 100pF

L

10

110

10

70

60

70

ns

C = 100pF

L

TCHCTV Control Active Delay 2

10

ns

C = 100pF

L

TCVCTX

TAZRL

TCLRL

TCLRH

TRHAV

TCLHAV

TRLRH

TWLWH

TAVAL

TOLOH

TOHOL

Control Inactive Delay

Address Float to READ Active

RD Active Delay

10

0

10

0

ns

C = 100pF

L

ns

C = 100pF

L

10

165

150

10

100

80

ns

C = 100pF

L

RD Inactive Delay

10

ns

C = 100pF

L

RD Inactive to Next Address Active

HLDA Valid Delay

TCLCL-45

10

TCLCL-40

10

ns

C = 100pF

L

160

100

ns

C = 100pF

L

RD Width

2TCLCL-75

2TCLCL-60

TCLCH-60

2TCLCL-50

2TCLCL-40

TCLCH-40

ns

C = 100pF

L

WR Width

ns

C = 100pF

L

Address Valid to ALE Low

Output Rise Time

ns

C = 100pF

L

20

15

ns

From 0.8V to 2.0V

From 2.0V to 0.8V

Output Fall Time

ns

7. Signal at 82C84A shown for reference only.

8. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

9. Applies only to T2 state (8ns into T3).

3-158

80C86

Waveforms

T1

T2

T3

T4

T_W

(2)

(5)

(1)

TCLCL

TCL2CL1

TCH1CH2

(4)

CLK (82C84A OUTPUT)

(3)

TCHCTV

(30)

TCLCH

TCHCL

(30) TCHCTV

M/IO

(17)

TCLAV

(17)

TCLAV

(26) TCLDV

(18) TCLAX

S7-S3

BHE, A19-A16

TLHLL

BHE/S7, A19/S6-A16/S3

(23) TCLLH

(22)

TLLAX

(25)

ALE

(24)

TR1VCL (8)

TCHLL

V_IH

RDY (82C84A INPUT)

SEE NOTE

TAVAL

(39)

V_IL

(12)

TRYLCL

TCLR1X (9)

(11)

TCHRYX

READY (80C86 INPUT)

(10)

TRYHCH

(7)

TCLDX1

(19)

TCLAZ

(16)

TDVCL

AD15-AD0

DATA IN

(34) TCLRH

AD15-AD0

RD

(35)

TRHAV

(32) TAZRL

(30)

TCHCTV

(30)

TCHCTV

READ CYCLE

(WR, INTA = V_OH

TRLRH

(37)

TCLRL

(33)

)

DT/R

DEN

(29) TCVCTV

TCVCTX

(31)

FIGURE 7A. BUS TIMING - MINIMUM MODE SYSTEM

NOTE: Signals at 82C84A are shown for reference only. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are

to be inserted.

3-159

80C86

Waveforms (Continued)

T1

T2

T3

(5)

TCL2CL1

TW

T4

(4)

TCH1CH2

TW

CLK (82C84A OUTPUT)

(26)

TCLDV

TCLAX

(27)

TCLDX2

(17)

TCLAV

(18)

AD15-AD0

DATA OUT

AD15-AD0

TWHDX

(28)

(29)

TCVCTV

(31) TCVCTX

WRITE CYCLE

DEN

WR

(RD, INTA,

DT/R = V_OH

)

(29) TCVCTV

(38)

TWLWH

TCVCTX

TDVCL

(31)

(6)

(19)

TCLAZ

TCLDX1 (7)

POINTER

AD15-AD0

TCHCTV (30)

TCHCTV

(30)

DT/R

INTA

INTA CYCLE

(SEE NOTE)

(29) TCVCTV

(RD, WR = V_OH

BHE = V_OL

)

TCVCTX

(31)

(29) TCVCTV

DEN

SOFTWARE

HALT -

INVALID ADDRESS

SOFTWARE HALT

AD15-AD0

DEN, RD,

TCLAV

(17)

WR, INTA = V_OH

DT/R = INDETERMINATE

FIGURE 7B. BUS TIMING - MINIMUM MODE SYSTEM

NOTE: Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is ﬂoating during both INTA cycles. Control signals are shown

for the second INTA cycle.

3-160

80C86

o

AC Electrical Speciﬁcations

V

= 5.0V ±10% T = 0 C to +70 C (C80C86, C80C86-2)

CC

A

o

= 5.0V ±10%; T = -40 C to +85 C (I80C86, I80C86-2)

A

o

= 5.0V ±10%; T = -55 C to +125 C (M80C86)

A

o

= 5.0V ±5%; T = -55 C to +125 C (M80C86-2)

A

MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)

TIMING REQUIREMENTS

80C86

MAX

80C86-2

SYMBOL

TCLCL

PARAMETER

CLK Cycle Period

MIN

200

118

69

MIN

MAX

UNITS TEST CONDITIONS

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

125

68

ns

TCLCH

TCHCL

CLK Low Time

CLK High Time

44

TCH1CH2 CLK Rise Time

TCL2CL1 CLK Fall Time

10

ns

From 1.0V to 3.5V

From 3.5V to 1.0V

TDVCL

TCLDX1

TR1VCL

Data in Setup Time

Data In Hold Time

30

10

35

20

10

35

RDY Setup Time into 82C84A

(Notes 10, 11)

(9)

TCLR1X

RDY Hold Time into 82C84A

(Notes 10, 11)

0

ns

(10)

(11)

(12)

(13)

TRYHCH READY Setup Time into 80C86

TCHRYX READY Hold Time into 80C86

118

30

-8

68

20

-8

ns

TRYLCL

TlNVCH

READY Inactive to CLK (Note 12)

Setup Time for Recognition (lNTR,

NMl, TEST) (Note 11)

30

15

(14)

(15)

TGVCH

TCHGX

RQ/GT Setup Time

30

40

15

30

ns

RQ Hold Time into 80C86 (Note 13)

TCHCL+

10

TCHCL+

10

(16)

(17)

TILlH

TIHIL

Input Rise Time (Except CLK)

Input Fall Time (Except CLK)

15

ns

From 0.8V to 2.0V

From 2.0V to 0.8V

TIMING RESPONSES

(18)

(19)

(20)

(21)

(22)

TCLML

Command Active Delay (Note 10)

5

35

5

35

65

60

70

ns

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

TCLMH

Command Inactive (Note 10)

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

TRYHSH READY Active to Status Passive

(Notes 12, 14)

110

130

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

TCHSV

TCLSH

Status Active Delay

10

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

Status Inactive Delay (Note 14)

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

3-161

80C86

o

AC Electrical Speciﬁcations

V

= 5.0V ±10% T = 0 C to +70 C (C80C86, C80C86-2)

CC

A

o

= 5.0V ±10%; T = -40 C to +85 C (I80C86, I80C86-2)

A

o

= 5.0V ±10%; T = -55 C to +125 C (M80C86)

A

o

= 5.0V ±5%; T = -55 C to +125 C (M80C86-2) (Continued)

A

MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)

TIMING REQUIREMENTS

80C86

MAX

80C86-2

SYMBOL

TCLAV

PARAMETER

Address Valid Delay

MIN

MAX

UNITS TEST CONDITIONS

= 100pF for All

(23)

(24)

(25)

(26)

(27)

10

110

10

60

ns

C

L

80C86 Outputs (In

Addition to 80C86

Self Load)

TCLAX

TCLAZ

TCHSZ

TSVLH

Address Hold Time

10

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

Address Float Delay

TCLAX

80

20

30

20

25

18

15

110

TCLAX

50

20

30

20

25

18

15

60

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

Status Float Delay

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

Status Valid to ALE High (Note 10)

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

(28) TSVMCH Status Valid to MCE High (Note 10)

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

(29)

(30)

(31)

(32)

(33)

(34)

TCLLH

CLK low to ALE Valid (Note 10)

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

TCLMCH CLK low to MCE High (Note 10)

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

TCHLL

ALE Inactive Delay (Note 10)

4

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

TCLMCL MCE Inactive Delay (Note 10)

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

TCLDV

Data Valid Delay

Data Hold Time

10

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

TCLDX2

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

3-162

80C86

o

AC Electrical Speciﬁcations

V

= 5.0V ±10% T = 0 C to +70 C (C80C86, C80C86-2)

CC

A

o

= 5.0V ±10%; T = -40 C to +85 C (I80C86, I80C86-2)

A

o

= 5.0V ±10%; T = -55 C to +125 C (M80C86)

A

o

= 5.0V ±5%; T = -55 C to +125 C (M80C86-2) (Continued)

A

MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)

TIMING REQUIREMENTS

80C86

MAX

80C86-2

SYMBOL

TCVNV

PARAMETER

MIN

MAX

UNITS TEST CONDITIONS

(35)

Control Active Delay (Note 10)

5

45

5

45

ns

C

= 100pF for All

L

80C86 Outputs (In

Addition to 80C86

Self Load)

(36)

(37)

(38)

(39)

(40)

TCVNX

TAZRL

TCLRL

TCLRH

TRHAV

Control Inactive Delay (Note 10)

Address Float to Read Active

RD Active Delay

10

0

45

10

0

45

ns

C = 100pF

L

C = 100pF

L

10

165

150

10

100

80

C = 100pF

L

RD Inactive Delay

C = 100pF

L

RD Inactive to Next Address Active

TCLCL

-45

TCLCL

-40

C = 100pF

L

(41)

(42)

TCHDTL

Direction Control Active Delay

(Note 10)

50

30

50

30

ns

C = 100pF

L

TCHDTH Direction Control Inactive Delay

(Note 10)

C = 100pF

L

(43)

(44)

(45)

TCLGL

TCLGH

TRLRH

GT Active Delay

GT Inactive Delay

RD Width

10

85

0

50

ns

C = 100pF

L

C = 100pF

L

2TCLC

L -75

2TCLC

L -50

C = 100pF

L

(46)

TOLOH

TOHOL

Output Rise Time

Output Fall Time

20

15

ns

From 0.8V to 2.0V

From 2.0V to 0.8V

(47)

NOTES:

10. Signal at 82C84A or 82C88 shown for reference only.

11. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

12. Applies only to T2 state (8ns into T3).

13. The 80C86 actively pulls the RQ/GT pin to a logic one on the following clock low time.

14. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.

3-163

80C86

Waveforms

T₁

T₂

T₃

T₄

(4)

TCH1CH2

(1)

TCLCL

(5)

TCL2CL1 T_W

CLK

(23)

TCLAV

TCLCH

(2)

TCHCL (3)

QS0, QS1

TCLSH

(21) TCHSV

S2, S1, S0 (EXCEPT HALT)

(23) TCLAV

(22)

(33)

(SEE NOTE 17)

TCLDV

TCLAX

TCLAV

(23)

(24)

BHE/S7, A19/S6-A16/S3

TSVLH

BHE, A19-A16

(31)

S7-S3

TCHLL

(27)

TCLLH

(29)

ALE (82C88 OUTPUT)

NOTE

TR1VCL

(8)

RDY (82C84 INPUT)

TCLR1X

(9)

(12) TRYLCL

(11)

TCHRYX

READY 80C86 INPUT)

TRYHSH

(20)

(24)

TCLAX

(10)

TRYHCH

(7)

TCLDX1

(6)

TDVCL

(25)

READ CYCLE

TCLAV

(23)

TCLAZ

AD15-AD0

(37) TAZRL

DATA IN

(39) TCLRH

AD15-AD0

RD

TRHAV

(40)

(42)

TCHDTH

(41) TCHDTL

TRLRH

(45)

TCLRL

(38)

DT/R

TCLML

(18)

TCLMH

(19)

82C88

OUTPUTS

SEE NOTES

15, 16

MRDC OR IORC

(35) TCVNV

DEN

TCVNX

(36)

FIGURE 8A. BUS TIMING - MAXIMUM MODE (USING 82C88)

NOTES:

15. Signals at 82C84A or 82C88 are shown for reference only. RDY is sampled near the end of T2, T3, TW to determine if TW machine states

are to be inserted.

16. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active

high 82C88 CEN.

17. Status inactive in state just prior to T4.

3-164

80C86

Waveforms (Continued)

T1

T2

T3

T4

TW

CLK

TCHSV (21)

(SEE NOTE 20))

TCLDX2

S2, S1, S0 (EXCEPT HALT)

(23)

TCLAV

(22)

TCLDV

TCLAX

(33)

(24)

(34)

WRITE CYCLE

AD₁₅-AD₀

TCLSH

DATA

TCVNX (36)

TCVNV

(35)

DEN

TCLMH

(19)

82C88

OUTPUTS

(18) TCLML

SEE NOTES

18, 19

AMWC OR AIOWC

TCLMH (19)

(18)TCLML

MWTC OR IOWC

INTA CYCLE

AD15-AD0

(SEE NOTES 21, 22)

RESERVED FOR

CASCADE ADDR

(25) TCLAZ

AD15-AD0

(6)

TDVCL

POINTER

TCLDX1 (7)

(32)

TCLMCL

(28) TSVMCH

(41)

TCHDTL

MCE/PDEN

(30) TCLMCH

TCHDTH

(42)

DT/R

82C88 OUTPUTS

SEE NOTES 18, 19

(18) TCLML

INTA

(19) TCLMH

TCVNV

(35)

DEN

TCVNX

(36)

SOFTWARE

HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH

INVALID ADDRESS

AD15-AD0

TCLAV

(23)

S2

TCLSH

(22)

TCHSV

(21)

FIGURE 8B. BUS TIMING - MAXIMUM MODE (USING 82C88)

NOTES:

18. Signals at 82C84A or 82C86 are shown for reference only.

19. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active

high 82C88 CEN.

20. Status inactive in state just prior to T4.

21. Cascade address is valid between first and second INTA cycles.

22. Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is

shown for second INTA cycle.

3-165

80C86

Waveforms (Continued)

ANY

CLK

CYCLE

>0-CLK

CYCLES

CLK

TCLGH

(44)

TGVCH (14)

TCHGX (15)

TCLGL

(43)

TCLGH (44)

(1)

TCLCL

PULSE 2

80C86 GT

RQ/GT

PREVIOUS GRANT

AD15-AD0

PULSE 3

PULSE 1

COPROCESSOR

RELEASE

COPROCESSOR

TCLAZ (25)

TCHSZ (26)

RQ

80C86

COPROCESSOR

TCHSV (21)

(SEE NOTE)

RD, LOCK

BHE/S7, A19/S0-A16/S3

S2, S1, S0

NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.

FIGURE 9. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

≥ 1CLK

CYCLE

1 OR 2

CYCLES

CLK

THVCH (13)

HOLD

HLDA

TCLHAV (36)

TCLAZ (19)

COPROCESSOR

TCHSZ (20)

80C86

TCHSV (21)

AD15-AD0

BHE/S7, A19/S6-A16/S3

RD, WR, M/IO, DT/R, DEN

FIGURE 10. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

ANY CLK CYCLE

CLK

(13)

TINVCH (SEE NOTE)

NMI

INTR

TEST

TCLAV

(23)

TCLAV

(23)

SIGNAL

LOCK

NOTE: Setup requirements for asynchronous signals only to guar-

antee recognition at next CLK.

FIGURE 11. ASYNCHRONOUS SIGNAL RECOGNITION

FIGURE 12. BUS LOCK SIGNAL TIMING (MAXIMUM MODE

ONLY)

3-166

80C86

Waveforms (Continued)

≥ 50µs

V_CC

CLK

(7) TCLDX1

(6) TDVCL

RESET

≥ 4 CLK CYCLES

FIGURE 13. RESET TIMING

AC Test Circuit

OUTPUT FROM

DEVICE UNDER TEST

TEST POINT

C_L(SEE NOTE)

NOTE: Includes stay and jig capacitance.

AC Testing Input, Output Waveform

INPUT

OUTPUT

V_IH+ 20% V_IH

V_OH

V_OL

1.5V

V_IL- 50% V_IL

NOTE: AC Testing: All input signals (other than CLK) must switch between V

-50% V and V

+20% V . CLK must switch between

IHMIN IH

ILMAX

IL

0.4V and V .-0.4 Input rise and fall times are driven at 1ns/V.

CC

3-167

80C86

Burn-In Circuits

MD80C86 CERDIP

C

GND

1

2

3

4

5

6

7

8

9

GND

V_CC40

AD15 39

AD16 38

AD17 37

AD18 36

AD19 35

BHE 34

GND

V_CL

V_CC

RIO

AD14

AD13

AD12

AD11

AD10

AD9

V_CL

RO

V_CC/2

RIO

RO

GND

V_CL

V_CC/2

GND

RIO

RO

GND

V_CL

33

32

31

30

29

28

27

26

25

24

23

22

21

AD8

MX

RD

RO

RI

AD7

V_CC/2

V_CL

10 AD6

11 AD5

12 AD4

13 AD3

14 AD2

15 AD1

16 AD0

17 NMI

18 INTR

19 CLK

20 GND

RQ0

RQ1

LOCK

S2

RO

V_CL

V_CC/2

V_CL

RO

OPEN

S1

RO

S0

OPEN

GND

F₀

QS0

QS2

V_CC/2

GND

TEST

READY

RESET

RI

RC

V_CL

NODE

FROM

GND

A

PROGRAM

CARD

NOTES:

COMPONENTS:

V

= 5.5V ±0.5V, GND = 0V.

1. RI = 10kΩ ±5%, 1/4W

2. RO = 1.2kΩ ±5%, 1/4W

3. RIO = 2.7kΩ ±5%, 1/4W

4. RC = 1kΩ ± 5%, 1/4W

5. C = 0.01µF (Minimum)

CC

Input voltage limits (except clock):

V

(maximum) = 0.4V

IL

(minimum) = 2.6V, V (clock) = (V -0.4V) minimum.

IH

CC

is external supply set to 2.7V ±10%.

CC/2

is generated on program card (V - 0.65V).

CL

CC

Pins 13 - 16 input sequenced instructions from internal hold devices.

F = 100kHz ±10%.

0

Node

= a 40µs pulse every 2.56ms.

A

3-168

80C86

Burn-In Circuits (Continued)

MR80C86 CLCC

C

V_CC

V_CL

44

43 42 41 40

6

5

4

3

2

1

RIO

7

39

38

37

36

35

34

33

32

31

30

29

RO

8

RIO

9

10

11

12

13

14

15

16

17

RO

RI

RIO

RI

RO

18 19 20 21 22 23 24 25 26 27 28

V_CC/2

GND

F₀

A

(FROM PROGRAM CARD)

NOTES:

COMPONENTS:

V

= 5.5V ±0.5V, GND = 0V.

1. RI = 10kΩ ±5%, 1/4W

2. RO = 1.2kΩ ±5%, 1/4W

3. RIO = 2.7kΩ ±5%, 1/4W

4. RC = 1kΩ ± 5%, 1/4W

5. C = 0.01µF (Minimum)

CC

Input voltage limits (except clock):

V

(maximum) = 0.4V

IL

(minimum) = 2.6V, V (clock) = (V -0.4V) minimum.

IH

CC

is external supply set to 2.7V ±10%.

CC/2

is generated on program card (V - 0.65V).

CL

CC

Pins 13 - 16 input sequenced instructions from internal hold devices.

F = 100kHz ±10%.

0

Node

= a 40µs pulse every 2.56ms.

A

3-169

80C86

Metallization Topology

DIE DIMENSIONS:

GLASSIVATION:

249.2 x 290.9 x 19

Type: Nitrox

Thickness: 10kÅ ±2kÅ

METALLIZATION:

Type: Silicon - Aluminum

Thickness: 11kÅ ±2kÅ

WORST CASE CURRENT DENSITY:

1.5 x 10⁵A/cm²

Metallization Mask Layout

80C86

AD11

AD12

AD13 AD14 GND

V_CCAD15 A16/S3 A17/S4 A18/S5

A19/S6

AD10

AD9

BHE/S7

MN/MX

AD8

AD7

RD

RQ/GT0

AD6

AD5

RQ/GT1

AD4

AD3

LOCK

S2

AD2

AD1

AD0

S1

S0

NMI INTR CLK

GND

RESET READY TEST QS1 QS0

3-170

80C86

Instruction Set Summary

INSTRUCTION CODE

MNEMONIC AND DESCRIPTION

7 6 5 4 3 2 1 0

DATA TRANSFER

MOV = MOVE:

Register/Memory to/from Register

Immediate to Register/Memory

Immediate to Register

Memory to Accumulator

Accumulator to Memory

Register/Memory to Segment Register ††

Segment Register to Register/Memory

PUSH = Push:

1 0 0 0 1 0 d w

1 1 0 0 0 1 1 w

1 0 1 1 w reg

mod reg r/m

mod 0 0 0 r/m

data

data if w 1

addr-high

1 0 1 0 0 0 0 w

1 0 1 0 0 0 1 w

1 0 0 0 1 1 1 0

1 0 0 0 1 1 0 0

addr-low

mod 0 reg r/m

Register/Memory

1 1 1 1 1 1 1 1

0 1 0 1 0 reg

0 0 0 reg 1 1 0

mod 1 1 0 r/m

Register

Segment Register

POP = Pop:

Register/Memory

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 reg 1 1 1

mod 0 0 0 r/m

Register

Segment Register

XCHG = Exchange:

Register/Memory with Register

Register with Accumulator

IN = Input from:

1 0 0 0 0 1 1 w

1 0 0 1 0 reg

mod reg r/m

port

Fixed Port

1 1 1 0 0 1 0 w

1 1 1 0 1 1 0 w

Variable Port

OUT = Output to:

Fixed Port

1 1 1 0 0 1 1 w

1 1 1 0 1 1 1 w

1 1 0 1 0 1 1 1

1 0 0 0 1 1 0 1

1 1 0 0 0 1 0 1

1 1 0 0 0 1 0 0

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

1 0 0 1 1 1 0 0

1 0 0 1 1 1 0 1

port

Variable Port

XLAT = Translate Byte to AL

LEA = Load EA to Register2

LDS = Load Pointer to DS

LES = Load Pointer to ES

LAHF = Load AH with Flags

SAHF = Store AH into Flags

PUSHF = Push Flags

POPF = Pop Flags

mod reg r/m

ARITHMETIC

ADD = Add:

Register/Memory with Register to Either

Immediate to Register/Memory

Immediate to Accumulator

ADC = Add with Carry:

0 0 0 0 0 0 d w

1 0 0 0 0 0 s w

0 0 0 0 0 1 0 w

mod reg r/m

mod 0 0 0 r/m

data

data if s:w = 01

data if w = 1

Register/Memory with Register to Either

0 0 0 1 0 0 d w

mod reg r/m

3-171

80C86

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

Immediate to Register/Memory

Immediate to Accumulator

INC = Increment:

7 6 5 4 3 2 1 0

1 0 0 0 0 0 s w

mod 0 1 0 r/m

data

data if s:w = 01

0 0 0 1 0 1 0 w

data if w = 1

Register/Memory

1 1 1 1 1 1 1 w

0 1 0 0 0 reg

mod 0 0 0 r/m

Register

AAA = ASCll Adjust for Add

DAA = Decimal Adjust for Add

SUB = Subtract:

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

Register/Memory and Register to Either

Immediate from Register/Memory

Immediate from Accumulator

SBB = Subtract with Borrow

Register/Memory and Register to Either

Immediate from Register/Memory

Immediate from Accumulator

DEC = Decrement:

0 0 1 0 1 0 d w

1 0 0 0 0 0 s w

0 0 1 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

data if s:w = 01

data if w = 1

0 0 0 1 1 0 d w

1 0 0 0 0 0 s w

0 0 0 1 1 1 0 w

mod reg r/m

mod 0 1 1 r/m

data

data if w = 1

Register/Memory

1 1 1 1 1 1 1 w

0 1 0 0 1 reg

mod 0 0 1 r/m

mod 0 1 1 r/m

Register

NEG = Change Sign

1 1 1 1 0 1 1 w

CMP = Compare:

Register/Memory and Register

Immediate with Register/Memory

Immediate with Accumulator

AAS = ASCll Adjust for Subtract

DAS = Decimal Adjust for Subtract

MUL = Multiply (Unsigned)

IMUL = Integer Multiply (Signed)

AAM = ASCll Adjust for Multiply

DlV = Divide (Unsigned)

0 0 1 1 1 0 d w

1 0 0 0 0 0 s w

0 0 1 1 1 1 0 w

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

1 1 1 1 0 1 1 w

1 1 0 1 0 1 0 0

1 1 1 1 0 1 1 w

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

mod reg r/m

mod 1 1 1 r/m

data

data if s:w = 01

data if w = 1

mod 1 0 0 r/m

mod 1 0 1 r/m

0 0 0 0 1 0 1 0

mod 1 1 0 r/m

mod 1 1 1 r/m

0 0 0 0 1 0 1 0

IDlV = Integer Divide (Signed)

AAD = ASClI Adjust for Divide

CBW = Convert Byte to Word

CWD = Convert Word to Double Word

LOGIC

NOT = Invert

1 1 1 1 0 1 1 w

1 1 0 1 0 0 v w

mod 0 1 0 r/m

mod 1 0 0 r/m

mod 1 0 1 r/m

mod 1 1 1 r/m

mod 0 0 0 r/m

mod 0 0 1 r/m

mod 0 1 0 r/m

SHL/SAL = Shift Logical/Arithmetic Left

SHR = Shift Logical Right

SAR = Shift Arithmetic Right

ROL = Rotate Left

ROR = Rotate Right

RCL = Rotate Through Carry Flag Left

3-172

80C86

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND DESCRIPTION

RCR = Rotate Through Carry Right

AND = And:

7 6 5 4 3 2 1 0

1 1 0 1 0 0 v w

mod 0 1 1 r/m

Reg./Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

TEST = And Function to Flags, No Result:

Register/Memory and Register

Immediate Data and Register/Memory

Immediate Data and Accumulator

OR = Or:

0 0 1 0 0 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 0 0 1 0 w

mod reg r/m

mod 1 0 0 r/m

data

data if w = 1

1 0 0 0 0 1 0 w

1 1 1 1 0 1 1 w

1 0 1 0 1 0 0 w

mod reg r/m

mod 0 0 0 r/m

data

data if w = 1

Register/Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

XOR = Exclusive or:

0 0 0 0 1 0 d w

1 0 0 0 0 0 0 w

0 0 0 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

data if w = 1

Register/Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

STRING MANIPULATION

REP = Repeat

0 0 1 1 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 1 0 1 0 w

mod reg r/m

mod 1 1 0 r/m

data

data if w = 1

1 1 1 1 0 0 1 z

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

MOVS = Move Byte/Word

CMPS = Compare Byte/Word

SCAS = Scan Byte/Word

LODS = Load Byte/Word to AL/AX

STOS = Stor Byte/Word from AL/A

CONTROL TRANSFER

CALL = Call:

Direct Within Segment

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

1 0 0 1 1 0 1 0

disp-low

mod 0 1 0 r/m

offset-low

disp-high

Indirect Within Segment

Direct Intersegment

offset-high

seg-high

seg-low

Indirect Intersegment

1 1 1 1 1 1 1 1

mod 0 1 1 r/m

JMP = Unconditional Jump:

Direct Within Segment

1 1 1 0 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 1 1 1

1 1 1 0 1 0 1 0

disp-low

disp

disp-high

Direct Within Segment-Short

Indirect Within Segment

Direct Intersegment

mod 1 0 0 r/m

offset-low

seg-low

offset-high

seg-high

Indirect Intersegment

1 1 1 1 1 1 1 1

mod 1 0 1 r/m

RET = Return from CALL:

Within Segment

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

Within Seg Adding lmmed to SP

data-low

data-high

3-173

80C86

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

Intersegment

7 6 5 4 3 2 1 0

1 1 0 0 1 0 1 1

Intersegment Adding Immediate to SP

JE/JZ = Jump on Equal/Zero

1 1 0 0 1 0 1 0

0 1 1 1 0 1 0 0

0 1 1 1 1 1 0 0

0 1 1 1 1 1 1 0

0 1 1 1 0 0 1 0

0 1 1 1 0 1 1 0

0 1 1 1 1 0 1 0

0 1 1 1 0 0 0 0

data-low

disp

data-high

JL/JNGE = Jump on Less/Not Greater or Equal

JLE/JNG = Jump on Less or Equal/ Not Greater

JB/JNAE = Jump on Below/Not Above or Equal

JBE/JNA = Jump on Below or Equal/Not Above

JP/JPE = Jump on Parity/Parity Even

JO = Jump on Overflow

disp

JS = Jump on Sign

0 1 1 1 1 0 0 0

0 1 1 1 0 1 0 1

0 1 1 1 1 1 0 1

disp

JNE/JNZ = Jump on Not Equal/Not Zero

JNL/JGE = Jump on Not Less/Greater or Equal

JNLE/JG = Jump on Not Less or Equal/Greater

JNB/JAE = Jump on Not Below/Above or Equal

JNBE/JA = Jump on Not Below or Equal/Above

JNP/JPO = Jump on Not Par/Par Odd

JNO = Jump on Not Overﬂow

JNS = Jump on Not Sign

0 1 1 1 1 1 1 1

0 1 1 1 0 0 1 1

0 1 1 1 0 1 1 1

0 1 1 1 1 0 1 1

0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 1

1 1 1 0 0 0 1 0

1 1 1 0 0 0 0 1

1 1 1 0 0 0 0 0

1 1 1 0 0 0 1 1

disp

LOOP = Loop CX Times

LOOPZ/LOOPE = Loop While Zero/Equal

LOOPNZ/LOOPNE = Loop While Not Zero/Equal

JCXZ = Jump on CX Zero

INT = Interrupt

Type Specified

1 1 0 0 1 1 0 1

1 1 0 0 1 1 0 0

1 1 0 0 1 1 1 0

1 1 0 0 1 1 1 1

type

Type 3

INTO = Interrupt on Overﬂow

IRET = Interrupt Return

PROCESSOR CONTROL

CLC = Clear Carry

1 1 1 1 1 0 0 0

1 1 1 1 0 1 0 1

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 0

CMC = Complement Carry

STC = Set Carry

CLD = Clear Direction

STD = Set Direction

CLl = Clear Interrupt

ST = Set Interrupt

1 1 1 1 1 1 0 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 1 0 0

1 0 0 1 1 0 1 1

1 1 0 1 1 x x x

1 1 1 1 0 0 0 0

HLT = Halt

WAIT = Wait

ESC = Escape (to External Device)

LOCK = Bus Lock Prefix

mod x x x r/m

3-174

80C86

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

7 6 5 4 3 2 1 0

NOTES:

AL = 8-bit accumulator

AX = 16-bit accumulator

if s:w = 01 then 16-bits of immediate data form the operand.

if s:w. = 11 then an immediate data byte is sign extended

to form the 16-bit operand.

CX = Count register

if v = 0 then “count” = 1; if v = 1 then “count” in (C )

L

DS= Data segment

x = don't care

ES = Extra segment

z is used for string primitives for comparison with ZF FLAG.

Above/below refers to unsigned value.

Greater = more positive;

Less = less positive (more negative) signed values

if d = 1 then “to” reg; if d = 0 then “from” reg

if w = 1 then word instruction; if w = 0 then byte

instruction

if mod = 11 then r/m is treated as a REG ﬁeld

if mod = 00 then DISP = O†, disp-low and disp-high

are absent

if mod = 01 then DISP = disp-low sign-extended

16-bits, disp-high is absent

if mod = 10 then DISP = disp-high:disp-low

if r/m = 000 then EA = (BX) + (SI) + DISP

if r/m = 001 then EA = (BX) + (DI) + DISP

if r/m = 010 then EA = (BP) + (SI) + DISP

if r/m = 011 then EA = (BP) + (DI) + DISP

if r/m = 100 then EA = (SI) + DISP

if r/m = 101 then EA = (DI) + DISP

if r/m = 110 then EA = (BP) + DISP †

if r/m = 111 then EA = (BX) + DISP

DISP follows 2nd byte of instruction (before data

if required)

SEGMENT OVERRIDE PREFIX

001 reg 11 0

REG is assigned according to the following table:

16-BIT (w = 1)

000 AX

001 CX

010 DX

011 BX

100 SP

101 BP

110 SI

8-BIT (w = 0)

000 AL

SEGMENT

00 ES

01 CS

10 SS

11 DS

00 ES

001 CL

010 DL

011 BL

100 AH

101 CH

110 DH

111 BH

111 DI

Instructions which reference the flag register file as a 16-bit

object use the symbol FLAGS to represent the file:

FLAGS =

†

except if mod = 00 and r/m = 110 then

EA = disp-high: disp-low.

X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)

Mnemonics Intel, 1978

†† MOV CS, REG/MEMORY not allowed.

3-175


型号：	LS80C86
厂家：	Intersil
描述：	CMOS 16-Bit Microprocessor CMOS 16位微处理器微处理器
文件：	总35页 (文件大小：341K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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