LS8297CT [LSI]
STEPPER MOTOR CONTROLLER; 步进电机控制器
| 型号： | LS8297CT |
| 厂家： | 
LSI COMPUTER SYSTEMS |
| 描述： | STEPPER MOTOR CONTROLLER |
| 文件： | 总8页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LS8297
LS8297CT
LSI/CSI
U
® L
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
A3800
April 2009
STEPPER MOTOR CONTROLLER
FEATURES:
PIN ASSIGNMENT
TOP VIEW
• Controls Bipolar and Unipolar Motors
• Cost-effective, low current, pin compatible replacement for L297
• Torque ripple compensated half-steps - LS8297CT
• Half and full step modes
20
19
SYNC
1
RESET
• Normal/wave drive
• Direction control
• Reset input
• Step control input
V
SS
2
3
HALF/FULL
HOME
18
17
STEP
• Enable input
FWD/REV
• PWM chopper circuit for current control
• Two over current sensor comparators with external references input
• All inputs and outputs TTL/CMOS compatible (TTL for 5V operation)
• Supply current < 400uA
• 4.75 to 7V Operation (VDD – VSS).
• LS8297 (DIP), LS8297-S (SOIC), LS8297-TS (TSSOP)
LS8297CT (DIP), LS8297CT-S (SOIC), LS8297CT-TS (TSSOP)
– See Figure 1 –
4
5
6
PHA
INH1
OSC
16
15
VREF
PHB
PHC
7
8
14 SENSE1
INH2
13
12
SENSE2
DESCRIPTION:
9
VDD
PHD
The LS8297 Stepper Motor Controller generates four phase drive signal
outputs for controlling two phase Bipolar and four phase Unipolar mo-
tors. The outputs are used to drive two H-bridges for the two motor
windings in the Bipolar motor or the four driver transistors for the two
center- tapped windings in the Unipolar motor. The motor can be driven
in full step mode either in normal drive (two-phase-on) or wave drive
(one-phase-on) and half step mode. The LS8297 provides two inhibit
outputs which are used to control the driver stages of each of the motor
phases. The circuit uses STEP, FRD/REV and HALF/FULL inputs in a
translator to generate controls for the output stages.
10
11 CONTROL
ENABLE
FIGURE 1
current in either half of the center tapped motor winding recir-
culates through the diode across it.
LS8297CT is the torque ripple compensated version of the
LS8297. Torque imbalance resulting from alternating “one-
phase on”, “two-phase on” sequence of the half-step mode
(see Figure 4) is eliminated in the LS8297CT by switching the
sense reference voltage between 100% and 70.7% in alter-
nate steps.
A dual PWM chopper circuit using an on-chip oscillator, latches and volt-
age comparators are used to regulate the current in the motor windings.
For each pair of phase driver outputs (PHA, PHB, and PHC, PHD) each
pulse of the common internal oscillator sets the latch and enables the
output. If the current in the motor winding causes the voltage across a
sense resistor to exceed the reference voltage, VREF, at the comparator
inputs, the latch is reset disabling the output until the next oscillator
pulse.
INPUT/OUTPUT DESCRIPTION:
OSC Input
An RC input with the resistor connected to VDD and the ca-
pacitor connected to ground determines the oscillator chopper
rate. When connected as an oscillator, the oscillator output
appears as a negative-going pulse at the Sync pin. If the Os-
cillator pin is tied to ground, the Sync pin becomes an input.
Osc frequency, fosc = 1/0.69RC
The CONTROL input determines whether the chopper acts on the
phase driver outputs or the inhibit outputs. When the phase lines are
chopped, the non-active phase line of each pair (PHA, PHB or PHC,
PHD) is activated rather than de-activating the active line to reduce dis-
sipation in the load sensing resistors. Refer to Figure 5B for Bipolar mo-
tors. If PHA is high and PHB is low, current flows through Q1, motor
winding, Q4 and sense resistor Rs. When chopping occurs, PHB is
brought high and circulating current flows through Q1 and D3 and not
through Rs resulting in less power dissipation in Rs. Current decay is
slow using this method. When the Control input is brought low, chopping
occurs by bringing INH1 low. In this case circulating current flows
through D2, motor winding and D3 and through the power supply to
ground causing the current to decay rapidly. For Unipolar motors, only
inhibit chopping is used. Refer to Figure 6. When INH1 is brought low
SYNC
As an output the Sync can be used to drive Sync pins of other
LS8297s. This eliminates the need for RC components for
any other LS8297 controllers used in the system. As an input
the Sync can be driven by the LS8297 that has the RC oscilla-
tor components or by any other system external clock.
8297-042009-1
PHA/PHB/PHC/PHD
STEP Input
Phase drive output signals for power stages. In a Bipolar motor An active low pulse on this input causes the motor to ad-
PHA and PHB are used for one H-bridge while PHC and PHD vance one step. The step occurs on the rising edge of the
are used for the other.
step signal.
INH1/INH2 Outputs
FRD/REV Input
These outputs are active low inhibit controls for motor drive A logic 1 on this input causes the motor to advance through
outputs. INH1 controls driver stage using PHA and PHB sig- the stepping sequence of Fig. 4. A logic 0 on this input cause
nals while INH2 control driver stage using PHC and PHD sig- the motor to reverse the sequence.
nals. When the Control input is low, these outputs are chopped
using the internal oscillator for current regulating.
RESET Input
An active low on this input cause the motor to be restored to
the home position (0101).
CONTROL Input
When high, the phase outputs, PHA, PHB, PHC and PHD are
chopped. When low, INH1 and INH2 are chopped. Normally, HALF/FULL Input
inhibit outputs are chopped. Phase chopping might be used When high, half-step operation is selected. When low, full-
with a Bipolar motor that does not store much energy to pre- step operation is selected. One-phase on full step is selected
vent fast current decay and a low useful torque.
by selecting full when stepping sequence is at an even state.
Two-phase on full step operation is selected when stepping
sequence is at an odd state. Refer to Figure 4.
ENABLE Input
When Enable input is low, INH1, INH2, PHA, PHB, PHC and
PHD are brought low.
SENSE1/ SENSE2 Inputs
Inputs for load current sense voltages from power stages us-
ing PHA and PHB drive signals or PHC and PHD drive sig-
HOME Output
An open drain output that indicates when the LS8297 is in its nals, respectively.
initial state with PHA, PHB, PHC, PHD = logic states 0101 re-
spectively. Refer to Figure 4. In the active state the open drain VREF
device is off.
Reference voltage for chopper circuit which determines the
peak load current.
VDD
V
SS
PHA INH1 PHB PHC INH2 PHD
12
2
4
5
6
7
8
9
+ V
19
20
HALF/FULL
RESET
10
11
ENABLE
TRANSLATOR
OUTPUT LOGIC
CONTROL
FWD/REV
17
Q
S
S
Q
FF1
FF2
R
R
18
3
STEP
1
SYNC
+
-
+
-
x0.707
HOME
OSC
16
MUX
15
14
SENSE1
13
V
REF
SENSE2 OSC
FIGURE 2. LS8297/LS8297CT BLOCK DIAGRAM
8297-091608-2
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VS
Vi
Supply Voltage
Input Signals
10
7
V
V
TSTG, TJ
Storage and Junction Temperatures
-40 to +150
°C
ELECTRICAL CHARACTERISTICS: (Refer to Block Diagram, Figure 2, and Timing Diagram, Figure 3)
TA = +25°C, VDD = +5V unless otherwise specified.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Condition
(Pin 12)
Supply Voltage
Quiscent Supply Current
VDD
IDD
4.75
-
-
7
400
V
uA
-
300
Outputs floating
(Pins 11, 17, 18, 19, 20)
Input Voltage Low
Input Voltage High
Input Current
VIL
VIH
II
0
2
-
-
-
-
-
0.75
VDD
50
V
V
nA
nA
-
-
VI = VIL
VI = VIH
Input Current
II
-
50
(Pin 10)
Enable Input Voltage Low
Enable Input Voltage High VENH
Enable Input Current
Enable Input Current
VENL
0
2
-
-
-
-
-
1.3
VDD
50
V
V
nA
nA
-
-
IEN
IEN
VEN = VENL
VEN = VENH
-
50
(Pins 4, 6, 7, 9)
Phase Output Voltage Low VOL
Phase Output Voltage High VOH
-
-
-
0.5
-
V
V
IO = -10mA
IO = 5mA
4.0
(Pins 5, 8)
Inhibit Output Voltage Low VInhL
Inhibit Output Voltage High VInhH
-
-
-
0.5
-
V
V
IO = -10mA
IO = 5mA
4.0
(Pin 3)
Leakage Current
Saturation Voltage
ILeak
VSat
-
-
-
-
1
0.4
uA
V
VO = VDO = 7V
I = 5mA
(Pins 13, 14, 15)
Comparators Offset Voltage VOff
-
5
-
-
10
mV
uA
VREF = 1V
-
Comparator Bias Current
IO
100
(Pin 15)
Input Reference Voltage
Input Current
VREF
IREF
0
-
-
-
3
8
V
uA
-
VREF = 3V
Clock Time Step
Pulse Width
tstp
0.5
-
-
us
-
Set up time
tS
1
4
1
1
-
-
-
-
-
-
-
-
us
us
us
us
-
-
-
-
Hold time
tH
Reset time
tR
Reset to Step delay
tRStp
(Pin 16)
Oscillator:
Sawtooth Low
VSOL
VSOH
fOSC
-
-
-
2.1
3.65
30
-
-
-
V
-
Sawtooth High
Frequency
V
-
kHz
R = 22kW, C = 3.3nF
8297-040109-3
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Condition
(Pin 1)
Sync:
Sync Output Voltage Low
Sync Output Voltage High
VSyncL
VSyncH
-
-
-
0.8
-
V
V
IO = -5mA
IO = 5mA
3.0
Sync Input Pulse Width
TSPW
-
-
-
3.3
-
-
-
us
V
R = 22kW, C = 3.3nF
<
Sync Input Switching Point TSSP
2.0
Pin 16 1.0V
<
Sync Input Current
IIS
-425
uA
Pin 16 1.0V, VIN = VDD
STEP
tSTP
FWD/REV
HALF/FULL
tS
tH
RESET
tR
tRSTP
FIGURE 3. Input Timing Diagram
8297-040109-4
1
2
3
4
5
6
7
8
1
2
3
4
5
STEP
1000
4
1001
1010
0010
0110
3
2
5
A
B
6
0001
C
D
0101
7
1
8
INH1
INH2
HOME
0100
FIGURE 4A. HALF-STEP MODE
1
3
5
7
1
3
5
7
1
3
5
7
STEP
1001
1010
4
3
2
5
A
B
6
C
D
7
1
8
0101
INH1
0110
HOME
0
INH2
0
FIGURE 4B. NORMAL DRIVE MODE (TWO-PHASE-ON)
2
4
6
8
2
4
6
8
2
4
6
8
STEP
1000
4
3
2
5
A
B
0010
6
0001
C
D
7
1
8
INH1
INH2
0100
FIGURE 4C. WAVE DRIVE MODE (ONE-PHASE-ON)
FIGURE 4. MOTOR DRIVING SEQUENCES
The LS8297 generates phase sequences for half-step mode, normal drive mode and wave drive mode. Advancing occurs on the positive
edge of the STEP input signal. HOME is defined as PHA, PHB, PHC, PHD being 0101, respectively. The State Diagrams showing the
phase output polarities for all states are shown above for clockwise rotation. For counter clockwise rotation, the sequences are reversed.
RESET restores the phases to 0101 and State 1.
7297-081208-5
5V
VM
VS
4
9
12
V
DD
V
DD
19
5
8
6
INH1
INH2
PHA
HALF/FULL
CONTROL
2
INH1
INH2
PHA
PHB
OUT1
11
20
11
5
RESET
4
6
3
OUT2
OUT3
18
17
STEPPER
MOTOR
WINDINGS
MCU
STEP
7
13
PHB
PHC
FRD/REV
ENABLE
10
7
9
10
12
PHC
PHD
14
OUT4
PHD
LS8297
LS8297CT
L298
16
22k
OSC
VDD
3.3nF
V
SS
14
SENSE1
SENSE2
1
15
8
2
V
SS
13
15
VREF
R
R
Note: The SENSE resistors on L298 should be chosen so that
MAX = V REF/R, where IMAX is the maximum motor winding current.
See Note
I
FIGURE 5A. Typical Application Schematic for a Two-Phase Bipolar Motor Using a Single Motor Driver IC
VM
PHA
INH1
PHB
Q1
Q2
Q3
Q4
D1
D2
D3
D4
SENSE1
R
FIGURE 5B. One half of L298 Drive Stage
8297-040309-6
5V
VM
12
Q1
4
1
2
3
VDD
PHA
6
19
11
HALF/FULL
CONTROL
PHB
INH1
5
74HC08
6
4
5
20
18
RESET
MCU
STEP
Q2
17
10
14
FRD/REV
SENSE1
ENABLE
R
LS8297
LS8297CT
22k
16
VDD
OSC
3.3nF
VM
Q3
7
9
8
PHC
PHD
10
9
8
74HC08
11
INH2
12
13
Q4
13
15
SENSE2
VREF
2
VSS
R
NOTE: Q1, Q2, Q3, Q4 are MOSFET Power Transistors suitable for 5V Gate Drive
Typical P/Ns = IRLZ44N and IRF3708
FIGURE 6. TYPICAL APPLICATION SCHEMATIC FOR A FOUR-PHASE
UNIPOLAR MOTOR USING DISCRETE MOSFET TRANSISTORS
7297-090908-7
+V
1
1
1
SYNC
SYNC
SYNC
R
C
LS8297
LS8297CT
LS8297
LS8297CT
LS8297
LS8297CT
16
16
16
OSC
OSC
OSC
FIGURE 7. Synchronizing Multiple LS8297s
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
7297-041309-8
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