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LS830 [MICROSS]

Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET; 线性系统的超低漏电低漂移单片双路JFET
LS830
型号： LS830
厂家： MICROSS COMPONENTS    MICROSS COMPONENTS
描述：

Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
线性系统的超低漏电低漂移单片双路JFET
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LS830  
MONOLITHIC DUAL  
N-CHANNEL JFET  
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET  
FEATURES  
The LS830 is a high-performance monolithic dual  
ULTRA LOW DRIFT  
ULTRA LOW LEAKGE  
LOW NOISE  
LOW CAPACITANCE  
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)  
| V GS1‐2 / T| ≤ 5µV/°C TYP.  
IG = 80fA TYP.  
en = 70nV/√Hz TYP.  
CISS = 3pF MAX.  
JFET featuring extremely low noise, tight offset voltage  
and low drift over temperature specifications, and is  
targeted for use in a wide range of precision  
instrumentation applications. The LS830 features a 5-  
mV offset and 10-µV/°C drift.  
Maximum Temperatures  
Storage Temperature  
Operating Junction Temperature  
Maximum Voltage and Current for Each Transistor – Note 1  
The 8 Pin P-DIP and 8 Pin SOIC provide ease of  
manufacturing, and the symmetrical pinout prevents  
improper orientation.  
‐65°C to +150°C  
+150°C  
‐VGSS  
‐VDSO  
‐IG(f)  
‐IG  
Gate Voltage to Drain or Source  
Drain to Source Voltage  
Gate Forward Current  
40V  
40V  
10mA  
10µA  
(See Packaging Information).  
LS830 Applications:  
Gate Reverse Current  
Maximum Power Dissipation  
Device Dissipation @ Free Air – Total  
ƒ
ƒ
Wideband Differential Amps  
High-Speed,Temp-Compensated Single-  
Ended Input Amps  
High-Speed Comparators  
Impedance Converters and vibrations  
detectors.  
40mW @ +125°C  
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED  
ƒ
ƒ
SYMBOL  
CHARACTERISTICS VALUE UNITS CONDITIONS  
| V GS1‐2 / T| max.  
DRIFT VS.  
TEMPERATURE  
5
µV/°C  
VDG=10V, ID=30µA  
TA=‐55°C to +125°C  
VDG=10V, ID=30µA  
| V GS1‐2 | max.  
OFFSET VOLTAGE  
25  
mV  
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)  
SYMBOL  
BVGSS  
BVGGO  
CHARACTERISTICS  
Breakdown Voltage  
Gate‐To‐Gate Breakdown  
TRANSCONDUCTANCE  
Full Conduction  
MIN.  
40  
40  
TYP.  
60  
‐‐  
MAX.  
‐‐  
‐‐  
UNITS  
V
V
CONDITIONS  
VDS = 0  
I G= 1nA  
ID=1nA  
ID= 0  
IS= 0  
YfSS  
YfS  
|YFS1‐2 / Y FS|  
70  
50  
‐‐  
300  
100  
0.6  
500  
200  
3
µmho  
µmho  
%
VDG= 10V  
VDG= 10V  
VGS= 0V f = 1kHz  
ID= 30µA f = 1kHz  
Typical Operation  
Mismatch  
DRAIN CURRENT  
Click To Buy  
IDSS  
|IDSS1‐2 / IDSS  
Full Conduction  
Mismatch at Full Conduction  
GATE VOLTAGE  
0.5  
‐‐  
‐‐  
1
10  
5
mA  
%
VDG= 10V  
VGS= 0V  
|
VGS(off) or Vp  
VGS(on)  
Pinchoff voltage  
Operating Range  
GATE CURRENT  
0.6  
‐‐  
2
‐‐  
4.5  
4
V
V
VDS= 10V  
VDS=10V  
ID= 1nA  
ID=30µA  
‐IGmax.  
‐IGmax.  
‐IGSSmax.  
‐IGSSmax.  
IGGO  
Operating  
‐‐  
‐‐  
‐‐  
5
‐‐  
‐‐  
‐‐  
5
0.1  
0.1  
0.2  
0.5  
‐‐  
pA  
nA  
pA  
nA  
pA  
VDG= 10V ID= 30µA  
TA= +125°C  
High Temperature  
At Full Conduction  
High Temperature  
Gate‐to‐Gate Leakage  
OUTPUT CONDUCTANCE  
Full Conduction  
VDS =0  
VGS= 0V, VGS= ‐20V, TA= +125°C  
VGG = 20V  
‐‐  
1
YOSS  
YOS  
‐‐  
‐‐  
‐‐  
‐‐  
5
0.5  
µmho  
µmho  
VDG= 10V  
VDG= 10V  
VGS= 0V  
ID= 30µA  
Operating  
COMMON MODE REJECTION  
CMR  
‐20 log | V GS1‐2/ V DS  
‐20 log | V GS1‐2/ V DS  
NOISE  
|
|
‐‐  
‐‐  
90  
90  
‐‐  
‐‐  
dB  
∆VDS = 10 to 20V  
∆VDS = 5 to 10V  
VDS= 10V VGS= 0V  
f= 100Hz  
ID=30µA  
ID=30µA  
RG= 10MΩ  
NBW= 6Hz  
NF  
en  
Figure  
Voltage  
‐‐  
‐‐  
‐‐  
20  
1
70  
dB  
nV/√Hz  
VDS=10V ID=30µA f=10Hz NBW=1Hz  
CAPACITANCE  
Input  
Reverse Transfer  
Drain‐to‐Drain  
CISS  
CRSS  
CDD  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
3
1.5  
0.1  
pF  
pF  
pF  
VDS= 10V, VGS= 0V, f= 1MHz  
VDS= 10V, VGS= 0V, f= 1MHz  
VDS= 10V, ID=30µA  
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired  
PDIP & SOIC (Top View)  
Available Packages:  
LS830 / LS830 in PDIP & SOIC  
LS830 / LS830 available as bare die  
Please contact Micross for full package and die dimensions  
Tel: +44 1603 788967  
Email: chipcomponents@micross.com  
Web: http://www.micross.com/distribution  
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or  
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.  

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