JANSR2N7272 [INTERSIL]
8A, 100V, 0.180 Ohm, Rad Hard, N-Channel Power MOSFET; 8A ， 100V ， 0.180欧姆，抗辐射， N沟道功率MOSFET
| 型号： | JANSR2N7272 |
| 厂家： | 
Intersil |
| 描述： | 8A, 100V, 0.180 Ohm, Rad Hard, N-Channel Power MOSFET |
| 文件： | 总7页 (文件大小：42K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JANSR2N7272
Formerly FRL130R4
June 1998
8A, 100V, 0.180 Ohm, Rad Hard,
N-Channel Power MOSFET
Features
Description
• 8A, 100V, r
= 0.180Ω
The Intersil Corporation,has designed a series of SECOND
GENERATION hardened power MOSFETs of both N-Chan-
nel and P-Channel enhancement types with ratings from
100V to 500V, 1A to 60A, and on resistance as low as
25mΩ. Total dose hardness is offered at 100K RAD (Si) and
1000K RAD (Si) with neutron hardness ranging from 1E13
for 500V product to 1E14 for 100V product. Dose rate hard-
DS(ON)
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
- Typically Survives 2E12 if Current Limited to I
DSS
DM
ness (GAMMA DOT) exists for rates to 1E9 without current
limiting and 2E12 with current limiting.
• Photo Current
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to exhibit mini-
mal characteristic changes to total dose (GAMMA) and
neutron (n ) exposures. Design and processing efforts are
also directed to enhance survival to dose rate (GAMMA
DOT) exposure.
- 1.5nA Per-RAD(Si)/s Typically
• Neutron
o
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm
2
2
- Usable to 3E14 Neutrons/cm
Also available at other radiation and screening levels. See us
Ordering Information
on
the
web,
Intersil’s
home
page:
http://www.semi.harris.com. Contact your local Intersil
Sales Office for additional information.
PART NUMBER
PACKAGE
TO-205AF
BRAND
JANSR2N7272
JANSR2N7272
Symbol
Die family TA17631.
MIL-PRF-19500/604.
D
G
S
Package
TO-205AF
G
D
S
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 4297.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
2-3
JANSR2N7272
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
JANSR2N7272
UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
100
100
V
V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
o
T
T
= 25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
8
5
A
A
A
V
C
D
D
o
= 100 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
24
±20
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
Maximum Power Dissipation
o
T
T
= 25 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
25
10
W
W
C
T
o
= 100 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
C
T
o
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . I
0.20
24
W/ C
A
A
A
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
8
S
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
24
SM
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T , T
-55 to 150
300
C
JC STG
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
(Distance >0.063in (1.6mm) from Case, 10s Max)
C
L
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.0
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
C
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
SYMBOL
BV
TEST CONDITIONS
= 1mA, V = 0V
MIN
TYP
MAX
-
UNITS
V
I
100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DSS
D
GS
o
V
V
= V
= 1mA
,
T
T
T
T
T
T
T
= -55 C
-
5.0
4.0
-
V
GS(TH)
GS
DS
C
C
C
C
C
C
C
I
D
o
= 25 C
2.0
V
o
= 125 C
1.0
-
V
o
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
V
V
= 80V,
DS
= 25 C
25
µA
µA
nA
nA
V
DSS
= 0V
GS
o
= 125 C
-
250
100
200
1.51
0.180
0.360
35
o
I
V
= ±20V
= 25 C
-
GSS
GS
o
= 125 C
-
Drain to Source On-State Voltage
Drain to Source On Resistance
V
V
= 10V, I = 8A
-
DS(ON)
GS
D
o
r
I
= 5A,
T
T
= 25 C
-
Ω
DS(ON)
D
C
C
V
= 10V
GS
o
= 125 C
-
Ω
Turn-On Delay Time
t
V
R
R
= 50V, I = 8A,
-
ns
ns
ns
ns
nC
nC
nC
nC
nC
d(ON)
DD
D
= 6.3Ω, V = 10V,
L
GS
Rise Time
t
-
210
200
145
142
76
r
= 25Ω
GS
Turn-Off Delay Time
t
-
d(OFF)
Fall Time
t
-
f
Total Gate Charge (Not on slash sheet)
Gate Charge at 10V
Q
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
= 50V,
-
g(TOT)
GS
DD
= 8A
I
D
Q
V
-
g(10)
g(TH)
GS
Threshold Gate Charge (Not on slash sheet)
Gate Charge Source
Q
V
-
4
GS
Q
-
13
gs
gd
Gate Charge Drain
Q
-
38
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
-
5.0
175
C/W
JC
JA
θ
o
R
-
C/W
θ
2-4
JANSR2N7272
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
0.6
-
TYP
MAX
1.8
UNITS
V
V
I
I
= 8A
-
-
SD
SD
t
= 8A, dI /dt = 100A/µs
450
ns
rr
SD
SD
o
Electrical Specifications up to 100K RAD T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 0, I = 1mA
MIN
MAX
-
UNITS
Drain to Source Breakdown Volts (Note 3)
V
100
V
V
DSS
GS
D
Gate to Source Threshold Volts
Gate to Body Leakage
(Note 3)
V
V
= V , I = 1mA
DS
2.0
4.0
GS(TH)
GS
D
(Notes 2, 3)
(Note 3)
I
V
= ±20V, V
= 0V
= 80V
-
-
-
-
100
25
nA
µA
V
GSS
GS DS
Zero Gate Leakage
I
V
= 0, V
DSS
GS
DS
= 10V, I = 8A
Drain to Source On-State Volts
Drain to Source On Resistance
(Notes 1, 3)
(Notes 1, 3)
V
V
1.51
0.180
DS(ON)
DS(ON)
GS
D
r
V
= 10V, I = 5A
Ω
GS
D
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 10V, V
DS
= 0V and V
GS
= 0V, V
= 80% BV
.
DS
DSS
Typical Performance Curves Unless Otherwise Specified
100
10
o
T
= 25 C
C
8
100µs
10
6
1ms
4
10ms
1
OPERATION IN THIS
AREA MAY BE
2
0
100ms
LIMITED BY r
DS(ON)
0.1
-50
0
50
100
150
1
10
100
o
T
, CASE TEMPERATURE ( C)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
C
FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 2. FORWARD BIAS SAFE OPERATING AREA
1
0.5
0.2
0.1
0.05
0.1
0.01
P
0.02
0.01
DM
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
PEAK T = P
J
t
t
1
2
1
2
+ T
x Z
DM
JC
C
θ
0.001
-5
-4
10
-3
-2
-1
0
1
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
2-5
JANSR2N7272
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I IS REACHED
AS
V
DS
L
BV
DSS
+
I
-
CURRENT
TRANSFORMER
t
P
AS
V
DS
I
AS
V
DD
VARY t TO OBTAIN
P
+
50Ω
REQUIRED PEAK I
AS
V
DD
V
≤ 20V
GS
-
50V-150V
DUT
50Ω
t
P
0V
t
AV
FIGURE 4. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 5. UNCLAMPED ENERGY WAVEFORMS
t
ON
t
OFF
t
d(OFF)
V
DD
t
d(ON)
t
t
f
r
R
L
V
DS
90%
90%
V
DS
V
= 10V
GS
10%
10%
DUT
0V
90%
50%
R
GS
50%
V
GS
PULSE WIDTH
10%
FIGURE 6. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 7. RESISTIVE SWITCHING WAVEFORMS
Q
Q
10V
G
Q
GD
GS
V
G
CHARGE
FIGURE 8. BASIC GATE CHARGE WAVEFORM
2-6
JANSR2N7272
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
o
Delta Tests and Limits (JANS) T = 25 C, Unless Otherwise Specified
C
PARAMETER
Gate to Source Leakage Current
Zero Gate Voltage Drain Current
Drain to Source On Resistance
Gate Threshold Voltage
NOTES:
SYMBOL
TEST CONDITIONS
= ±20V
GS
MAX
UNITS
nA
I
V
±20 (Note 4)
±25 (Note 4)
±20% (Note 5)
±20% (Note 5)
GSS
I
V
= 80% Rated Value
o
µA
DSS
DS
r
T
= 25 C at Rated I
D
Ω
DS(ON)
C
V
I
= 1.0mA
V
GS(TH)
D
4. Or 100% of Initial Reading (whichever is greater).
5. Of Initial Reading.
Screening Information
TEST
JANS
Gate Stress
V
= 30V, t = 250µs
GS
Pind
Required
o
Pre Burn-In Tests (Note 6)
Steady State Gate Bias (Gate Stress)
MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25 C)
MIL-STD-750, Method 1042, Condition B
o
V
= 80% of Rated Value, T = 150 C, Time = 48 hours
A
GS
Interim Electrical Tests (Note 6)
All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
o
V
= 80% of Rated Value, T = 150 C, Time = 240 hours
A
DS
PDA
5%
Final Electrical Tests (Note 6)
MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
6. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area
SYMBOL
TEST CONDITIONS
= 80V, t = 10ms
MAX
1.50
24
UNITS
A
SOA
V
DS
Unclamped Inductive Switching
Thermal Response
I
V
= 15V, L = 0.1mH
A
AS
GS(PEAK)
∆V
∆V
t
t
= 10ms; V = 25V; I = 2A
92
mV
mV
SD
SD
H
H
H
Thermal Impedance
= 500ms; V = 25V; I = 1A
190
H
H
H
2-7
JANSR2N7272
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E.
Preconditioning Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi Temp Drain Stress Post Reverse
Bias Delta Data
F. Group A
G. Group B
H. Group C
I. Group D
- Attributes Data Sheet
- Attributes Data Sheet
- Attributes Data Sheet
- Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A
G. Group B
H. Group C
I. Group D
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
2-8
JANSR2N7272
TO-205AF
3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE
ØD
INCHES
MIN
MILLIMETERS
ØD
1
SYMBOL
MAX
0.180
0.021
0.370
0.335
0.105
0.210
0.105
0.020
0.034
0.045
0.560
-
MIN
4.07
0.41
8.89
8.01
2.42
4.83
2.42
0.26
0.72
0.74
12.70
1.91
MAX
4.57
0.53
9.39
8.50
2.66
5.33
2.66
0.50
0.86
1.14
14.22
-
NOTES
P
A
0.160
0.016
0.350
0.315
0.095
0.190
0.095
0.010
0.028
0.029
0.500
0.075
-
2, 3
-
A
Øb
ØD
SEATING
PLANE
h
ØD
e
-
1
L
Øb
4
4
4
-
e
e
1
e
2
e1
h
j
-
o
90
2
k
-
e2
1
3
L
P
3
5
o
45
j
k
NOTES:
1. These dimensions are within allowable dimensions of Rev. E of
JEDEC TO-205AF outline dated 11-82.
2. Lead dimension (without solder).
3. Solder coating may vary along lead length, add typically 0.002
inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.100 inches (2.54mm) from bottom
of seating plane.
5. This zone controlled for automatic handling. The variation in
actual diameter within this zone shall not exceed 0.010 inches
(0.254mm).
6. Lead no. 3 butt welded to stem base.
7. Controlling dimension: Inch.
8. Revision 3 dated 6-94.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
2-9
相关型号：
JANSR2N7278
Power Field-Effect Transistor, 4A I(D), 250V, 0.7ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, HERMETIC SEALED, METAL CAN-3
FAIRCHILD
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