ISL84544IP [INTERSIL]
Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches; 低电压，单电源，双路SPST ， SPDT模拟开关
| 型号： | ISL84544IP |
| 厂家： | 
Intersil |
| 描述： | Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches |
| 文件： | 总16页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL84541, ISL84542, ISL84543, ISL84544
®
Data Sheet
April 2003
FN6016.5
Low-Voltage, Single Supply, Dual SPST,
SPDT Analog Switches
Features
• Drop-in Replacements for MAX4541 - MAX4544,
DG9461, DG9262 - DG9263
The Intersil ISL84541–ISL84544 devices are precision, dual
analog switches designed to operate from a single +2.7V to
+12V supply. Targeted applications include battery powered
equipment that benefit from the devices’ low power
• Fully Specified at 3.3V and 5V Supplies
• Pin Compatible with MAX323 - MAX325
consumption (5µW), low leakage currents (100pA max), and
• ON Resistance (R ) . . . . . . . . . . . . . . . . . . . . . . . . 30Ω
ON
fast switching speeds (t
= 35ns, t = 25ns). Cell phones,
ON
OFF
• R
ON
Matching Between Channels. . . . . . . . . . . . . . . . . .<1Ω
for example, often face ASIC functionality limitations. The
number of analog input or GPIO pins may be limited and
digital geometries are not well suited to analog switch
performance. This family of parts may be used to “mux-in”
additional functionality while reducing ASIC design risk. Some
of the smallest packages are available alleviating board space
limitations, and making Intersil’s newest line of low-voltage
switches an ideal solution.
• Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max)
• Single Supply Operation. . . . . . . . . . . . . . . . . +2.7V to +12V
• Low Power Consumption (P ). . . . . . . . . . . . . . . . . . . .<5µW
D
• Low Leakage Current (Max at 85oC) . . . . . . . . . . . . 10nA
• Fast Switching Action
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ns
ON
The ISL84541/ISL84542/ISL84543 are dual single-
pole/single-throw (SPST) devices. The ISL84541 has two
normally open (NO) switches; the ISL84542 has two normally
closed (NC) switches; the ISL84543 has one NO and one NC
switch and can be used as an SPDT. The ISL84544 is a
committed SPDT, which is perfect for use in 2-to-1 multiplexer
applications.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns
OFF
• Guaranteed Break-Before-Make (ISL84543/ISL84544
only)
• Minimum 2000V ESD Protection per Method 3015.7
• TTL, CMOS Compatible
• Available in SOT-23 Packaging
Table 1 summarizes the performance of this family. For higher
performance, pin compatible versions, see the ISL43120 - 22
and ISL43210 datasheet.
Applications
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
TABLE 1. FEATURES AT A GLANCE
ISL84541 ISL84542 ISL84543 ISL84544
- Pagers
- Laptops, Notebooks, Palmtops
NUMBER OF
SWITCHES
2
2
2
1
• Communications Systems
- Military Radios
SW 1 / SW 2
NO / NO
50Ω
NC / NC NO / NC
50Ω 50Ω
50 / 20ns 50 / 20ns
30Ω 30Ω
SPDT
50Ω
- PBX, PABX
3.3V R
ON
3.3V t
/ t
50 / 20ns
30Ω
50 / 20ns
30Ω
• Test Equipment
- Ultrasound
ON OFF
5V R
ON
- Electrocardiograph
5V t
/ t
35 / 25ns
35 / 25ns 35 / 25ns
35 / 25ns
ON OFF
• Heads-Up Displays
8 Ld PDIP,
8 Ld SOIC,
8 Ld SOT-23,
8 Ld MSOP
8 Ld PDIP,
8 Ld SOIC,
8 Ld SOT-23
8 Ld PDIP,
8 Ld SOIC,
6 Ld SOT-23
PACKAGES
• Audio and Video Switching
• Various Circuits
- +3V/+5V DACs and ADCs
- Sample and Hold Circuits
- Digital Filters
Related Literature
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
- Integrator Reset Circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL84541, ISL84542, ISL84543, ISL84544
Pinouts (Note 1)
ISL84541 (PDIP, SOIC, MSOP)
ISL84541 (SOT-23)
TOP VIEW
TOP VIEW
NO
COM
IN
1
2
3
4
8
7
6
5
V+
IN
NO
1
2
3
4
8
7
6
5
COM
1
1
1
2
1
V+
IN
1
1
IN
COM
GND
2
2
2
GND
COM
NO
2
NO
2
ISL84542 (PDIP, SOIC)
ISL84542 (SOT-23)
TOP VIEW
TOP VIEW
NC
1
2
3
4
8
7
6
5
COM
NC
1
1
2
3
4
8
7
6
5
V+
IN
1
1
V+
COM
IN
1
1
2
1
IN
2
IN
GND
COM
2
COM
GND
NC
2
NC
2
2
ISL84543 (PDIP, SOIC)
ISL84543 (SOT-23)
TOP VIEW
TOP VIEW
NO
1
2
3
4
8
7
6
5
V+
IN
NO
1
2
3
4
8
7
6
5
COM
1
1
1
COM
IN
V+
IN
1
1
1
IN
COM
2
GND
2
2
2
GND
NC
2
COM
NC
2
ISL84544 (PDIP, SOIC)
ISL84544 (SOT-23)
TOP VIEW
TOP VIEW
NO
COM
NC
1
2
3
4
8
7
6
5
V+
IN
IN
V+
1
2
3
6
5
4
NO
COM
NC
NC
NC
GND
GND
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
Pin Descriptions
ISL84541 ISL84542
ISL84543
ISL84544
PIN
FUNCTION
LOGIC SW 1, 2 SW 1, 2 SW 1 SW 2 PIN NC PIN NO
V+
GND
IN
System Power Supply Input (+2.7V to +12V)
Ground Connection
0
1
OFF
ON
ON
OFF
ON
ON
ON
OFF
ON
OFF
OFF
OFF
Digital Control Input
NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V.
COM
NO
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
No Internal Connection
NC
N.C.
2
ISL84541, ISL84542, ISL84543, ISL84544
Ordering Information
PART NO.
(BRAND)
(NOTE 2)
TEMP.
RANGE ( C)
o
PACKAGE
PKG. NO.
E8.3
ISL84541CP
ISL84541CB
ISL84541IP
ISL84541IB
0 to 70
8 Ld PDIP
8 Ld SOIC
8 Ld PDIP
8 Ld SOIC
0 to 70
M8.15
E8.3
-40 to 85
-40 to 85
-40 to 85
M8.15
P8.064
ISL84541IH-T
(541I)
8 Ld SOT-23
Tape and Reel
ISL84541IU
(541I)
-40 to 85
8 Ld MSOP
M8.118
ISL84542CP
ISL84542CB
ISL84542IP
ISL84542IB
0 to 70
0 to 70
8 Ld PDIP
8 Ld SOIC
8 Ld PDIP
8 Ld SOIC
E8.3
M8.15
E8.3
-40 to 85
-40 to 85
-40 to 85
M8.15
P8.064
ISL84542IH-T
(542I)
8 Ld SOT-23
Tape and Reel
ISL84543CP
ISL84543CB
ISL84543IP
ISL84543IB
0 to 70
0 to 70
8 Ld PDIP
8 Ld SOIC
8 Ld PDIP
8 Ld SOIC
E8.3
M8.15
E8.3
-40 to 85
-40 to 85
-40 to 85
M8.15
P8.064
ISL84543IH-T
(543I)
8 Ld SOT-23
Tape and Reel
ISL84544CP
ISL84544CB
ISL84544IP
ISL84544IB
0 to 70
0 to 70
8 Ld PDIP
8 Ld SOIC
8 Ld PDIP
8 Ld SOIC
E8.3
M8.15
E8.3
-40 to 85
-40 to 85
-40 to 85
M8.15
P6.064
ISL84544IH-T
(544I)
6 Ld SOT-23
Tape and Reel
NOTES:
2. Most surface mount devices are available on tape and reel; add
“-T” to suffix.
3
ISL84541, ISL84542, ISL84543, ISL84544
Absolute Maximum Ratings
Thermal Information
o
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
Input Voltages
IN (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
NO, NC (Note 3) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 10mA
Peak Current, IN, NO, NC, or COM
Thermal Resistance (Typical, Note 4)
θ
( C/W)
JA
6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . .
8 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . .
8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . .
8 LD SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . .
8 LD PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . .
230
215
210
170
140
o
Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C
Moisture Sensitivity (See Technical Brief TB363)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA
ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV
All Other Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
8 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
o
o
Maximum Storage Temperature Range. . . . . . . . . . . . -65 C to 150 C
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
Operating Conditions
(SOIC, MSOP and SOT-23 - Lead Tips Only)
Temperature Range
ISL8454XCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
ISL8454XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
4. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Note 5),
INL
INH
TEMP
o
MIN
(NOTE 6)
MAX
(NOTE 6) UNITS
PARAMETER
TEST CONDITIONS
( C)
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
Full
25
0
-
-
V+
60
75
2
V
Ω
ANALOG
ON Resistance, R
V+ = 4.5V, I
= 1.0mA, V or V
NO NC
= 3.5V,
30
ON
COM
See Figure 5
Full
25
-
-
Ω
R
Matching Between Channels, V+ = 5V, I
= 1.0mA, V or V = 3.5V
NO NC
-
0.8
Ω
ON
∆R
COM
ON
Full
Full
25
-
-
4
Ω
R
Flatness, R
V+ = 5V, I
= 1.0mA, V
or V = 1V, 2V, 3V
NC
-
7
8
Ω
ON
FLAT(ON)
COM
NO
NO or NC OFF Leakage Current,
or I
V+ = 5.5V, V
Note 7
= 1V, 4.5V, V
or V
= 4.5V, 1V,
-0.1
-5
-0.1
-5
-0.2
-10
0.01
0.1
5
nA
nA
nA
nA
nA
nA
COM
COM
COM
NO
NC
I
NO(OFF)
NC(OFF)
Full
25
-
-
-
-
-
COM OFF Leakage Current,
V+ = 5.5V, V
Note 7
= 4.5V, 1V, V
or V
= 1V, 4.5V,
0.1
5
NO
NC
I
COM(OFF)
Full
25
COM ON Leakage Current,
V+ = 5.5V, V
4.5V, or Floating, Note 7
= 1V, 4.5V, or V
or V
= 1V,
NC
0.2
10
NO
I
COM(ON)
Full
4
ISL84541, ISL84542, ISL84543, ISL84544
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V
Unless Otherwise Specified (Continued)
= 2.4V, V
= 0.8V (Note 5),
INL
INH
TEMP
o
MIN
(NOTE 6)
MAX
(NOTE 6) UNITS
PARAMETER
TEST CONDITIONS
( C)
TYP
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V
or V
= 3V, R =1kΩ, C = 35pF, V = 0 to 3V,
IN
25
Full
25
-
-
35
-
100
240
75
ns
ns
ns
ns
ns
ON
NO
NC
L
L
See Figure 1
Turn-OFF Time, t
V
or V
= 3V, R =1kΩ, C = 35pF, V = 0 to 3V,
-
25
-
OFF
NO
NC
L
L
IN
See Figure 1
Full
Full
-
150
-
Break-Before-Make Time Delay
R = 300Ω, C = 35pF, V
= V = 3V, V = 0 to 3V,
NC IN
2
10
L
L
NO
(ISL84543, ISL84544), t
Charge Injection, Q
OFF Isolation
See Figure 3
D
C
R
R
= 1.0nF, V = 0V, R = 0Ω, See Figure 2
25
25
25
25
25
-
-
-
-
-
1
76
-90
8
5
-
pC
dB
dB
pF
pF
L
L
L
G
G
= 50Ω, C = 5pF, f = 1MHz, See Figure 4
L
Crosstalk (Channel-to-Channel)
= 50Ω, C = 5pF, f = 1MHz, See Figure 6
-
L
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V, See Figure 7
= 0V, See Figure 7
-
OFF
NO
NO
NC
COM
COM
COM OFF Capacitance,
8
-
NC
C
COM(OFF)
COM ON Capacitance, C
f = 1MHz, V
ISL84541/2/3
or V
= V
= V
= 0V, See Figure 7,
= 0V, See Figure 7,
25
25
-
-
13
20
-
-
pF
pF
COM(ON)
NO
NC
NC
COM
COM
f = 1MHz, V
ISL84544
or V
NO
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
Full
2.7
-1
12
1
V
Positive Supply Current, I+
V+ = 5.5V, V = 0V or V+, all channels on or off
IN
0.0001
µA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
-
-
-
0.8
-
V
V
INL
Input Voltage High, V
2.4
INH
NOTES:
5. V = input voltage to perform proper function.
IN
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
o
7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25 C.
5
ISL84541, ISL84542, ISL84543, ISL84544
Electrical Specifications - 3.3V Supply
Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, V
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Note 5),
INL
INH
TEMP
( C)
MIN
(NOTE 6)
MAX
(NOTE 6) UNITS
o
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
Full
25
0
-
V+
80
140
2
V
Ω
ANALOG
ON Resistance, R
V+ = 3V, I
= 1.0mA, V
or V = 1.5V
NC
-
-
50
ON
COM
NO
Full
25
-
Ω
R
Matching Between Channels, V+ = 3.3V, I
COM
= 1.0mA, V
NO
or V
NC
= 1.5V
-
0.8
Ω
ON
∆R
ON
Full
25
-
-
4
Ω
R
Flatness, R
V+ = 3.3V, I
1V, 1.5V
= 1.0mA, V or V
NO NC
= 0.5V,
-
6
10
12
0.1
5
Ω
ON
FLAT(ON)
COM
Full
25
-
7
Ω
NO or NC OFF Leakage Current,
or I
V+ = 3.6V, V
Note 7
= 1V, 3V, V
or V
= 3V, 1V,
= 1V, 3V,
-0.1
-5
-0.1
-5
-0.2
-10
0.01
nA
nA
nA
nA
nA
nA
COM
COM
COM
NO
NO
NC
NC
I
NO(OFF)
NC(OFF)
Full
25
-
COM OFF Leakage Current,
V+ = 3.6V, V
Note 7
= 3V, 1V, V
or V
0.01
0.1
5
I
COM(OFF)
Full
25
-
-
-
COM ON Leakage Current,
V+ = 3.6V, V
or floating, Note 7
= 1V, 3V, or V
or V
= 1V, 3V,
NC
0.2
10
NO
I
COM(ON)
Full
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V
V
or V
or V
= 1.5V, R =1kΩ, C = 35pF, V = 0 to 3V
IN
25
Full
25
-
50
120
200
50
ns
ns
ns
ns
ns
ON
NO
NO
NC
NC
L
L
Turn-OFF Time, t
= 1.5V, R =1kΩ, C = 35pF, V = 0 to 3V
-
-
20
-
OFF
L
L
IN
Full
Full
120
-
Break-Before-Make Time Delay
R
= 300Ω, C = 35pF, V
or V
= 1.5V,
3
30
L
L
NO
NC
(ISL84543, ISL84544), t
Charge Injection, Q
OFF Isolation
V
C
R
= 0 to 3V
D
IN
= 1.0nF, V = 0V, R = 0Ω
25
25
25
25
25
-
-
-
-
-
1
76
-90
8
5
-
pC
dB
dB
pF
pF
L
L
G
G
= 50Ω, C = 5pF, f = 1MHz
L
Crosstalk (Channel-to-Channel)
-
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V
= 0V
-
OFF
NO
NO
NC
COM
COM
COM OFF Capacitance,
8
-
NC
C
COM(OFF)
COM ON Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V, ISL84541/2/3
= 0V, ISL84544
25
25
-
-
13
20
-
-
pF
pF
COM(ON)
NO
NO
NC
COM
COM
NC
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 3.6V, V = 0V or V+, all channels on or off
IN
Full
-1
-
1
µA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.8
-
V
V
INL
Input Voltage High, V
2.4
-1
INH
Input Current, I
, I
V+ = 3.6V, V = 0V or V+
IN
1
µA
INH INL
6
ISL84541, ISL84542, ISL84543, ISL84544
Test Circuits and Waveforms
V+
3V
t < 20ns
r
t < 20ns
f
C
LOGIC
INPUT
50%
0V
t
V
OFF
OUT
NO or NC
IN
SWITCH
INPUT
COM
SWITCH
INPUT
V
NO
V
OUT
90%
90%
C
L
35pF
R
1kΩ
LOGIC
INPUT
L
GND
SWITCH
OUTPUT
0V
t
ON
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
------------------------------
V
= V
OUT
(NO or NC)
R
+ R
(ON)
L
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
SWITCH
OUTPUT
∆V
OUT
V
R
OUT
G
COM
NO or NC
GND
V
OUT
V+
0V
ON
ON
LOGIC
INPUT
V
OFF
G
IN
C
L
LOGIC
INPUT
Q = ∆V
x C
L
OUT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
3V
0V
LOGIC
INPUT
V
OUT1
NO1
NC2
V
NX
COM
1
C
V
R
L1
L1
35pF
OUT2
90%
SWITCH
OUTPUT
300Ω
COM
2
V
0V
OUT1
IN
IN
1
2
R
C
L2
300Ω
L2
35pF
90%
SWITCH
OUTPUT
LOGIC
INPUT
V
OUT2
0V
GND
t
t
D
D
C
includes fixture and stray capacitance.
L
FIGURE 3B. TEST CIRCUIT (ISL84543 ONLY)
FIGURE 3A. MEASUREMENT POINTS (ISL84543 ONLY)
7
ISL84541, ISL84542, ISL84543, ISL84544
Test Circuits and Waveforms (Continued)
V+
C
3V
0V
LOGIC
INPUT
NO
NC
V
V
OUT
NX
COM
C
R
L
L
300Ω
35pF
IN
90%
SWITCH
OUTPUT
GND
LOGIC
INPUT
V
OUT
0V
t
D
C
includes fixture and stray capacitance.
L
FIGURE 3D. TEST CIRCUIT (ISL84544 ONLY)
FIGURE 3. BREAK-BEFORE-MAKE TIME
FIGURE 3C. MEASUREMENT POINTS (ISL84544 ONLY)
V+
V+
C
C
R
= V /1mA
1
ON
SIGNAL
GENERATOR
NO or NC
NO or NC
V
NX
IN
1mA
0V or 2.4V
X
0.8V or 2.4V
IN
V
1
COM
COM
ANALYZER
GND
GND
R
L
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. R
TEST CIRCUIT
ON
V+
C
V+
C
SIGNAL
GENERATOR
50Ω
NO1 or NC1
COM1
NO or NC
IN
1
IN
0V or 2.4V
X
0V or 2.4V
0V or 2.4V
IN
2
IMPEDANCE
ANALYZER
COM
NO2 or NC2
GND
COM2
ANALYZER
NC
GND
R
L
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
8
ISL84541, ISL84542, ISL84543, ISL84544
their analog voltage limits. Unlike switches with a 13V
Detailed Description
maximum supply voltage, the ISL8454X 15V maximum supply
voltage provides plenty of room for the 10% tolerance of 12V
supplies, as well as room for overshoot and noise spikes.
The ISL84541–ISL84544 dual analog switches offer precise
switching capability from a single 2.7V to 12V supply with
low on-resistance (30Ω) and high speed operation
(t
= 35ns, t = 25ns). The devices are especially well
The minimum recommended supply voltage is 2.7V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer to
the electrical specification tables and Typical Performance
curves for details.
ON
OFF
suited to portable battery powered equipment thanks to the
low operating supply voltage (2.7V), low power consumption
(5µW), low leakage currents (100pA max), and the tiny
SOT-23 packaging. High frequency applications also benefit
from the wide bandwidth, and the very high off isolation and
crosstalk rejection.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the logic levels to switched V+ and
GND signals to drive the analog switch gate terminals.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and input signal voltages
must remain between V+ and GND. If these conditions cannot
be guaranteed, then one of the following two protection
methods should be employed.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes negative
in this configuration.
Logic-Level Thresholds
This switch family is TTL compatible (0.8V and 2.4V) over a
supply range of 3V to 11V (see Figure 15). At 12V the V
IH
level is about 2.5V. This is still below the TTL guaranteed
high output minimum level of 2.8V, but noise margin is
reduced. For best results with a 12V supply, use a logic
Logic inputs can easily be protected by adding a 1kΩ resistor
in series with the input (see Figure 8). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
family the provides a V
greater than 3V.
OH
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
Adding a series resistor to the switch input defeats the
purpose of using a low R
switch, so two small signal diodes
High-Frequency Performance
ON
can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
In 50Ω systems, signal response is reasonably flat even past
300MHz (see Figure 16). Figure 16 also illustrates that the
frequency response is very consistent over a wide V+ range,
and for varying analog signal levels.
An off switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation
is the resistance to this feedthrough, while Crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 17 details the high Off Isolation and
Crosstalk rejection provided by this family. At 10MHz, off
isolation is about 50dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease Off Isolation and
Crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load impedance.
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
IN
X
V
V
NO or NC
COM
GND
OPTIONAL PROTECTION
DIODE
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND.
One of these diodes conducts if any analog signal exceeds
V+ or GND.
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL8454X construction is typical of most CMOS analog
switches, except that they have only two supply pins: V+ and
GND. V+ and GND drive the internal CMOS switches and set
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
9
ISL84541, ISL84542, ISL84543, ISL84544
they are reverse biased differently. Each is biased by either
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog-signal
paths and V+ or GND.
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
o
Typical Performance Curves T = 25 C, Unless Otherwise Specified
A
45
40
V+ = 3.3V
40
35
30
25
20
35
30
25
20
15
o
85 C
o
o
25 C
85 C
o
-40 C
15
30
25
V+ = 5V
o
20
15
85 C
o
o
25 C
25 C
o
-40 C
o
10
20
-40 C
10
5
o
85 C
V+ = 12V
o
25 C
15
10
5
3
4
5
6
7
8
9
10
11
12
13
o
-40 C
V+ (V)
0
2
4
6
8
10
12
V
(V)
COM
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
0.5
V+ = 3.3V
60
0.4
0.3
0.2
o
25 C
50
40
30
20
10
0
o
85 C
0.1
0
o
-40 C
0.25
0.2
V+ = 5V
o
25 C
o
V+ = 5V
0.15
85 C
V+ = 12V
0.1
0.05
0
o
85 C
V+ = 3.3V
o
-40 C
0.15
o
V+ = 12V
25 C
0.1
0.05
0
-10
-20
o
o
-40 C
85 C
o
25 C
o
-40 C
0
2
4
6
8
10
12
0
2
4
6
8
10
12
V
(V)
COM
V
(V)
COM
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 11. R
MATCH vs SWITCH VOLTAGE
ON
10
ISL84541, ISL84542, ISL84543, ISL84544
o
Typical Performance Curves T = 25 C, Unless Otherwise Specified (Continued)
A
100
90
80
70
60
50
40
30
20
35
30
25
20
15
o
85 C
o
85 C
o
-40 C
o
-40 C
o
-40 C
o
25 C
o
25 C
2
3
4
5
6
7
8
9
10
11
12
2
3
4
5
6
7
8
9
10
11
12
V+ (V)
V+ (V)
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
V+ = 3.3V to 12V
GAIN
3.0
2.5
2.0
1.5
1.0
0.5
0
-3
-6
V
INH
o
o
0
-40 C
85 C
PHASE
20
40
60
80
o
o
25 C
85 C
o
-40 C
o
25 C
R
= 50Ω
L
V
INL
V
V
V
= 0.2V
= 0.2V
= 0.2V
to 2.5V
to 4V
to 5V
(V+ = 3.3V)
(V+ = 5V)
(V+ = 12V)
IN
IN
IN
P-P
P-P
P-P
P-P
P-P
P-P
o
85 C
100
2
3
4
5
6
7
8
9
10
11
12
13
1
10
100
FREQUENCY (MHz)
600
V+ (V)
FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 16. FREQUENCY RESPONSE
-10
-20
-30
-40
-50
-60
-70
-80
-90
10
20
30
40
50
60
70
80
90
V+ = 3V to 13V
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ISL84541: 66
ISL84542: 66
ISL84543: 66
ISL84544: 58
ISOLATION
PROCESS:
CROSSTALK
Si Gate CMOS
-100
-110
100
110
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 17. CROSSTALK AND OFF ISOLATION
11
ISL84541, ISL84542, ISL84543, ISL84544
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1
2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-C-
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A
A
1
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
English and Metric dimensions, the inch dimensions control.
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
12
ISL84541, ISL84542, ISL84543, ISL84544
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
13
ISL84541, ISL84542, ISL84543, ISL84544
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INDEX
0.25(0.010)
M
L
B M
H
AREA
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
µ
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
14
ISL84541, ISL84542, ISL84543, ISL84544
Small Outline Transistor Plastic Packages (SOT23-6)
P6.064
0.20 (0.008)
C
M
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
C
L
INCHES
MILLIMETERS
e
b
6
L
SYMBOL
MIN
MAX
MIN
0.90
0.00
0.90
0.30
0.09
2.80
2.60
1.50
MAX
1.45
0.15
1.30
0.50
0.20
3.00
NOTES
A
A1
A2
b
0.036
0.000
0.036
0.012
0.0036
0.111
0.103
0.060
0.057
0.0059
0.051
0.020
0.0078
0.118
0.118
0.068
-
5
2
4
3
-
C
C
L
E
E1
-
L
-
1
C
-
D
3
e1
α
E
3.00
1.75
0.95 Ref
1.90 Ref
0.55
-
D
C
E1
e
3
C
L
0.0374 Ref
0.0748 Ref
0.014 0.022
-
e1
L
-
SEATING
PLANE
0.35
4, 5
A2
A1
A
N
6
6
6
-C-
o
o
o
o
0
10
0
10
-
α
Rev. 2 5/01
0.10 (0.004)
C
NOTES:
1. Dimensioning and tolerances per ANSI 14.5M-1982.
2. Package conforms to EIAJ SC-74 (1992).
3. Dimensions D and E1 are exclusive of mold flash, protrusions, or
gate burrs.
4. Footlength L measured at reference to seating plane.
5. “L” is the length of flat foot surface for soldering to substrate.
6. “N” is the number of terminal positions.
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
15
ISL84541, ISL84542, ISL84543, ISL84544
Small Outline Transistor Plastic Packages (SOT23-8)
P8.064
0.20 (0.008) M
C
8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
C
L
e
INCHES
MILLIMETERS
b
8
SYMBOL
MIN
MAX
MIN
0.90
0.00
0.90
0.28
0.09
2.80
2.60
1.50
MAX
1.45
0.15
1.30
0.45
0.20
3.00
3.00
1.75
NOTES
L
A
A1
A2
b
0.036
0.000
0.036
0.011
0.0036
0.111
0.103
0.060
0.057
0.0059
0.051
0.018
0.0078
0.118
0.118
0.068
-
7
2
6
5
4
-
-
C
L
C
L
E
E1
-
1
3
C
-
D
3
e1
D
α
E
-
C
E1
e
3
C
L
0.0256 Ref
0.0768 Ref
0.012 0.020
0.65 Ref
1.95 Ref
0.50
-
e1
L
-
0.30
4, 5
SEATING
PLANE
A2
A1
A
N
8
8
6
-C-
o
o
o
o
0
10
0
10
-
α
Rev. 1 10/01
0.10 (0.004)
C
NOTES:
1. Dimensioning and tolerances per ANSI 14.5M-1982.
2. Package patterned after EIAJ SC-74 (1992).
3. Dimensions D and E1 are exclusive of mold flash, protrusions, or
gate burrs.
4. Footlength L measured at reference to seating plane.
5. “L” is the length of flat foot surface for soldering to substrate.
6. “N” is the number of terminal positions.
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
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相关型号：
ISL84684II
Ultra Low ON-Resistance, Low Voltage, Single Supply, Dual SPDT Analog Switch in Chipscale Package
INTERSIL
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