ISL84581IAZ [INTERSIL]
Low-Voltage, Single and Dual Supply, 8-to-1 Multiplexer; 低电压，单电源和双电源， 8到1多路复用器
| 型号： | ISL84581IAZ |
| 厂家： | 
Intersil |
| 描述： | Low-Voltage, Single and Dual Supply, 8-to-1 Multiplexer |
| 文件： | 总15页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL84581
®
Data Sheet
April 13, 2009
FN6416.3
Low-Voltage, Single and Dual Supply,
8-to-1 Multiplexer
Features
• Fully Specified at 3.3V, 5V, ±5V, and 12V Supplies for 10%
Tolerances
The Intersil ISL84581 device contains precision,
bidirectional, analog switches configured as an 8-to-1
multiplexer/demultiplexer. It was designed to operate from a
single +2V to +12V single supply or from dual ±2V to ±6V
supplies. The device has an inhibit pin to simultaneously
open all signal paths.
• ON-Resistance (r ) Max, V = ±4.5V . . . . . . . . . . . 50Ω
ON
S
• ON-Resistance (r ) Max, V = +3V. . . . . . . . . . . . 155Ω
ON
S
• r
ON
Matching Between Channels, V = ±5V . . . . . . . . .<2Ω
S
• Low Charge Injection, V = ±5V . . . . . . . . . . . . . 1pC (Max)
S
The ISL84581 has an ON-resistance of 39Ω with a dual ±5V
supply and 125Ω with a single +3.3V supply. Each switch
can handle rail-to-rail analog signals. The off-leakage current
is only 0.02nA at +25°C or 0.2nA at +85°C.
• Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V
• Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . ±2V to ±6V
• Fast Switching Action (V = +5V)
S
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38ns
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring
TTL/CMOS logic compatibility when using a single 3.3V or
+5V supply or dual ±5V supplies.
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ns
OFF
• Guaranteed Max Off-leakage . . . . . . . . . . . . . . . . . . .2.5nA
• Guaranteed Break-Before-Make
• TTL, CMOS Compatible
The ISL84581 is a single 8-to-1 multiplexer device. Table 1
summarizes the performance of the part.
TABLE 1. FEATURES AT A GLANCE
• Pb-free (RoHS Compliant)
CONFIGURATION
SINGLE 8:1 MUX
±5V r
ON
39Ω
32ns/18ns
32Ω
Applications
±5V t /t
ON OFF
• Battery Powered, Handheld, and Portable Equipment
12V r
ON
• Communications Systems
- Radios
12V t /t
ON OFF
23ns/15ns
65Ω
- Telecom Infrastructure
- ADSL, VDSL Modems
5V r
ON
5V t /t
ON OFF
38ns/19ns
125Ω
• Test Equipment
3.3V r
ON
- Medical Ultrasound
- Magnetic Resonance Image
- CT and PET Scanners (MRI)
- ATE
3.3V t /t
70ns/32ns
16 Ld TSSOP, 16 Ld QSOP
ON OFF
Package
Related Literature
- Electrocardiograph
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Audio and Video Signal Routing
• Various Circuits
- +3V/+5V DACs and ADCs
- Sample and Hold Circuits
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
• Application Note AN520 “CMOS Analog Multiplexers and
Switches; Specifications and Application Considerations.”
• Application Note AN1034 “Analog Switch and Multiplexer
Applications”
- Integrator Reset Circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007-2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL84581
Pinout
ISL84581
(16 LD TSSOP, QSOP)
TOP VIEW
NO1
NO3
COM
NO7
NO5
INH
1
2
3
4
5
6
7
8
16 V+
15 NO2
14 NO4
13 NO0
12 NO6
11 ADDC
10 ADDB
LOGIC
V-
9
ADDA
GND
NOTE: Switches Shown for Logic “0” Inputs.
Truth Tables
Pin Descriptions
ISL84581
PIN
FUNCTION
INH
0
ADDC
ADDB
ADDA
SWITCH ON
NO0
V+
V-
Positive Power Supply Input
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
Negative Power Supply Input. Connect to GND for
Single Supply Configurations.
0
NO1
GND
INH
Ground Connection
0
NO2
Digital Control Input. Connect to GND for Normal
Operation. Connect to V+ to turn all switches off.
0
NO3
0
NO4
ADDx Address Input Pin
0
NO5
COM
NOx
Analog Switch Common Pin
0
NO6
Analog Switch Normally Open Pin
0
NO7
1
NONE
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V, with V+ between 2.7V and
10V. X = Don’t Care.
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP RANGE
PACKAGE
(Pb-free)
PKG.
DWG. #
(°C)
ISL84581IVZ
84581 IVZ
-40 to +85
-40 to +85
-40 to +85
-40 to +85
16 Ld TSSOP (4.4mm)
M16.173
ISL84581IVZ-T*
ISL84581IAZ
84581 IVZ
84581 IAZ
84581 IAZ
16 Ld TSSOP (4.4mm) Tape and Reel
16 Ld QSOP (4.4mm)
M16.173
M16.15A
M16.15A
ISL84581IAZ-T*
16 Ld QSOP (4.4mm) Tape and Reel
* Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6416.3
April 13, 2009
2
ISL84581
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15V to 0.3V
Input Voltages
INH, NOx, ADDx (Note 1). . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 1). . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . ±30mA
Peak Current NOx, COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA
ESD Rating
Thermal Resistance (Typical, Note 2)
θ
(°C/W)
JA
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
16 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
110
160
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Human Body Model (Per Mil-STD-883, Method 3015.7) . . >2.5kV
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on NOx, COM, ADDx, INH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications ±5V Supply
Test Conditions: V
Unless Otherwise Specified.
= ±4.5V to ±5.5V, GND = 0V, V
INH
= 2.4V, V
= 0.8V (Note 3),
INL
SUPPLY
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 4, 8) TYP (Notes 4, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
(Note 10)
Full
25
V-
-
-
44
V+
60
80
4
V
Ω
ON-Resistance, r
V
= ±4.5V, I
= 2mA, V
= 2mA, V
= 2mA, V
= 3V
ON
S
COM
NO
NO
NO
(See Figure 5)
Full
25
-
-
Ω
r
r
Matching Between Channels, Δr
V
V
= ±4.5V, I
= ±4.5V, I
= 3V (Note 5)
= ±3V, 0.1V
-
1.3
-
Ω
ON
ON
ON
S
S
COM
COM
Full
25
-
6
Ω
Flatness, r
-
7.5
-
9
Ω
FLAT(ON)
(Note 6)
Full
25
-
12
-
Ω
NO OFF Leakage Current, I
V
V
V
= ±5.5V, V
= ±4.5V, V
= ±4.5V, V
= +4.5V (Note 7)
= +4.5V (Note 7)
-
0.02
0.2
0.02
0.2
0.02
0.2
nA
nA
nA
nA
nA
nA
NO(OFF)
S
S
S
COM
COM
COM
NO
NO
Full
25
-
-
COM OFF Leakage Current, I
= ±5.5V, V
= ±5.5V, V
-
-
COM(OFF)
COM(ON)
Full
25
-
-
COM ON Leakage Current, I
= V
= ±4.5V (Note 7)
-
-
NO
Full
-
-
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Input Voltage Low, V
, V
INHH ADDH
Full
Full
Full
2.4
-
-
-
-
-
V
V
, V
INHL ADDL
0.8
0.5
Input Current, I
, I
I
, I
V
= ±5.5V, V , V
INH ADD
= 0V or V+, (Note 9)
-0.5
µA
ADDH ADDL, INHH INHL
S
DYNAMIC CHARACTERISTICS
INHIBIT Turn-ON Time, t
V
V
= ±4.5V, V
= ±3V, R = 300Ω, C = 35pF,
25
Full
25
-
-
-
-
-
-
35
-
50
60
35
40
60
70
ns
ns
ns
ns
ns
ns
ON
S
NO
L
L
= 0 to 3 (See Figure 1, Note 9)
IN
INHIBIT Turn-OFF Time, t
V
V
= ±4.5V, V
NO
= ±3V, R = 300Ω, C = 35pF,
22
-
OFF
S
L
L
= 0 to 3 (See Figure 1, Note 9)
IN
Full
25
Address Transition Time, t
TRANS
V
V
= ±4.5V, V
NO
= ±3V, R = 300Ω, C = 35pF,
43
-
S
L
L
= 0 to 3 (See Figure 1, Note 9)
IN
Full
FN6416.3
April 13, 2009
3
ISL84581
Electrical Specifications ±5V Supply
Test Conditions: V
Unless Otherwise Specified. (Continued)
= ±4.5V to ±5.5V, GND = 0V, V
INH
= 2.4V, V
= 0.8V (Note 3),
INL
SUPPLY
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 4, 8) TYP (Notes 4, 8) UNITS
Break-Before-Make Time, t
V
V
= ±5.5V, V
NO
= 3V, R = 300Ω, C = 35pF,
Full
2
7
-
ns
BBM
S
L
L
= 0 to 3V (See Figure 3, Note 9)
IN
Charge Injection, Q
C = 1.0nF, V = 0V, R = 0Ω (See Figure 2, Note 9)
25
25
25
25
25
-
-
-
-
-
0.3
3
1
-
pC
pF
pF
pF
dB
L
G
G
NO OFF Capacitance, C
f = 1MHz, V
= V
= V
= V
= 0V (See Figure 6)
= 0V (See Figure 6)
= 0V (See Figure 6)
OFF
NO
NO
NO
COM
COM
COM
COM OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
21
26
92
-
OFF
COM ON Capacitance, C
OFF-Isolation
-
COM(ON)
R = 50Ω, C = 15pF, f = 100kHz, V
NOx
= 1V
RMS
-
L
L
(See Figures 4 and 18)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
(Note 10)
Full
Full
Full
±2
-7
-1
-
-
-
±6
7
V
Positive Supply Current, I+
Negative Supply Current, I-
V
= ±5.5V, V
, V
= 0V or V+, Switch On or
µA
µA
S
INH ADD
Off, (Note 9)
1
Electrical Specifications +12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, V
Unless Otherwise Specified.
= 4V, V
= 0.8V (Note 3),
INL
INH
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 4, 8) TYP (Notes 4, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
(Note 10)
Full
25
0
-
-
-
-
-
-
-
-
-
-
-
-
37
V+
45
55
2
2
-
V
Ω
ON-Resistance, r
V+ = 10.8V, I
= 1.0mA, V
= 9V (See Figure 5)
= 9V (Note 5)
ON
COM
COM
COM
NO
NO
NO
Full
25
-
Ω
r
Matching Between Channels,
V+ = 10.8V, I
= 1.0mA, V
1.2
-
Ω
ON
Δr
ON
Full
Ω
r
Flatness, r
V+ = 10.8V, I
= 1.0mA, V
= 3V, 6V, 9V (Note 6) Full
5
Ω
ON
FLAT(ON)
NO OFF Leakage Current, I
V+ = 13.2V, V
= 1V, 12V, V
= 12V, 1V (Note 7)
= 1V, 12V (Note 7)
= 1V, 12V, or
25
Full
25
0.02
0.2
0.02
0.2
0.02
0.2
-
nA
nA
nA
nA
nA
nA
NO(OFF)
COM
NO
-
COM OFF Leakage Current,
V+ = 13.2V, V
= 12V, 1V, V
-
COM
NO
I
COM(OFF)
Full
25
-
COM ON Leakage Current, I
V+ = 13.2V, V
COM
floating (Note 7)
= 1V, 12V, V
NO
-
COM(ON)
Full
-
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Input Voltage Low, V
, V
INHH ADDH
Full
Full
Full
3.7
-
3.3
2.7
-
-
V
V
, V
INHL ADDL
0.8
0.5
Input Current, I
, I
I
,
V+ = 13.2V, V
, V
= 0V or V+
-0.5
µA
ADDH ADDL, INHH
INH ADD
I
INHL
DYNAMIC CHARACTERISTICS
INHIBIT Turn-ON Time, t
V+ = 10.8V, V
= 10V, R = 300Ω, C = 35pF,
25
Full
25
-
-
-
-
24
-
40
45
30
35
ns
ns
ns
ns
ON
NO
L
L
V
= 0 to 4 (See Figure 1, Note 9)
IN
INHIBIT Turn-OFF Time, t
V+ = 10.8V, V
= 10V, R = 300Ω, C = 35pF,
15
-
OFF
NO
L
L
V
= 0 to 4 (See Figure 1, Note 9)
IN
Full
FN6416.3
April 13, 2009
4
ISL84581
Electrical Specifications +12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, V
Unless Otherwise Specified. (Continued)
= 4V, V
= 0.8V (Note 3),
INL
INH
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 4, 8) TYP (Notes 4, 8) UNITS
Address Transition Time, t
TRANS
V+ = 10.8V, V
= 10V, R = 300Ω, C = 35pF,
25
-
-
27
-
50
55
-
ns
ns
ns
NO
L
L
V
= 0 to 4 (See Figure 1, Note 9)
IN
Full
Full
Break-Before-Make Time Delay, t
V+ = 13.2V, R = 300Ω, C = 35pF, V
= 10V,
2
5
D
L
L
NO
V
C
R
= 0 to 4 (See Figure 3, Note 9)
IN
Charge Injection, Q
OFF-Isolation
= 1.0nF, V = 0V, R = 0Ω (See Figure 2, Note 9)
25
25
-
-
2.7
92
5
-
pC
dB
L
L
G
G
= 50Ω, C = 15pF, f = 100kHz
L
(See Figures 4 and 18)
NO OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
f = 1MHz, V
= V
= V
= V
= 0V (See Figure 6)
= 0V (See Figure 6)
= 0V (See Figure 6)
25
25
25
-
-
-
3
-
-
-
pF
pF
pF
OFF
NO
NO
NO
COM
COM
COM
COM OFF Capacitance, C
21
26
COM(OFF)
COM(ON)
COM ON Capacitance, C
POWER SUPPLY CHARACTERISTICS
Power Supply Range
(Note 10)
Full
Full
2
-
-
12
7
V
Positive Supply Current, I+
V+ = 13.2V, V
off
, V
INH ADD
= 0V or V+, all channels on or
-7
µA
Electrical Specifications 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
Unless Otherwise Specified.
= 2.4V, V
= 0.8V (Note 3),
INL
INH
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 4, 8) TYP (Notes 4, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
(Note 10)
Full
25
0
-
-
81
-
V+
100
120
4
V
Ω
Ω
Ω
Ω
Ω
ON-Resistance, r
V+ = 4.5V, I
(See Figure 5)
= 1.0mA, V
= 3.5V
ON
COM
NO
Full
25
-
r
Matching Between Channels, Δr
V+ = 4.5V, I
= 1.0mA, V
= 3V (Note 5)
= 1V, 2V, 3V
-
2.2
-
ON
ON
ON
COM
COM
NO
Full
Full
-
6
r
Flatness, r
V+ = 4.5V, I
(Note 6)
= 1.0mA, V
-
11.5
-
FLAT(ON)
NO
NO OFF Leakage Current, I
V+ = 5.5V, V
(Note 7)
= 1V, 4.5V, V
= 1V, 4.5V, V
= 4.5V, 1V
= 4.5V, 1V
25
Full
25
-
-
-
-
-
-
0.02
0.2
-
-
-
-
-
-
nA
nA
nA
nA
nA
nA
NO(OFF)
COM
COM
COM
NO
NO
COM OFF Leakage Current, I
V+ = 5.5V, V
(Note 7)
0.02
0.2
COM(OFF)
COM(ON)
Full
25
COM ON Leakage Current, I
V+ = 5.5V, V
= V
= 4.5V (Note 7)
0.02
0.2
NO
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Input Voltage Low, V
, V
INHH ADDH
Full
Full
Full
2.4
-
-
-
-
-
V
V
, V
INHL ADDL
0.8
0.5
Input Current, I
, I
I
,
V+ = 5.5V, V
, V
INH ADD
= 0V or V+, (Note 9)
-0.5
µA
ADDH ADDL, INHH
I
INHL
DYNAMIC CHARACTERISTICS
INHIBIT Turn-ON Time, t
V+ = 4.5V, V
NO
= 3V, R = 300Ω, C = 35pF,
25
-
-
43
-
60
70
ns
ns
ON
L
L
V
= 0 to 3V (see Figure 1, Note 9)
IN
Full
FN6416.3
April 13, 2009
5
ISL84581
Electrical Specifications 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
Unless Otherwise Specified. (Continued)
= 2.4V, V
= 0.8V (Note 3),
INL
INH
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
= 3V, R = 300Ω, C = 35pF,
(°C) (Notes 4, 8) TYP (Notes 4, 8) UNITS
INHIBIT Turn-OFF Time, t
V+ = 4.5V, V
NO
25
Full
25
-
-
20
-
35
40
70
85
-
ns
ns
ns
ns
ns
OFF
L
L
V
= 0 to 3V (see Figure 1, Note 9)
IN
Address Transition Time, t
V+ = 4.5V, V
NO
= 3V, R = 300Ω, C = 35pF,
-
51
-
TRANS
BBM
L
L
V
= 0 to 3V (see Figure 1, Note 9)
IN
Full
Full
-
Break-Before-Make Time, t
V+ = 5.5V, V
NO
= 3V, R = 300Ω, C = 35pF,
2
9
L
L
V
= 0 to 3V (see Figure 3, Note 9)
IN
Charge Injection, Q
OFF-Isolation
C = 1.0nF, V = 0V, R = 0Ω (see Figure 2, Note 9)
25
25
-
-
0.6
92
1.5
-
pC
dB
L
G
G
R
= 50Ω, C = 15pF, f = 100kHz, V
= 1V
NOx RMS
L
L
(see Figures 4 and 18)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
(Note 10)
Full
Full
Full
2
-
-
-
12
7
V
Positive Supply Current, I+
Positive Supply Current, I-
V+ = 5.5V, V- = 0V, V
Switch On or Off, (Note 9)
, V
INH ADD
= 0V or V+,
-7
-1
µA
µA
1
Electrical Specifications 3.3V SupplyTest Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, V
= 2.4V, V
= 0.8V (Note 3),
INL
INH
Unless Otherwise Specified
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 4, 8) TYP (Notes 4, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
135
-
V+
180
200
8
V
Ω
Ω
Ω
Ω
Ω
ON-Resistance, r
V+ = 3.0V, I
V+ = 3.0V, I
= 1.0mA, V
NO
= 1.5V (see Figure 5)
= 1.5V (Note 5)
ON
COM
Full
25
-
r
Matching Between Channels,
= 1.0mA, V
NO
-
3.4
-
ON
Δr
COM
ON
Full
Full
-
10
-
r
Flatness, r
V+ = 3.0V, I
(Note 6)
= 1.0mA, V = 0.5V, 1V, 2V
NO
-
34
ON
FLAT(ON)
COM
NO OFF Leakage Current, I
V+ = 3.6V, V
V+ = 3.6V, V
V+ = 3.6V, V
= 0V, 4.5V, V
= 0V, 4.5V, V
= 3V, 1V (Note 7)
= 3V, 1V (Note 7)
25
Full
25
-
-
-
-
-
-
0.02
0.2
-
-
-
-
-
-
nA
nA
nA
nA
nA
nA
NO(OFF)
COM
COM
COM
NO
COM OFF Leakage Current,
0.02
0.2
NO
I
COM(OFF)
Full
25
COM ON Leakage Current, I
= V
= 3V (Note 7)
NO
0.02
0.2
COM(ON)
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Input Voltage Low, V
, V
INHH ADDH
Full
Full
Full
2.4
-
-
-
-
-
V
V
, V
INHL ADDL
0.8
0.5
Input Current, I
, I
I
,
V+ = 3.6V, V
, V
INH ADD
= 0V or V+, (Note 9)
-0.5
μA
ADDH ADDL, INHH
I
INHL
DYNAMIC CHARACTERISTICS
INHIBIT Turn-ON Time, t
V+ = 3.0V, V
= 1.5V, R = 300Ω, C = 35pF,
25
-
-
82
-
100
120
ns
ns
ON
NO
L
L
V
= 0V to 3V (see Figure 1, Note 9)
IN
Full
FN6416.3
April 13, 2009
6
ISL84581
Electrical Specifications 3.3V SupplyTest Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, V
Unless Otherwise Specified (Continued)
= 2.4V, V
= 0.8V (Note 3),
INL
INH
TEMP
MIN
MAX
PARAMETER
INHIBIT Turn-OFF Time, t
TEST CONDITIONS
= 1.5V, R = 300Ω, C = 35pF,
(°C) (Notes 4, 8) TYP (Notes 4, 8) UNITS
V+ = 3.0V, V
25
Full
25
-
-
37
-
50
60
ns
ns
ns
ns
ns
OFF
NO
L
L
V
= 0V to 3V (see Figure 1, Note 9)
IN
Address Transition Time, t
Break-Before-Make Time, t
V+ = 3.0V, V
= 1.5V, R = 300Ω, C = 35pF,
-
96
-
120
145
-
TRANS
BBM
NO
L
L
V
= 0V to 3V (see Figure 1, Note 9)
IN
Full
Full
-
V+ = 3.6V, V
= 1.5V, R = 300Ω, C = 35pF,
3
13
NO
L
L
V
= 0V to 3V (see Figure 3, Note 9)
IN
Charge Injection, Q
OFF-Isolation
C = 1.0nF, V = 0V, R = 0Ω (see Figure 2, Note 9)
25
25
-
-
0.3
92
1
-
pC
dB
L
G
G
R
= 50Ω, C = 15pF, f = 100kHz,
L
L
V
= 1V
(see Figures 4 and 18)
NO
RMS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
(Note 10)
Full
2
-
12
V
NOTES:
3. V = Input logic voltage to configure the device in a given state.
IN
4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Δr = r (MAX) - r (MIN).
ON ON
ON
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25°C.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Limits established by characterization and are not production tested.
10. Limits should be considered typical and are not production tested.
Test Circuits and Waveforms
V+
V-
C
C
C
3V
0V
t < 20ns
r
t < 20ns
f
LOGIC
INPUT
50%
V+
NO0
V
OUT
t
ON
COM
NO1-NO7
INH
V
ADDA-C
OUT
VNO0
0V
GND
C
35pF
90%
90%
L
R
300Ω
L
LOGIC
INPUT
SWITCH
OUTPUT
t
OFF
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. C includes fixture and stray
L
capacitance.
R
L
-----------------------
V
= V
OUT
(NO or NC)
R
+ r
ON
L
FIGURE 1B. INHIBIT t /t
ON OFF
TEST CIRCUIT
FIGURE 1A. INHIBIT t /t
ON OFF
MEASUREMENT POINTS
FN6416.3
April 13, 2009
7
ISL84581
Test Circuits and Waveforms (Continued)
V+
V-
3V
0V
t < 20ns
r
t < 20ns
f
C
C
C
LOGIC
INPUT
50%
V+
NO0
t
TRANS
V
V
OUT
V-
NO7
COM
C
NO1-NO6
OUT
VNO0
0V
90%
ADDA-C
INH
GND
C
35pF
L
R
300Ω
L
SWITCH
OUTPUT
LOGIC
INPUT
10%
VNO
X
t
TRANS
Repeat test for other switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
-----------------------
V
= V
OUT
(NO or NC)
R
+ r
ON
L
FIGURE 1D. ADDRESS t
TEST CIRCUIT
TRANS
FIGURE 1C. ADDRESS t
MEASUREMENT POINTS
TRANS
FIGURE 1. SWITCHING TIMES
V+
V-
C
C
V
3V
OUT
R
OFF
G
OFF
COM
LOGIC
INPUT
NO
ON
0V
0Ω
ADDX
GND
INH
SWITCH
OUTPUT
V
C
L
1nF
G
ΔV
OUT
LOGIC
INPUT
V
OUT
Q = ΔV
x C
L
OUT
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
FIGURE 2A. Q MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
V-
C
C
t < 20ns
r
t < 20ns
f
3V
0V
C
LOGIC
INPUT
V
OUT
COM
C
35pF
R
L
300Ω
L
NO0-NO7
ADDA-C
V+
80%
SWITCH
OUTPUT
V
OUT
LOGIC
INPUT
INH
GND
0V
t
BBM
Repeat test for other switches. C includes fixture and stray
L
capacitance.
FIGURE 3A. t
BBM
MEASUREMENT POINTS
FIGURE 3B. t
TEST CIRCUIT
BBM
FIGURE 3. BREAK-BEFORE-MAKE TIME
FN6416.3
April 13, 2009
8
ISL84581
Test Circuits and Waveforms (Continued)
V+
V-
V+
V-
C
C
C
C
r
= V /1mA
1
ON
SIGNAL
GENERATOR
NOx
NO
V
NOX
0V OR V+
0V OR V+
0V OR V+
1mA
V
1
ADDX
ADDX
COM
ANALYZER
COM
INH
GND
INH
GND
R
L
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
FIGURE 5. r
TEST CIRCUIT
ON
V+
V-
C
C
NOx
0V OR V+
ADDX
INH
IMPEDANCE
ANALYZER
COM
GND
FIGURE 6. CAPACITANCE TEST CIRCUIT
FN6416.3
April 13, 2009
9
ISL84581
Power-Supply Considerations
Detailed Description
The ISL84581 construction is typical of most CMOS analog
switches, in that it has three supply pins: V+, V-, and GND.
V+ and V- drive the internal CMOS switches and set their
analog voltage limits, so there are no connections between
the analog signal path and GND. Unlike switches with a 13V
maximum supply voltage, the ISL84581 15V maximum
supply voltage provides plenty of room for the 10% tolerance
of 12V supplies (±6V or 12V single supply), as well as room
for overshoot and noise spikes.
The ISL84581 multiplexer offers precise switching capability
from bipolar ±2V to ±6V supplies or a single 2V to 12V
supply. When powered with dual ±5V supplies the part has
low ON-resistance (39Ω) and high speed operation
(t
= 38ns, t = 19ns).
ON
OFF
It has an inhibit pin to simultaneously open all signal paths.
The device is especially well suited for applications using
±5V supplies. With ±5V supplies the performance (r
Leakage, Charge Injection, etc.) is best in class.
,
ON
The part performs equally well when operated with bipolar or
single voltage supplies.The minimum recommended supply
voltage is 2V single supply or ±2V dual supply. It is important
to note that the input signal range, switching times, and
ON-resistance degrade at lower supply voltages. Refer to
the “Electrical Specification” tables on page 4 and “Typical
Performance Curves” on page 11 for details.
High frequency applications also benefit from the wide
bandwidth and high off-isolation.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V- (see
Figure 7). To prevent forward biasing these diodes, V+ and
V- must be applied before any input signals, and input signal
voltages must remain between V+ and V-. If these conditions
cannot be guaranteed, then one of the following two
protection methods should be employed.
V+ and GND power the internal logic setting the digital
switching point of the level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This ISL84581 is TTL compatible
(0.8V and 2.4V) over a V+ supply range of 2.7V to 10V. At
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 7). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
12V the V level is about 3.3V. This is still below the CMOS
IH
guaranteed high output minimum level of 4V, but noise
margin is reduced. For best results with a 12V supply, use a
logic family that provides a V
OH
greater than 4V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low r
switch, so two small signal
ON
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 7). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
100MHz (see Figures 16 and 17). Figures 16 and 17 also
illustrate that the frequency response is very consistent over
varying analog signal levels.
OPTIONAL
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off-isolation is the
resistance to this feed through. Figure 18 details the high off
isolation of the ISL84581. At 10MHz, off-isolation is about
55dB in 50Ω systems, decreasing approximately 20dB per
decade as frequency increases. Higher load impedances
decrease off-isolation due to the voltage divider action of the
switch OFF impedance and the load impedance.
PROTECTION
OPTIONAL PROTECTION
DIODE
RESISTOR
FOR LOGIC
INPUTS
V+
1kΩ
LOGIC
V
V
COM
NOx
V-
OPTIONAL PROTECTION
DIODE
FIGURE 7. INPUT OVERVOLTAGE PROTECTION
FN6416.3
April 13, 2009
10
ISL84581
V+ or V- and the analog signal. This means their leakages
Leakage Considerations
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
analog-signal-path leakage current. All analog leakage
current flows between each pin and one of the supply
terminals, not to the other switch terminal. This is why both
sides of a given switch can show leakage currents of the
same or opposite polarity. There is no connection between
the analog signal paths and GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
Typical Performance Curves T = +25°C, Unless Otherwise Specified
A
120
V
= ±2V
110
S
I
= 1mA
COM
70
+85°C
100
V
= (V+) - 1V
COM
= 1mA
V- = -5V
90
80
70
60
50
60
50
40
30
I
COM
+25°C
-40°C
+85°C
+25°C
-40°C
90
80
70
60
50
40
30
V
= ±3V
S
20
400
+85°C
V- = 0V
+25°C
-40°C
300
200
100
0
60
50
40
30
20
V
= ±5V
+85°C
S
+85°C
+25°C
+25°C
-40°C
-40°C
-5
-4
-3
-2
-1
0
1
2
3
4
5
3
4
5
6
7
8
9
10
11
12
2
V
(V)
V+ (V)
COM
FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE
225
60
55
50
45
40
35
30
25
20
I
= 1mA
COM
200
I
= 1mA
V+ = 12V
V- = 0V
COM
175
150
+85°C
125
100
+25°C
-40°C
V+ = 2.7V
V- = 0V
75
160
140
120
100
80
+85°C
+85°C
+25°C
-40°C
V+ = 3.3V
V- = 0V
60
+25°C
100
90
80
V+ = 5V
V- = 0V
+85°C
70 +25°C
60
50
40
-40°C
-40°C
0
2
4
6
8
10
12
0
1
2
3
4
5
V
(V)
V
(V)
COM
COM
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FN6416.3
April 13, 2009
11
ISL84581
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
500
400
300
200
100
200
150
100
50
V
= (V+) - 1V
V- = -5V
V
= (V+) - 1V
COM
V- = -5V
COM
-40°C
+25°C
-40°C
+25°C
+25°C
+85°C
+25°C
+85°C
-40°C
0
-40°C
0
250
100
V- = 0V
V- = 0V
200
150
100
50
80
60
40
20
0
+85°C
+85°C
+25°C
+25°C
-40°C
-40°C
0
2
3
4
5
6
7
8
9
10
11
12
2
3
4
5
6
7
8
9
10
11
12
V+ (V)
V+ (V)
FIGURE 12. INHIBIT TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 13. INHIBIT TURN-OFF TIME vs SUPPLY VOLTAGE
300
250
V
= (V+) - 1V
COM
V
= (V+) - 1V
COM
V- = 0V
250
200
150
100
50
200
150
100
50
+25°C
+25°C
+85°C
+85°C
-40°C
-40°C
0
0
2
3
4
5
6
2
3
4
5
6
7
8
9
10
11
12
13
V± (V)
V+ (V)
FIGURE 15. ADDRESS TRANS TIME vs DUAL SUPPLY
VOLTAGE
FIGURE 14. ADDRESS TRANS TIME vs SINGLE SUPPLY
VOLTAGE
V
= ±5V
V
= ±3V
S
V
= 0.2V
TO 5V
P-P P-P
V
= 0.2V
P-P
TO 4V
P-P
S
IN
IN
3
0
3
0
GAIN
GAIN
-3
-3
0
0
PHASE
PHASE
45
90
45
90
135
180
135
180
R
= 50Ω
R
= 50Ω
L
L
1M
10M
100M
600M
1M
10M
100M
600M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 16. FREQUENCY RESPONSE
FIGURE 17. FREQUENCY RESPONSE
FN6416.3
April 13, 2009
12
ISL84581
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
3
-10
-20
-30
-40
-50
-60
-70
-80
-90
V+ = 3V TO 12V OR
V
= ±2V TO ±5V
S
2
R
= 50Ω
L
V+ = 3.3V
V- = 0V
1
V+ = 12V
V- = 0V
0
V+ = 5V
V- = 0V
ISOLATION
-1
-2
-3
-4
V
= ±5V
S
-100
-110
-5
0
5
10
12
-2.5
2.5
7.5
1k
10k
100k
1M
10M
100M 500M
V
(V)
FREQUENCY (Hz)
COM
FIGURE 18. OFF ISOLATION
FIGURE 19. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V-
TRANSISTOR COUNT:
193
PROCESS:
Si Gate CMOS
FN6416.3
April 13, 2009
13
ISL84581
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M16.15A
N
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
INDEX
M
M
B
0.25(0.010)
H
AREA
E
INCHES
MILLIMETERS
GAUGE
PLANE
-B-
SYMBOL
MIN
MAX
MIN
1.55
0.102
1.40
0.20
0.191
4.80
3.81
MAX
1.73
0.249
1.55
0.31
0.249
4.98
3.99
NOTES
A
A1
A2
B
0.061
0.004
0.055
0.008
0.0075
0.189
0.150
0.068
0.0098
0.061
0.012
0.0098
0.196
0.157
-
1
2
3
-
L
-
0.25
0.010
SEATING PLANE
A
9
-A-
D
h x 45°
C
D
E
-
3
-C-
4
α
A2
e
A1
e
0.025 BSC
0.635 BSC
-
C
B
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.89
-
0.10(0.004)
M
M
S
B
0.17(0.007)
C
A
5
L
6
NOTES:
N
α
16
16
7
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
0°
8°
0°
8°
-
Rev. 2 6/04
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimen-
sions are not necessarily exact.
FN6416.3
April 13, 2009
14
ISL84581
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
MIN
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
GAUGE
PLANE
SYMBOL
MAX
0.043
0.006
0.037
0.012
0.008
0.201
0.177
MIN
-
MAX
1.10
0.15
0.95
0.30
0.20
5.10
4.50
NOTES
A
A1
A2
b
-
-
0.002
0.033
0.0075
0.0035
0.193
0.169
0.05
0.85
0.19
0.09
4.90
4.30
-
1
2
3
-
L
0.25
0.010
0.05(0.002)
SEATING PLANE
A
9
-A-
c
-
D
D
3
-C-
E1
e
4
α
0.026 BSC
0.65 BSC
-
A2
e
A1
c
E
0.246
0.020
0.256
0.028
6.25
0.50
6.50
0.70
-
b
0.10(0.004)
L
6
0.10(0.004) M
C
A M B S
N
16
16
7
o
o
o
o
0
8
0
8
-
α
NOTES:
Rev. 1 2/02
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6416.3
April 13, 2009
15
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