ISL84582IVZ-T [INTERSIL]
Low-Voltage, Single and Dual Supply, Differential 4 to 1 Multiplexer; 低电压，单电源和双电源，差分4：1多路复用器
| 型号： | ISL84582IVZ-T |
| 厂家： | 
Intersil |
| 描述： | Low-Voltage, Single and Dual Supply, Differential 4 to 1 Multiplexer |
| 文件： | 总14页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL84582
®
Data Sheet
January 27, 2006
FN6213.1
Low-Voltage, Single and Dual Supply,
Differential 4 to 1 Multiplexer
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
The Intersil ISL84582 device is made of precision,
bidirectional, analog switches configured as a differential 4
channel multiplexer/demultiplexer. It is designed to operate
from a single +2V to +12V supply or from a ±2V to ±6V dual
supplies. The device has an inhibit pin to simultaneously open
all signal paths.
• Fully Specified at 3.3V, 5V, ±5V, and 12V Supplies for 10%
Tolerances
• ON Resistance (R ), V = ±4.5V. . . . . . . . . . . . . . . 44Ω
ON
S
• ON Resistance (R ), V = +2.7V . . . . . . . . . . . . . 135Ω
ON
S
• R
ON
Matching Between Channels, V = ±5V . . . . . . . . <2Ω
S
ON resistance of 39Ω with a ±5V supply and 125Ω with a
single +3.3V supply. Each switch can handle rail to rail
analog signals. The off-leakage current is only 0.1nA at
+25°C or 2.5nA at +85°C.
• Low Charge Injection, V = ±5V . . . . . . . . . . . . . 1pC (Max)
S
• Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V
• Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . ±2V to ±6V
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring
TTL/CMOS logic compatibility when using a single 3.3V or
+5V supply or dual ±5V supplies.
• Low Power Consumption (P ). . . . . . . . . . . . . . . . . . . .<3µW
D
• Fast Switching Action (V = +5V)
S
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ns
ON
The ISL84582 is a differential 4 to 1 multiplexer device.
Table 1 summarizes the performance of this part.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
OFF
• Guaranteed Max Off-Leakage . . . . . . . . . . . . . . . . . . .2.5nA
• Guaranteed Break-Before-Make
TABLE 1. FEATURES AT A GLANCE
Configuration
±5V R
Diff 4:1 Mux
39Ω
• TTL, CMOS Compatible
ON
±5V t /t
32ns/18ns
32Ω
ON OFF
12V R
Applications
• Battery Powered, Handheld, and Portable Equipment
• Communications Systems
- Radios
- Telecom Infrastructure
- ADSL, VDSL Modems
ON
12V t /t
23ns/15ns
65Ω
ON OFF
5V R
ON
5V t /t
43ns/20ns
125Ω
ON OFF
3.3V R
ON
3.3V t /t
• Test Equipment
70ns/32ns
16 Ld TSSOP
ON OFF
- Medical Ultrasound
- Magnetic Resonance Image
- CT and PET Scanners (MRI)
- ATE
Package
Related Literature
- Electrocardiograph
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Audio and Video Signal Routing
• Various Circuits
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
- +3V/+5V DACs and ADCs
- Sample and Hold Circuits
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
• Application Note AN520 “CMOS Analog Multiplexers and
Switches; Specifications and Application Considerations.”
• Application Note AN1034 “Analog Switch and Multiplexer
Applications”
- Integrator Reset Circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL84582
Pinout
ISL84582 (TSSOP)
TOP VIEW
B0
B1
1
2
3
4
5
6
7
8
16 V+
15 A1
14 A2
COM
B
B3
13 COM
A
B2
INH
V-
12 A0
11 A3
10 ADDB
LOGIC
9
ADDA
GND
Truth Table
Pin Descriptions
ISL84582
PIN
FUNCTION
INH
1
ADDB
ADDA
SWITCH ON
NONE
V+
V-
Positive Power Supply Pin
X
0
0
1
1
X
0
1
0
1
Negative Power Supply Pin. Connect to GND for Single
Supply Configurations.
0
A0, B0
GND
INH
Ground Connection
0
A1, B1
Digital Control Input. Connect to GND for Normal
Operation. Connect to V+ to turn all switches off.
0
A2, B2
0
A3, B3
COMx Analog Mux Common Pin
Ax, Bx Analog Mux Signal Pin
ADDx Address Input Pin
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V, with V+ between 2.7V and
10V. X = Don’t Care.
Ordering Information
PART NO.
PART
TEMP.
PACKAGE
(Pb-Free)
PKG.
(Note)
MARKING RANGE (°C)
DWG. #
ISL84582IVZ
84582IVZ
-40 to 85 16 Ld TSSOP M16.173
ISL84582IVZ-T 84582IVZ
-40 to 85 16 Ld TSSOP M16.173
Tape and Reel
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN6213.1
2
January 27, 2006
ISL84582
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 2)
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 15V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V
Input Voltages
θ
(°C/W)
150
JA
INH, NO, NC, ADD (Note 1). . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 1). . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . ±30mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±100mA
ESD Rating
HBM (Per Mil-STD-883, Method 3015.7) . . . . . . . . . . . . . . . >2kV
Operating Conditions
Temperature Range
ISL84582IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on NC, NO, COM, ADD, INH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications: ±5V Supply
Test Conditions: V
= ±4.5V to ±5.5V, GND = 0V, V
INH
= 2.4V, V
= 0.8V (Note 3),
SUPPLY
INL
Unless Otherwise Specified
TEMP (NOTE 4)
(NOTE 4)
MAX
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
V-
-
-
V+
60
80
4
V
Ω
ON Resistance, R
V
= ±4.5V, I
COM
= 2mA, V
= 2mA, V
= 2mA, V
or V
or V
or V
= 3V,
44
ON
S
NO
NO
NO
NC
NC
NC
(See Figure 5)
Full
25
-
-
Ω
R
Matching Between Channels,
ON
V
V
= ±4.5V, I
= 3V, (Note 5)
= ±3V, 0V,
-
1.3
Ω
ON
∆R
S
S
COM
COM
Full
25
-
-
6
Ω
R
Flatness, R
= ±4.5V, I
-
7.5
9
Ω
ON
FLAT(ON)
(Note 6)
Full
25
-
-
12
0.1
2.5
0.1
2.5
0.1
2.5
Ω
NO or NC OFF Leakage Current,
or I
V
= ±5.5V, V
= ±4.5V, V
= ±4.5V, V
or V
= +4.5V,
= +4.5V,
-0.1
-2.5
-0.1
-2.5
-0.1
-2.5
0.002
nA
nA
nA
nA
nA
nA
S
COM
COM
COM
NO
NO
NC
NC
I
(Note 7)
NO(OFF)
NC(OFF)
Full
25
-
COM OFF Leakage Current,
V
= ±5.5V, V
or V
0.002
S
I
(Note 7)
COM(OFF)
Full
25
-
0.002
-
COM ON Leakage Current,
V
= ±5.5V, V
= V
or V
= ±4.5V, (Note 7)
NC
S
NO
I
COM(ON)
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Input Voltage Low, V
, V
INHH ADDH
Full
Full
Full
2.4
-
-
-
-
V
V
, V
INHL ADDL
0.8
0.5
Input Current, I
, I
I
V
= ±5.5V, V
, V
INH ADD
= 0V or V+
-0.5
0.03
µA
ADDH ADDL, INHH,
S
I
INHL
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, t
V
V
= ±4.5V, V
IN
or V
= ±3V, R = 300Ω, C = 35pF,
25
Full
25
-
-
-
-
35
-
50
60
35
40
ns
ns
ns
ns
ON
S
NO
NC
L
L
= 0 to 3, (See Figure 1, Note 9)
Inhibit Turn-OFF Time, t
OFF
V
V
= ±4.5V, V
IN
or V
= ±3V, R = 300Ω, C = 35pF,
22
-
S
NO
NC
L
L
= 0 to 3, (See Figure 1, Note 9)
Full
FN6213.1
3
January 27, 2006
ISL84582
Electrical Specifications: ±5V Supply
Test Conditions: V
= ±4.5V to ±5.5V, GND = 0V, V
= 2.4V, V
= 0.8V (Note 3),
SUPPLY
INH
INL
Unless Otherwise Specified (Continued)
TEMP (NOTE 4)
(NOTE 4)
MAX
PARAMETER
TEST CONDITIONS
(°C)
25
MIN
TYP
43
-
UNITS
ns
Address Transition Time, t
V
V
= ±4.5V, V
IN
or V
= ±3V, R = 300Ω, C = 35pF,
-
-
60
70
-
TRANS
S
NO
NC
L
L
= 0 to 3, (See Figure 1, Note 9)
Full
Full
ns
Break-Before-Make Time, t
Charge Injection, Q
V
V
= ±5.5V, V
IN
or V
= 3V, R = 300Ω, C = 35pF,
2
7
ns
BBM
S
NO
NC
L
L
= 0 to 3V, (See Figure 3, Note 9)
C
= 1.0nF, V = 0V, R = 0Ω, (See Figure 2, Note 9)
25
25
25
25
25
25
25
-
-
-
-
-
-
-
0.3
3
1
-
-
-
-
-
-
pC
pF
pF
pF
dB
dB
dB
L
G
NO
NO
NO
G
NO/NC OFF Capacitance, C
OFF
f = 1MHz, V
f = 1MHz, V
f = 1MHz, V
or V
or V
or V
= V
= 0V, (See Figure 7)
= 0V, (See Figure 7)
= 0V, (See Figure 7)
NC
NC
NC
COM
COM
COM
COM OFF Capacitance, C
= V
= V
12
OFF
COM ON Capacitance, C
OFF Isolation
18
COM(ON)
R
V
= 50Ω, C = 15pF, f = 100kHz,
92
L
L
= 1V
, (See Figures 4, 6 and 19)
RMS
NOx
Crosstalk, (Note 8)
≤110
-105
All Hostile Crosstalk, (Note 8)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
Full
Full
±2
-1
-1
-
-
-
±6
1
V
Positive Supply Current, I+
Negative Supply Current, I-
NOTES:
V
= ±5.5V, V
, V
INH ADD
= 0V or V+, Switch On or Off
µA
µA
S
1
3. V = Input logic voltage to configure the device in a given state.
IN
4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. ∆R = R (MAX) - R (MIN).
ON ON ON
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25°C.
8. Between any two switches.
9. Guaranteed but not tested.
Electrical Specifications: 12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, V
Unless Otherwise Specified
= 4V, V
= 0.8V (Note 3),
(NOTE4)
INH
INL
TEMP (NOTE 4)
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
V+
V
Ω
Ω
Ω
ON Resistance, R
V+ = 10.8V, I
COM
= 1.0mA, V
or V
= 9V,
37
47
-
-
-
ON
NO
NC
(See Figure 5)
Full
Full
-
R
Matching Between Channels, V+ = 10.8V, I
COM
ON
= 1.0mA, V
= 1.0mA, V
or V
or V
= 9V, (Note 5)
= 3V, 6V, 9V,
-
1.2
ON
∆R
NO
NC
R
Flatness, R
V+ = 10.8V, I
COM
Full
-
5
-
Ω
ON
FLAT(ON)
NO
NC
(Note 6)
NO or NC OFF Leakage Current,
or I
V+ = 13.2V, V
(Note 7)
= 1V, 12V, V
or V
= 12V, 1V,
= 1V, 12V,
= 1V, 12V,
25
Full
25
-0.1
-2.5
-0.1
-2.5
-0.1
-2.5
0.002
0.1
2.5
0.1
2.5
0.1
2.5
nA
nA
nA
nA
nA
nA
COM
NO
NO
NC
I
NO(OFF)
NC(OFF)
-
COM OFF Leakage Current,
V+ = 13.2V, V
(Note 7)
= 12V, 1V, V
or V
0.002
COM
NC
I
COM(OFF)
Full
25
-
0.002
-
COM ON Leakage Current,
V+ = 13.2V, V
COM
= 1V, 12V, V
NO
or V
NC
I
or floating, (Note 7)
COM(ON)
Full
FN6213.1
4
January 27, 2006
ISL84582
Electrical Specifications: 12V Supply
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, V
= 4V, V
= 0.8V (Note 3),
(NOTE4)
INH
INL
Unless Otherwise Specified (Continued)
TEMP (NOTE 4)
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Input Voltage Low, V
, V
INHH ADDH
Full
Full
Full
3.7
-
3.3
2.7
-
-
V
V
, V
INHL ADDL
0.8
0.5
Input Current, I
, I
I
V+ = 13.2V, V
, V
= 0V or V+
-0.5
µA
ADDH ADDL, INHH,
INH ADD
I
INHL
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, t
V+ = 10.8V, V
IN
or V
= 10V, R = 300Ω, C = 35pF,
25
Full
25
-
-
24
-
40
45
30
35
50
55
-
ns
ns
ns
ns
ns
ns
ns
ON
NO
NC
L
L
V
= 0 to 4, (See Figure 1, Note 9)
Inhibit Turn-OFF Time, t
OFF
V+ = 10.8V, V
IN
or V
= 10V, R = 300Ω, C = 35pF,
-
15
-
NO
NC
L
L
V
= 0 to 4, (See Figure 1, Note 9)
Full
25
-
Address Transition Time, t
TRANS
V+ = 10.8V, V
IN
or V
= 10V, R = 300Ω, C = 35pF,
-
27
-
NO
NC
L
L
V
= 0 to 4, (See Figure 1, Note 9)
Full
Full
-
Break-Before-Make Time Delay, t
V+ = 13.2V, R = 300Ω, C = 35pF, V
or V
= 10V,
2
5
D
L
L
NO
NC
V
C
R
= 0 to 4, (See Figure 3, Note 9)
IN
Charge Injection, Q
OFF Isolation
= 1.0nF, V = 0V, R = 0Ω, (See Figure 2, Note 9)
25
25
25
25
25
25
-
-
-
-
-
-
2.7
92
5
-
pC
dB
dB
dB
pF
pF
L
G
G
= 50Ω, C = 15pF, f = 100kHz,
L
L
(See Figure 4,6 and 19)
Crosstalk, (Note 8)
All Hostile Crosstalk, (Note 8)
≤110
-105
3
-
-
NO or NC OFF Capacitance, C
COM OFF Capacitance,
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V, (See Figure 7)
= 0V, (See Figure 7)
-
OFF
NO
NO
NC
COM
COM
12
-
NC
C
COM(OFF)
COM ON Capacitance, C
f = 1MHz, V
or V
= V
= 0V, (See Figure 7)
25
-
18
-
pF
COM(ON)
NO
NC
COM
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
Full
2
-
-
12
1
V
Positive Supply Current, I+
V+ = 13.2V, V
off
, V
= 0V or V+, all channels on or
-1
µA
INH ADD
Electrical Specifications: 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Note 3),
INL
INH
TEMP
(°C)
MIN
MAX
PARAMETER
TEST CONDITIONS
(NOTE 4)
TYP
(NOTE 4) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
81
-
V+
100
120
4
V
Ω
Ω
Ω
Ω
Ω
ON Resistance, R
V+ = 4.5V, I
= 1.0mA, V
or V
= 3.5V,
ON
COM
(See Figure 5)
NO
NC
Full
25
-
R
Matching Between Channels, V+ = 4.5V, I
ON
= 1.0mA, V
or V
= 3V, (Note 5)
= 1V, 2V, 3V,
-
2.2
-
ON
∆R
COM
COM
NO
NC
Full
Full
-
6
R
Flatness, R
V+ = 4.5V, I
(Note 6)
= 1.0mA, V
or V
-
11.5
-
ON
FLAT(ON)
NO
NC
FN6213.1
5
January 27, 2006
ISL84582
Electrical Specifications: 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
Unless Otherwise Specified (Continued)
= 2.4V, V
= 0.8V (Note 3),
INL
INH
TEMP
(°C)
MIN
MAX
PARAMETER
TEST CONDITIONS
(NOTE 4)
TYP
(NOTE 4) UNITS
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Input Voltage Low, V
, V
INHH ADDH
Full
Full
Full
2.4
-
-
-
-
-
V
V
, V
INHL ADDL
0.8
0.5
Input Current, I
, I
I
V+ = 5.5V, V
, V
INH ADD
= 0V or V+
-0.5
µA
ADDH ADDL, INHH,
I
INHL
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, t
V+ = 4.5V, V
IN
or V
= 3V, R = 300Ω, C = 35pF,
25
Full
25
-
-
43
-
60
70
35
40
70
85
-
ns
ns
ns
ns
ns
ns
ns
ON
NO
NC
L
L
V
= 0 to 3V, (See Figure 1, Note 9)
Inhibit Turn-OFF Time, t
OFF
V+ = 4.5V, V
IN
or V
= 3V, R = 300Ω, C = 35pF,
-
20
-
NO
NC
L
L
V
= 0 to 3V, (See Figure 1, Note 9)
Full
25
-
Address Transition Time, t
V+ = 4.5V, V
IN
or V
= 3V, R = 300Ω, C = 35pF,
-
51
-
TRANS
BBM
NO
NC
L
L
V
= 0 to 3V, (See Figure 1, Note 9)
Full
Full
-
Break-Before-Make Time, t
V+ = 5.5V, V
or V
= 3V, R = 300Ω, C = 35pF,
2
9
NO
NC
L
L
V
C
R
= 0 to 3V, (See Figure 3, Note 9)
IN
Charge Injection, Q
OFF Isolation
= 1.0nF, V = 0V, R = 0Ω, (See Figure 2, Note 9)
25
25
25
25
-
-
-
-
0.6
92
1.5
pC
dB
dB
dB
L
G
G
= 50Ω, C = 15pF, f = 100kHz,
-
-
-
L
L
V
= 1V
, (See Figures 4, 6 and 19)
RMS
NOx
Crosstalk, (Note 8)
≤110
-105
All Hostile Crosstalk, (Note 8)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
Full
2
-
-
12
1
V
Positive Supply Current, I+
V+ = 5.5V, V- = 0V, V
, V
INH ADD
= 0V or V+,
-1
µA
Switch On or Off
Electrical Specifications: 3.3V Supply
Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, V
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Note 3),
INL
INH
TEMP
(°C)
MIN
MAX
PARAMETER
TEST CONDITIONS
(NOTE 4)
TYP
(NOTE 4) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
175
-
V+
180
200
8
V
Ω
Ω
Ω
Ω
Ω
ON Resistance, R
V+ = 2.7V, I
= 1.0mA, V
or V
= 1.5V
NC
ON
COM
(See Figure 5)
NO
Full
25
-
R
Matching Between Channels, V+ = 2.7V, I
ON
= 1.0mA, V
NO
or V
= 1.5V, (Note 5)
or V = 0.5V, 1V, 2V,
NC
-
3.4
-
ON
∆R
COM
COM
NC
Full
Full
-
10
-
R
Flatness, R
V+ = 2.7V, I
(Note 6)
= 1.0mA, V
-
55
ON
FLAT(ON)
NO
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Input Voltage Low, V
, V
INHH ADDH
Full
Full
Full
2.4
-
-
-
-
-
V
V
, V
INHL ADDL
0.8
0.5
Input Current, I
I
, I
I
V+ = 3.6V, V
, V
INH ADD
= 0V or V+
-0.5
µA
ADDH ADDL, INHH,
INHL
FN6213.1
6
January 27, 2006
ISL84582
Electrical Specifications: 3.3V Supply
Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, V
Unless Otherwise Specified (Continued)
= 2.4V, V
= 0.8V (Note 3),
INL
INH
TEMP
(°C)
MIN
MAX
PARAMETER
TEST CONDITIONS
(NOTE 4)
TYP
(NOTE 4) UNITS
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, t
ON
V+ = 3.0V, V
IN
or V
= 1.5V, R = 300Ω, C = 35pF,
25
Full
25
-
-
82
-
100
120
50
ns
ns
ns
ns
ns
ns
ns
NO
NC
L
L
V
= 0 to 3V, (See Figure 1, Note 9)
Inhibit Turn-OFF Time, t
OFF
V+ = 3.0V, V
or V
= 1.5V, R = 300Ω, C = 35pF,
-
37
-
NO
NC
L
L
V
= 0 to 3V, (See Figure 1, Note 9)
IN
Full
25
-
60
Address Transition Time, t
V+ = 3.0V, V
or V
= 1.5V, R = 300Ω, C = 35pF,
-
96
-
120
145
-
TRANS
BBM
NO
NC
L
L
V
= 0 to 3V, (See Figure 1, Note 9)
IN
Full
Full
-
Break-Before-Make Time, t
V+ = 3.6V, V
or V
= 1.5V, R = 300Ω, C = 35pF,
3
13
NO
NC
L
L
V
C
R
= 0 to 3V, (See Figure 3, Note 9)
IN
Charge Injection, Q
OFF Isolation
= 1.0nF, V = 0V, R = 0Ω, (See Figure 2, Note 9)
25
25
25
25
-
-
-
-
0.3
92
1
-
pC
dB
dB
dB
L
G
G
= 50Ω, C = 15pF, f = 100kHz,
L
L
V
or V
= 1V
, (See Figures 4, 6 and 19)
RMS
NO
NC
Crosstalk, (Note 8)
≤110
-105
-
All Hostile Crosstalk, (Note 8)
-
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
Full
2
-
-
12
1
V
Positive Supply Current, I+
V+ = 3.6V, V- = 0V, V
, V
INH ADD
= 0V or V+,
-1
µA
Switch On or Off
Test Circuits and Waveforms
V+
V-
C
C
C
3V
t < 20ns
r
t < 20ns
f
LOGIC
INPUT
50%
0V
ISL84582
COM
V+
NO0
NO1 -NO3
x
V
x
OUT
t
ON
x
x
INH
V
OUT
ADDA-B
VNO0
0V
GND
90%
C
L
35pF
90%
R
300Ω
L
LOGIC
INPUT
SWITCH
OUTPUT
t
OFF
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. C includes fixture and stray
L
capacitance.
R
L
------------------------------
V
= V
OUT
(NO or NC)
R
+ R
L
(ON)
FIGURE 1B. INHIBIT t /t
ON OFF
TEST CIRCUIT
FIGURE 1A. INHIBIT t /t
ON OFF
MEASUREMENT POINTS
FN6213.1
January 27, 2006
7
ISL84582
Test Circuits and Waveforms (Continued)
3V
0V
t < 20ns
r
t < 20ns
f
V+
V-
LOGIC
INPUT
50%
C
C
C
t
TRANS
V
V+
NO0
x
ISL84582
V
OUT
V-
NO3
NO1 -NO2
x
x
OUT
COM
x
VNO0
0V
C
90%
x
SWITCH
OUTPUT
ADDA-B
EN
GND
C
35pF
L
R
L
300Ω
LOGIC
INPUT
10%
VNO
X
t
TRANS
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. C includes fixture and stray
L
capacitance.
R
L
------------------------------
V
= V
OUT
(NO or NC)
R
+ R
L
(ON)
FIGURE 1D. ADDRESS t
TEST CIRCUIT
FIGURE 1C. ADDRESS t
MEASUREMENT POINTS
TRANS
TRANS
FIGURE 1. SWITCHING TIMES
V+
V-
C
C
3V
V
OUT
OFF
OFF
LOGIC
INPUT
R
G
COM
INH
ON
NO or NC
ADDX
0V
0Ω
SWITCH
OUTPUT
GND
∆V
OUT
V
C
L
G
1nF
V
OUT
LOGIC
INPUT
Q = ∆V
x C
L
OUT
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
FIGURE 2A. Q MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
V-
C
C
C
t < 20ns
r
V
t < 20ns
f
OUT
3V
0V
COM
x
LOGIC
INPUT
C
L
R
L
NO0 -NO3
x
x
V+
300Ω
35pF
ISL84582
ADDA-B
80%
SWITCH
OUTPUT
LOGIC
INPUT
INH
GND
V
OUT
0V
t
BBM
Repeat test for other switches. C includes fixture and stray
L
capacitance.
FIGURE 3A. t
BBM
MEASUREMENT POINTS
FIGURE 3B. t
TEST CIRCUIT
BBM
FIGURE 3. BREAK-BEFORE-MAKE TIME
FN6213.1
8
January 27, 2006
ISL84582
Test Circuits and Waveforms (Continued)
V+
V-
V+
V-
C
C
C
C
R
= V /1mA
1
ON
SIGNAL
GENERATOR
NO or NC
NO or NC
V
NX
0V or V+
0V or V+
0V or V+
1mA
V
1
ADDX
ADDX
COM
ANALYZER
COM
INH
INH
GND
GND
R
L
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. R
TEST CIRCUIT
ON
V+
V-
C
C
V+
C
V-
C
SIGNAL
GENERATOR
50Ω
NO or NC
A
COM
A
A
NO or NC
0V or V+
ISL84582
ADDX
0V or V+
ADDX
IMPEDANCE
ANALYZER
NO or NC
N.C.
B
B
COM
ANALYZER
COM
INH
B
GND
INH
GND
R
L
FIGURE 7. CAPACITANCE TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
FN6213.1
January 27, 2006
9
ISL84582
Power-Supply Considerations
Detailed Description
The ISL84582 construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL84582 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (±6V or 12V single supply),
as well as room for overshoot and noise spikes.
The ISL84582 multiplexer offers precise switching capability
from a bipolar ±2V to ±6V or a single 2V to 12V supply with
low on-resistance (39Ω) and high speed operation
(t
= 38ns, t = 19ns) with dual 5V supplies. The device
ON
OFF
is especially well suited to portable battery powered
equipment thanks to the low operating supply voltage (2V),
low power consumption (3µW), low leakage currents (2.5nA
max). High frequency applications also benefit from the wide
bandwidth, and the very high off isolation and crosstalk
rejection.
The ISL84582 performs equally well when operated with
bipolar or single voltage supplies. The minimum
recommended supply voltage is 2V or ±2V. It is important to
note that the input signal range, switching times, and on-
resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V- (see
Figure 8). To prevent forward biasing these diodes, V+ and
V- must be applied before any input signals, and input signal
voltages must remain between V+ and V-. If these conditions
cannot be guaranteed, then one of the following two
protection methods should be employed.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This ISL84582 is TTL compatible
(0.8V and 2.4V) over a V+ supply range of 2.7V to 10V. At
12V the V level is about 3.3V. This is still below the CMOS
IH
guaranteed high output minimum level of 4V, but noise
margin is reduced. For best results with a 12V supply, use a
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
logic family that provides a V
greater than 4V.
OH
purpose of using a low R
switch, so two small signal
ON
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
100MHz (see Figures 17 and 18). Figures 17 and 18 also
illustrates that the frequency response is very consistent
over varying analog signal levels.
OPTIONAL
PROTECTION
OPTIONAL PROTECTION
DIODE
RESISTOR
FOR LOGIC
INPUTS
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off Isolation is the
resistance to this feed through, while Crosstalk indicates the
amount of feed through from one switch to another. Figure 19
details the high Off Isolation and Crosstalk rejection provided
by this family. At 10MHz, Off Isolation is about 55dB in 50Ω
systems, decreasing approximately 20dB per decade as
frequency increases. Higher load impedances decrease Off
Isolation and Crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load
impedance.
V+
1kΩ
LOGIC
V
V
NO or NC
COM
V-
OPTIONAL PROTECTION
DIODE
FIGURE 8. INPUT OVERVOLTAGE PROTECTION
FN6213.1
10
January 27, 2006
ISL84582
V+ or V- and the analog signal. This means their leakages
Leakage Considerations
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signal-
path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
Typical Performance Curves T = 25°C, Unless Otherwise Specified
A
120
V
= ±2V
110
S
I
= 1mA
COM
70
85°C
100
V
= (V+) - 1V
COM
= 1mA
V- = -5V
90
80
70
60
50
60
50
40
30
I
COM
25°C
85°C
25°C
-40°C
-40°C
90
80
70
60
50
40
30
60
50
40
30
20
V
= ±3V
S
20
85°C
400
V- = 0V
25°C
300
200
100
0
-40°C
V
= ±5V
S
85°C
85°C
25°C
25°C
-40°C
-40°C
-5
-4
-3
-2
-1
0
COM
1
2
3
4
5
3
4
5
6
7
8
9
10
11
12
2
V
(V)
V+ (V)
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
225
200
60
I
= 1mA
COM
I
= 1mA
COM
55
50
45
40
35
30
25
20
175
150
V+ = 12V
V- = 0V
85°C
125
100
75
160
140
25°C
V+ = 2.7V
V- = 0V
-40°C
85°C
85°C
25°C
-40°C
120
100
80
V+ = 3.3V
V- = 0V
60
25°C
100
90
80
70
60
50
40
V+ = 5V
V- = 0V
85°C
25°C
-40°C
10
-40°C
4
0
2
4
6
8
12
0
1
2
3
5
V
(V)
V
(V)
COM
COM
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
FN6213.1
11
January 27, 2006
ISL84582
Typical Performance Curves T = 25°C, Unless Otherwise Specified (Continued)
A
200
150
100
50
500
400
300
200
100
V
= (V+) - 1V
V
= (V+) - 1V
COM
V- = -5V
V- = -5V
COM
-40°C
25°C
-40°C
25°C
25°C
25°C
85°C
85°C
-40°C
0
100
-40°C
0
250
V- = 0V
V- = 0V
80
60
40
20
0
200
150
100
50
85°C
85°C
25°C
25°C
-40°C
-40°C
0
2
3
4
5
6
7
8
9
10
11
12
2
3
4
5
6
7
8
9
10
11
12
V+ (V)
V+ (V)
FIGURE 13. INHIBIT TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 14. INHIBIT TURN - OFF TIME vs SUPPLY VOLTAGE
300
250
V
= (V+) - 1V
COM
V
= (V+) - 1V
COM
V- = 0V
250
200
150
100
50
200
150
100
50
25°C
25°C
85°C
85°C
-40°C
-40°C
0
0
2
3
4
5
6
7
8
9
10
11
12
13
2
3
4
5
6
V+ (V)
V± (V)
FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY
VOLTAGE
FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY
VOLTAGE
V
= ±5V
V = ±3V
S
V
= 0.2V
P-P
to 4V
P-P
S
V
= 0.2V
to 5V
P-P P-P
IN
IN
3
0
3
0
GAIN
GAIN
-3
-3
0
0
PHASE
PHASE
45
45
90
90
135
180
135
180
R
= 50Ω
R = 50Ω
L
L
1
10
100
FREQUENCY (MHz)
600
1
10
100
FREQUENCY (MHz)
600
FIGURE 17. FREQUENCY RESPONSE
FIGURE 18. FREQUENCY RESPONSE
FN6213.1
January 27, 2006
12
ISL84582
Typical Performance Curves T = 25°C, Unless Otherwise Specified (Continued)
A
3
-10
-20
-30
-40
-50
-60
-70
-80
-90
10
20
30
40
50
60
70
80
90
V+ = 3V to 12V or
V
= ±2V to ±5V
= 50Ω
2
1
S
R
L
V+ = 3.3V
V- = 0V
V+ = 12V
V- = 0V
0
V+ = 5V
V- = 0V
-1
-2
-3
-4
ISOLATION
V
= ±5V
S
CROSSTALK
-100
-110
100
110
ALL HOSTILE CROSSTALK
-5
0
5
10
12
-2.5
2.5
7.5
1k
10k
100k
1M
10M
100M 500M
V
(V)
COM
FREQUENCY (Hz)
FIGURE 20. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 19. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ISL84582: 193
PROCESS:
Si Gate CMOS
FN6213.1
13
January 27, 2006
ISL84582
Thin Shrink Small Outline Plas tic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
MIN
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
GAUGE
PLANE
SYMBOL
MAX
0.043
0.006
0.037
0.012
0.008
0.201
0.177
MIN
-
MAX
1.10
0.15
0.95
0.30
0.20
5.10
4.50
NOTES
A
A1
A2
b
-
-
0.002
0.033
0.0075
0.0035
0.193
0.169
0.05
0.85
0.19
0.09
4.90
4.30
-
1
2
3
-
L
0.25
0.010
0.05(0.002)
SEATING PLANE
A
9
-A-
c
-
D
D
3
-C-
E1
e
4
α
0.026 BSC
0.65 BSC
-
A2
e
A1
c
E
0.246
0.020
0.256
0.028
6.25
0.50
6.50
0.70
-
b
0.10(0.004)
L
6
0.10(0.004) M
C
A M B S
N
16
16
7
o
o
o
o
0
8
0
8
-
α
NOTES:
Rev. 1 2/02
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6213.1
14
January 27, 2006
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