ISL84684IUZ-T [INTERSIL]
Ultra Low ON-Resistance, Low Voltage, Single Supply, Dual SPDT Analog Switch; 超低导通电阻，低电压，单电源，双路SPDT模拟开关
| 型号： | ISL84684IUZ-T |
| 厂家： | 
Intersil |
| 描述： | Ultra Low ON-Resistance, Low Voltage, Single Supply, Dual SPDT Analog Switch |
| 文件： | 总11页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL84684
®
Data Sheet
June 2004
FN6088
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Dual SPDT Analog Switch
Features
• Pb-Free Available as an Option (see Ordering Info)
The Intersil ISL84684 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.65V to
+3.6V supply. Targeted applications include battery powered
• Drop in Replacement for the MAX4684 and MAX4685
• ON Resistance (R
)
ON
- V+ = +2.7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29Ω
- V+ = +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4Ω
equipment that benefit from low R
(0.25Ω) and fast
= 6ns). The digital logic
ON
switching speeds (t
= 14ns, t
OFF
ON
• R
• R
Matching Between Channels . . . . . . . . . . . . . . . 0.03Ω
Flatness Across Signal Range . . . . . . . . . . . . . . 0.03Ω
ON
input is 1.8V logic-compatible when using a single +3V supply.
ON
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL84684 is offered in small form factor packages, alleviating
board space limitations.
• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +3.6V
• Fast Switching Action (V+ = +2.7V)
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14ns
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ns
OFF
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
• Guaranteed Break-before-Make
The ISL84684 is a committed dual single-pole/double-throw
(SPDT) that consist of two normally open (NO) and two
normally (NC) switches. This configuration can be used as a
dual 2-to-1 multiplexer. The ISL84684 is pin compatible with
the MAX4684 and MAX4685.
• 1.8V Logic Compatible (+3V supply)
• Available in 10 lead 3x3 Thin DFN and 10 lead MSOP
Applications
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
TABLE 1. FEATURES AT A GLANCE
ISL84684
- Pagers
- Laptops, Notebooks, Palmtops
Number of Switches
SW
2
SPDT or 2-1 MUX
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
3V R
0.25Ω
ON
3V t /t
12ns/5ns
ON OFF
1.8V R
0.4Ω
20ns/8ns
ON
1.8V t /t
ON OFF
Packages
10 Ld 3x3 Thin DFN, 10 Ld MSOP
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL84684
Ordering Information
Pinout (Note 1)
ISL84684 (TDFN, MSOP)
PART NO.
TEMP.
PKG.
TOP VIEW
(BRAND)
RANGE (°C)
PACKAGE
DWG. #
ISL84684IR
(684IR)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
10 Ld 3x3 Thin DFN L10.3x3A
V+
1
2
3
4
5
10 NO2
ISL84684IR-T
(684IR)
10 Ld 3x3 Thin DFN L10.3x3A
Tape and Reel
9
8
7
6
NO1
COM1
IN1
COM2
IN2
ISL84684IU
(684IU)
10 Ld MSOP
M10.118
NC2
GND
NC1
ISL84684IU-T
(684IU)
10 Ld MSOP
Tape and Reel
M10.118
ISL84684IRZ*
(684IR)
(See Note)
10 Ld 3x3 Thin DFN L10.3x3A
(Pb-free)
NOTE:
1. Switches Shown for Logic “0” Input.
ISL84684IRZ-T*
(684IR)
(See Note)
-40 to 85
-40 to 85
-40 to 85
10 Ld 3x3 Thin DFN L10.3x3A
Tape and Reel
(Pb-free)
Truth Table
ISL84684IUZ*
(684IU)
(See Note)
10 Ld MSOP
(Pb-free)
M10.118
M10.118
LOGIC
PIN NC1 and NC2 PIN NO1 and NO2
0
1
ON
OFF
ON
OFF
ISL84684IUZ-T*
(684IU)
(See Note)
10 Ld MSOP
Tape and Reel
(Pb-free)
NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-Free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Pin Descriptions
PIN
FUNCTION
System Power Supply Input (+1.65V to +3.6V)
Ground Connection
V+
GND
IN
Digital Control Input
* Pb-free Parts Coming Soon.
COM
NO
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
NC
2
ISL84684
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical)
10 Ld 3x3 TDFN Package (Note 3) . . . . . . . . . . . . .
10 Ld MSOP Package (Note 3) . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.8V
θ
(°C/W)
110
190
JA
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
Operating Conditions
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
MM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
CDM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Temperature Range
ISL84684IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
Unless Otherwise Specified
= 1.4V, V
= 0.5V (Notes 4, 6),
INH
INL
TEMP (NOTE 5)
(NOTE 5)
MAX
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
V+
0.4
0.4
0.06
0.06
0.1
0.1
2
V
Ω
ON Resistance, R
V+ = 2.7V, I
= 100mA, V
or V
= 0V to V+,
= Voltage at
= 0V to V+,
0.29
ON
COM
See Figure 5
NO
NC
Full
25
-
-
Ω
R
Matching Between Channels, V+ = 2.7V, I
ON
= 100mA, V
or V
-
0.03
Ω
ON
∆R
COM
NO
NC
max R , Note 9
ON
Full
25
-
-
Ω
R
Flatness, R
V+ = 2.7V, I
Note 7
= 100mA, V
or V
NC
-
0.03
Ω
ON
FLAT(ON)
COM
NO
Full
25
-
-
-
-
-
-
Ω
NO or NC OFF Leakage Current,
or I
V+ = 3.3V, V
= 0.3V, 3V, V
NO
or V
NC
= 3V, 0.3V
-2
-40
-3
-60
nA
nA
nA
nA
COM
COM
I
NO(OFF)
NC(OFF)
Full
25
40
COM ON Leakage Current,
V+ = 3.3V, V
or Floating
= 0.3V, 3V, or V
or V
= 0.3V, 3V,
NC
3
NO
I
COM(ON)
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
Full
60
V+ = 2.7V, V
See Figure 1, Note 8
or V
= 1.5V, R = 50Ω, C = 35pF,
25
Full
25
-
-
14
-
20
25
12
17
-
ns
ns
ns
ns
ns
ON
NO
NC
L
L
Turn-OFF Time, t
V+ = 2.7V, V or V
See Figure 1, Note 8
= 1.5V, R = 50Ω, C = 35pF,
-
6
-
OFF
NO
NC
L
L
Full
Full
-
Break-Before-Make Time Delay, t
V+ = 3.3V, V or V
See Figure 3, Note 8
= 1.5V, R = 50Ω, C = 35pF,
2
7
D
NO
NC
L
L
Charge Injection, Q
OFF Isolation
C
R
= 1.0nF, V = 0V, R = 0Ω, See Figure 2
25
25
-
-
95
-
-
pC
dB
L
L
G
G
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
,
,
-68
L
COM
RMS
See Figure 4
Crosstalk (Channel-to-Channel)
R
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
25
-
-95
-
dB
L
L
COM
RMS
See Figure 6
Total Harmonic Distortion
f = 20Hz to 20kHz, V
= 2V , R = 600Ω
P-P
25
25
25
-
-
-
0.003
115
-
-
-
%
pF
pF
COM
L
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= 0V, See Figure 7
= 0V, See Figure 7
OFF
NO
NO
NC
NC
COM
COM
COM ON Capacitance, C
= V
224
COM(ON)
3
ISL84684
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
= 1.4V, V
= 0.5V (Notes 4, 6),
(NOTE 5)
INH
INL
Unless Otherwise Specified (Continued)
TEMP (NOTE 5)
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
1.65
3.6
40
V
Positive Supply Current, I+
V+ = +1.65 to 3.6V, V = 0V or V+
IN
-
-
-
-
nA
nA
Full
750
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.5
-
V
V
INL
Input Voltage High, V
1.4
-0.5
INH
Input Current, I , I
INH INL
V+ = 3.3V, V = 0V or V+
IN
0.5
µA
NOTES:
4. V = input voltage to perform proper function.
IN
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Guaranteed by design.
9. R
matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron
ON
value.
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, V
Unless Otherwise Specified
= 1.0V, V
= 0.4V (Note 4, 6),
(NOTE 5)
INH
INL
TEMP (NOTE 5)
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
V+
0.6
0.6
2
V
ON Resistance, R
V+ = 1.8V, I
= 100mA, V
or V = 0V to V+,
NC
0.4
Ω
ON
COM
See Figure 5
NO
Full
25
-
-
-
-
-
-
Ω
NO or NC OFF Leakage Current,
or I
V+ = 2.0V, V
COM
= 0.3V, 1.8V, V
NO
or V
= 1.8V, 0.3V
or V = 0.3V,
NO NC
-2
-40
-3
-60
nA
nA
nA
nA
NC
I
NO(OFF)
NC(OFF)
Full
25
40
3
COM ON Leakage Current,
V+ = 2.0V, V
COM
= 0.3V, 1.8V, or V
I
1.8V, or Floating
COM(ON)
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
Full
60
V+ = 1.65V, V
or V
= 1.0V, R =50Ω, C = 35pF,
25
Full
25
-
-
22
-
28
33
15
20
-
ns
ns
ns
ns
ns
ON
NO
See Figure 1, Note 8
NC
NC
L
L
Turn-OFF Time, t
V+ = 1.65V, V or V
= 1.0V, R =50Ω, C = 35pF,
-
9
-
OFF
NO
See Figure 1, Note 8
L
L
Full
Full
-
Break-Before-Make Time Delay, t
V+ = 2.0V, V or V
See Figure 3, Note 8
= 1.0V, R =50Ω, C = 35pF,
2
9
D
NO
NC
L
L
Charge Injection, Q
OFF Isolation
C
R
= 1.0nF, V = 0V, R = 0Ω, See Figure 2
25
25
-
-
49
-
-
pC
dB
L
L
G
G
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
,
,
-68
L
COM
RMS
See Figure 4
Crosstalk (Channel-to-Channel)
R
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
25
-
-95
-
dB
L
L
COM
RMS
See Figure 6
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V, See Figure 7
= 0V, See Figure 7
25
25
-
-
115
224
-
-
pF
pF
OFF
NO
NO
NC
NC
COM
COM
COM ON Capacitance, C
COM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.4
-
V
V
INL
Input Voltage High, V
1.0
-0.5
INH
Input Current, I
, I
V+ = 2.0V, V = 0V or V+
IN
0.5
µA
INH INL
4
ISL84684
Test Circuits and Waveforms
V+
C
V
t < 20ns
r
INH
t < 20ns
f
LOGIC
INPUT
50%
V
INL
V
OUT
t
NO or NC
IN
OFF
SWITCH
INPUT
COM
SWITCH
INPUT
V
NO
0V
V
OUT
90%
90%
C
L
R
LOGIC
INPUT
L
GND
SWITCH
OUTPUT
35pF
50Ω
t
ON
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
------------------------------
V
= V
OUT
(NO or NC)
R
+ R
L
(ON)
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
V
R
OUT
G
COM
NO or NC
GND
SWITCH
OUTPUT
∆V
OUT
V
V
OUT
IN
G
C
L
V
INH
ON
ON
LOGIC
INPUT
LOGIC
INPUT
OFF
V
INL
Q = ∆V
x C
L
OUT
Repeat test for all switches.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
C
V
INH
NO
LOGIC
INPUT
V
V
OUT
NX
COM
NC
V
INL
C
R
L
L
50Ω
35pF
IN
GND
90%
LOGIC
INPUT
SWITCH
OUTPUT
V
OUT
0V
t
D
Repeat test for all switches. C includes fixture and stray
L
capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
5
ISL84684
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
NO or NC
R
= V /100mA
1
ON
NO or NC
V
NX
IN
0V or V+
V
or V
INH
100mA
INL
IN
V
1
COM
ANALYZER
GND
COM
R
L
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. R
TEST CIRCUIT
ON
V+
C
V+
C
SIGNAL
50Ω
GENERATOR
ANALYZER
NO or NC
COM
NO or NC
IN
1
V
or V
INH
IN
INL
0V or V+
IMPEDANCE
ANALYZER
NC or NO
COM
COM
N.C.
GND
GND
R
L
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Supply Sequencing and Overvoltage Protection
Detailed Description
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
The ISL84684 is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 3.6V supply with low on-
resistance (0.29Ω) and high speed operation (t
= 14ns,
ON
= 6ns). The device is especially well suited for portable
t
OFF
battery powered equipment due to its low operating supply
voltage (1.65V), low power consumption (2.7µW max), low
leakage currents (60nA max), and the tiny Thin DFN and
MSOP packages. The ultra low on-resistance and Ron
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
6
ISL84684
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.0V to 3.6V (see Figure 15). At 3.6V
purpose of using a low R
switch, so two small signal
ON
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.
the V level is about 1.27V. This is still below the 1.8V
IH
CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
OPTIONAL PROTECTION
DIODE
In 50Ω systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 120MHz (see Figure
16). The frequency response is very consistent over a wide
V+ range, and for varying analog signal levels.
V+
OPTIONAL
PROTECTION
RESISTOR
IN
V
X
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
the resistance to this feedthrough, while Crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 17 details the high Off Isolation and Crosstalk
rejection provided by this part. At 100kHz, Off Isolation is
about 68dB in 50Ω systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
V
NO or NC
COM
GND
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
Power-Supply Considerations
The ISL84684 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL84684 4.8V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
The minimum recommended supply voltage is 1.65V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and on-
resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shiftiers.
The level shiftiers convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
7
ISL84684
Typical Performance Curves T = 25°C, Unless Otherwise Specified
A
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.32
V+ = 2.7V
= 100mA
I
= 100mA
COM
I
V+ = 1.5V
COM
0.3
85°C
25°C
0.28
0.26
0.24
0.22
0.2
V+ = 1.8V
V+ = 3.6V
V+ = 2.7V
-40°C
V+ = 3V
1
0.18
0
0.5
1
1.5
(V)
2
2.5
3
0
2
3
4
V
V
(V)
COM
COM
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
100
0.5
V+ = 1.8V
= 100mA
I
COM
75
50
25
0
0.45
0.4
85°C
V+ = 3V
0.35
0.3
V+ = 1.8V
25°C
-40°C
-25
-50
0.25
0.2
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
V (V)
V
(V)
COM
COM
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
60
14
13
12
11
10
50
40
30
20
10
9
8
7
6
5
4
3
85°C
-40°C
25°C
85°C
25°C
-40°C
1
1.5
2
2.5
V+ (V)
3
3.5
4
4.5
1.5
2
2.5
V+ (V)
3
3.5
4
4.5
1
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
8
ISL84684
Typical Performance Curves T = 25°C, Unless Otherwise Specified (Continued)
A
1.5
V+ = 3V
1.4
1.3
1.2
1.1
1
0
-3
-6
GAIN
V
0
INH
PHASE
0.9
0.8
0.7
0.6
0.5
0.4
0.3
20
40
60
80
100
V
INL
R
IN
= 50Ω
L
V
= 0.2V
to 2V
P-P
P-P
10
1
1.5
2
2.5
3
3.5
4
4.5
1
100
FREQUENCY (MHz)
600
V+ (V)
FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 16. FREQUENCY RESPONSE
-10
-20
-30
-40
-50
-60
-70
-80
-90
10
20
30
40
50
60
70
80
90
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V+ = 3V
GND
TRANSISTOR COUNT:
114
PROCESS:
ISOLATION
Submicron CMOS
CROSSTALK
-100
-110
100
110
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 17. CROSSTALK AND OFF ISOLATION
9
ISL84684
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
0.15 C
A
A
D
MILLIMETERS
2X
0.15
C B
SYMBOL
MIN
0.70
NOMINAL
MAX
0.80
NOTES
A
A1
A3
b
0.75
-
-
0.20
2.20
1.40
-
0.20 REF
0.25
0.05
-
E
-
6
0.30
2.40
1.60
5,8
INDEX
AREA
D
3.00 BSC
2.30
-
D2
E
7,8
TOP VIEW
SIDE VIEW
B
A
3.00 BSC
1.50
-
// 0.10
0.08
C
E2
e
7,8
0.50 BSC
-
-
C
k
0.25
0.20
-
-
0.40
0.15
-
A3
C
L
0.30
8
SEATING
PLANE
L1
N
-
1
10
2
D2
D2/2
2
7
8
(DATUM B)
Nd
5
3
Rev. 1 6/04
1
6
NOTES:
INDEX
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
NX k
E2
AREA
(DATUM A)
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
10. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
NX L
N
N-1
NX b
5
8
e
(Nd-1)Xe
M
0.10
C A B
REF.
BOTTOM VIEW
(A1)
C
L
NX (b)
L1
L
9
5
e
SECTION "C-C"
TERMINAL TIP
C C
FOR ODD TERMINAL/SIDE
10
ISL84684
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.18
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.27
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.007
0.004
0.116
0.116
0.043
0.006
0.037
0.011
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
L
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
0.020 BSC
0.50 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
SEATING
PLANE
L1
N
0.037 REF
10
0.95 REF
10
-
0.10 (0.004)
-A-
C
C
b
7
-H-
A1
e
R
0.003
-
0.07
-
-
-
D
0.20 (0.008)
C
R1
θ
0.003
-
0.07
-
o
o
o
o
a
SIDE VIEW
5
15
5
15
-
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 0 12/02
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
-A -
10. Datums
and
to be determined at Datum plane
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
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