HFA1109IB [INTERSIL]
450MHz, Low Power, Current Feedback Video Operational Amplifier; 450MHz的低功耗，电流反馈视频运算放大器
| 型号： | HFA1109IB |
| 厂家： | 
Intersil |
| 描述： | 450MHz, Low Power, Current Feedback Video Operational Amplifier |
| 文件： | 总12页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFA1109
450MHz, Low Power, Current Feedback
Video Operational Amplifier
March 1997
Features
Description
• Wide - 3dB Bandwidth (A = +2). . . . . . . . . . . . 450MHz The HFA1109 is a high speed, low power, current feedback
V
amplifier built with Intersil’s proprietary complementary bipo-
lar UHF-1 process. This amplifier features a unique combi-
• Gain Flatness (To 250MHz) . . . . . . . . . . . . . . . . . . 0.8dB
nation of power and performance specifically tailored for
video applications.
• Very Fast Slew Rate (A = +2). . . . . . . . . . . . . 1100V/µs
V
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . 1.7MΩ
• Differential Gain/Phase . . . . . . . . . 0.02%/0.02 Degrees
• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . 10mA
The HFA1109 is a standard pinout op amp. It is a higher
performance, drop-in replacement (no feedback resistor
change required) for the CLC409.
If a comparably performing op amp with an output disable
function (useful for video multiplexing) is required, please
refer to the HFA1149 data sheet.
Applications
• Professional Video Processing
• Video Switchers and Routers
• Medical Imaging
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE ( C)
PKG.
NO.
o
PACKAGE
8 Ld PDIP
• PC Multimedia Systems
• Video Distribution Amplifiers
• Flash Converter Drivers
• Radar/IF Processing
HFA1109IP
-40 to 85
E8.3
M8.15
HFA1109IB (H1109)
HFA11XXEVAL
-40 to 85
8 Ld SOIC
DIP Evaluation Board for High Speed
Op Amps
Pinout
HFA1109
(PDIP, SOIC)
TOP VIEW
NC
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC
V+
-
+
OUT
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 4019.3
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
HFA1109
Absolute Maximum Ratings
Thermal Information
o
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Output Current (Note 2) . . . . . . . . . . . . . . . . Short Circuit Protected
30mA Continuous
Thermal Resistance (Typical, Note 1)
θJA ( C/W)
SUPPLY
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
170
o
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . . 175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300 C
o
o
o
60mA ≤ 50% Duty Cycle
o
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . 1400V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93). . . 2000V
Machine Model (Per EIAJ ED-4701Method C-111) . . . . . . . . 50V
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
2. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle)
output current must not exceed 30mA for maximum reliability.
Electrical Specifications
V
= ±5V, A = +2, R = 250Ω, R = 100Ω, Unless Otherwise Specified
SUPPLY V F L
(NOTE 3)
TEST
LEVEL
TEMP.
( C)
o
PARAMETER
INPUT CHARACTERISTICS
Input Offset Voltage
TEST CONDITIONS
MIN
TYP
MAX
UNITS
A
A
B
A
A
A
A
A
A
B
A
A
A
A
B
A
A
A
A
A
A
B
B
25
Full
Full
25
-
1
2
5
8
-
mV
mV
-
o
Average Input Offset Voltage Drift
-
10
50
48
53
51
4
µV/ C
Input Offset Voltage
Common-Mode Rejection Ratio
∆V
∆V
= ±2V
= ±2V
47
-
dB
dB
dB
dB
µA
µA
CM
Full
25
45
-
CM
Input Offset Voltage
Power Supply Rejection Ratio
∆V = ±1.25V
PS
50
-
∆V = ±1.25V
PS
Full
25
47
-
Non-Inverting Input Bias Current
-
10
15
-
Full
Full
25
-
5
o
Non-Inverting Input Bias Current Drift
-
30
0.5
0.5
2
nA/ C
Non-Inverting Input Bias Current
Power Supply Sensitivity
∆V = ±1.25V
PS
-
1
3
10
15
-
µA/V
µA/V
µA
∆V = ±1.25V
PS
Full
25
-
Inverting Input Bias Current
-
Full
Full
25
-
3
µA
o
Inverting Input Bias Current Drift
-
40
3
nA/ C
Inverting Input Bias Current
Common-Mode Sensitivity
∆V
∆V
= ±2V
= ±2V
-
6
8
5
8
-
µA/V
µA/V
µA/V
µA/V
MΩ
MΩ
Ω
CM
Full
25
-
3
CM
Inverting Input Bias Current
Power Supply Sensitivity
∆V = ±1.25V
PS
-
-
1.6
1.6
1.7
1.4
60
1.6
∆V = ±1.25V
PS
Full
25, 85
-40
25
Non-Inverting Input Resistance
∆V
= ±2V
= ±2V
0.8
0.5
-
CM
CM
∆V
-
Inverting Input Resistance
Input Capacitance
-
25
-
-
pF
2
HFA1109
Electrical Specifications
V
= ±5V, A = +2, R = 250Ω, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
(NOTE 3)
TEST
LEVEL
TEMP.
( C)
o
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Common Mode Range
A
Full
±2
±2.5
-
V
(Implied by V CMRR, +R , and -I
IO IN BIAS
CMS tests)
Input Noise Voltage Density (Note 4)
f = 100kHz
B
B
25
25
-
-
4
-
-
nV/√Hz
pA/√Hz
Non-Inverting Input Noise Current Density
(Note 4)
f = 100kHz
2.4
Inverting Input Noise Current Density
(Note 4)
f = 100kHz
B
25
-
40
-
pA/√Hz
TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain (Note 4)
Minimum Stable Gain
B
B
25
-
-
500
1
-
-
kΩ
Full
V/V
AC CHARACTERISTICS
-3dB Bandwidth
A
A
= -1, R = 200Ω
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
25
Full
25
300
290
280
260
390
350
-
375
360
-
MHz
MHz
MHz
MHz
MHz
MHz
dB
V
V
F
(V
OUT
= 0.2V
, Note 4)
P-P
-
= +1, +R = 550Ω (PDIP),
330
-
S
+R = 700Ω (SOIC)
S
Full
25
320
-
A
A
= +2
450
-
V
V
Full
25
410
-
Gain Peaking
Gain Flatness
= +2, V
= 0.2V
0
0.2
OUT
P-P
Full
25
-
0
0.5
dB
To 125MHz
To 200MHz
To 250MHz
To 125MHz
To 200MHz
To 250MHz
-1.0
-1.1
-1.6
-1.7
-1.9
-2.2
±0.3
±0.4
±0.8
±0.9
±1.3
±1.4
-0.45
-0.45
-0.75
-0.75
-0.85
-0.85
±0.1
±0.1
±0.35
±0.35
±0.6
±0.6
-
-
-
-
-
-
-
-
-
-
-
-
dB
(A = +2, V
= 0.2V , Note 4)
OUT P-P
V
Full
25
dB
dB
Full
25
dB
dB
Full
25
dB
Gain Flatness
(A = +1, +R = 550Ω (PDIP),
dB
V
S
Full
25
dB
+R = 700Ω (SOIC), V
= 0.2V ,
P-P
S
OUT
Note 4)
dB
Full
25
dB
dB
Full
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing, Unloaded
(Note 4)
A
A
A
= -1, R = ∞
A
A
A
A
B
B
B
B
25
Full
25, 85
-40
25
±3
±3.2
±3
-
-
-
-
-
-
-
-
V
V
V
V
L
±2.8
V
Output Current
(Note 4)
= -1, R = 75Ω
±33
±36
±33
120
0.05
-55
mA
mA
mA
Ω
L
±30
Output Short Circuit Current
= -1
-
-
-
-
Closed Loop Output Resistance (Note 4)
Second Harmonic Distortion
DC, A = +1
V
25
20MHz
60MHz
25
dBc
dBc
(V
OUT
= 2V , Note 4)
P-P
25
-57
3
HFA1109
Electrical Specifications
V
= ±5V, A = +2, R = 250Ω, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
(NOTE 3)
TEST
LEVEL
TEMP.
( C)
o
PARAMETER
TEST CONDITIONS
20MHz
MIN
TYP
-68
-60
-65
MAX
UNITS
dBc
Third Harmonic Distortion
B
B
B
25
25
25
-
-
-
-
-
-
(V
= 2V , Note 4)
P-P
OUT
60MHz
30MHz
dBc
Reverse Isolation (S
12
)
dB
TRANSIENT CHARACTERISTICS
Rise and Fall Times
V
V
= 0.5V
= 0.5V
B
B
B
B
B
B
B
B
25
Full
25
-
-
1.1
1.1
1.3
ns
ns
OUT
OUT
P-P
1.4
Overshoot
Slew Rate
-
0
2
5
-
%
P-P
Full
25
-
0.5
%
A
V
= -1, R = 200Ω
2300
2200
475
430
2600
2500
550
500
V/µs
V/µs
V/µs
V/µs
V
F
= 5V
OUT
P-P
Full
25
-
A
= +1, V
= 4V
,
-
V
OUT
P-P
+R = 550Ω (PDIP),
+R = 700Ω (SOIC)
S
Full
-
S
A
= +2, V
OUT
= 5V
B
B
B
B
B
B
25
Full
25
940
1100
950
19
-
-
-
-
-
-
V/µs
V/µs
ns
V
P-P
800
Settling Time
To 0.1%
To 0.05%
To 0.01%
-
-
-
-
(V
OUT
= +2V to 0V step, Note 4)
25
23
ns
25
36
ns
Overdrive Recovery Time
V
= ±2V
= 150Ω
= 75Ω
= 150Ω
= 75Ω
25
5
ns
IN
VIDEO CHARACTERISTICS
Differential Gain
(f = 3.58MHz)
R
R
R
R
B
B
B
B
B
B
B
B
25
Full
25
-
-
-
-
-
-
-
-
0.02
0.03
0.04
0.05
0.02
0.02
0.05
0.06
0.06
0.09
0.09
0.12
%
%
%
%
L
L
L
L
Full
25
Differential Phase
(f = 3.58MHz)
0.06 Degrees
0.06 Degrees
0.09 Degrees
0.13 Degrees
Full
25
Full
POWER SUPPLY CHARACTERISTICS
Power Supply Range
C
A
A
25
25
±4.5
-
±5.5
10
V
Power Supply Current (Note 4)
-
-
9.6
10
mA
mA
Full
11
NOTES:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. See Typical Performance Curves for more information.
4
HFA1109
ble oscillations. In most cases, the oscillation can be avoided
Application Information
Optimum Feedback Resistor
by placing a resistor (R ) in series with the output prior to
S
the capacitance.
Although a current feedback amplifier’s bandwidth depen-
dency on closed loop gain isn’t as severe as that of a voltage
feedback amplifier, there can be an appreciable decrease in
bandwidth at higher gains. This decrease may be minimized
by taking advantage of the current feedback amplifier’s
R
and C form a low pass network at the output, thus limit-
L
S
ing system bandwidth well below the amplifier bandwidth. By
decreasing R as C increases, the maximum bandwidth is
obtained without sacrificing stability. In spite of this, band-
width still decreases as the load capacitance increases.
S
L
unique relationship between bandwidth and R . All current
F
feedback amplifiers require a feedback resistor, even for
Evaluation Board
unity gain applications, and R , in conjunction with the inter-
F
nal compensation capacitor, sets the dominant pole of the
frequency response. Thus, the amplifier’s bandwidth is
The performance of the HFA1109 may be evaluated using
the
HFA11XX
evaluation
board
(part
number
inversely proportional to R . The HFA1109 design is opti-
F
HFA11XXEVAL). Please contact your local sales office for
information. When evaluating this amplifier, the two 510Ω
gain setting resistors on the evaluation board should be
changed to 250Ω.
mized for a 250Ω R at a gain of +2. Decreasing R
F
F
decreases stability, resulting in excessive peaking and over-
shoot (Note: Capacitive feedback will cause the same prob-
lems due to the feedback impedance decrease at higher
frequencies). At higher gains the amplifier is more stable, so
The layout and schematic of the board are shown in Figure 1.
R can be decreased in a trade-off of stability for bandwidth.
F
.
BOARD SCHEMATIC
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN (A
)
R
(Ω)
F
BANDWIDTH (MHz)
CL
510Ω
510Ω
50Ω
V
-1
200
400
350
H
+1
250 (+R = 550Ω) PDIP
S
1
2
3
4
8
7
6
5
0.1µF
50Ω
10µF
+5V
250 (+R = 700Ω) SOIC
S
+2
+5
250
100
90
450
160
70
IN
OUT
V
L
+10
10µF
0.1µF
GND
GND
Table 1 lists recommended R values, and the expected
F
-5V
bandwidth, for various closed loop gains. For a gain of +1, a
resistor (+R ) in series with +IN is required to reduce gain
peaking and increase stability
S
TOP LAYOUT
PC Board Layout
V
H
The frequency response of this amplifier depends greatly on
the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid ground
plane is a must! Attention should be given to decoupling the
power supplies. A large value (10µF) tantalum in parallel with a
small value (0.1µF) chip capacitor works well in most cases.
1
+IN
OUT
V-
V+
V
L
GND
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
BOTTOM LAYOUT
Care must also be taken to minimize the capacitance to ground
seen by the amplifier’s inverting input (-IN). The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. Thus it is recommended that
the ground plane be removed under traces connected to -IN,
and connections to -IN should be kept as short as possible.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly ter-
minated transmission line will degrade the amplifier’s phase
margin resulting in frequency response peaking and possi-
FIGURE 1. EVALUATION BOARD SCHEMATIC AND LAYOUT
5
HFA1109
o
Typical Performance Curves V
= ±5V, T = 25 C, R = Value From the Optimum Feedback Resistor Table,
SUPPLY
A
F
R
= 100Ω, Unless Otherwise Specified
L
200
150
100
50
2.0
A
= +2
A = +2
V
V
1.5
1.0
0.5
0
0
-50
-100
-0.5
-1.0
-150
-200
-1.5
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 2. SMALL SIGNAL PULSE RESPONSE
FIGURE 3. LARGE SIGNAL PULSE RESPONSE
200
150
100
50
2.0
1.5
1.0
0.5
0
A
= +1
A = +1
V
V
0
-50
-100
-0.5
-1.0
-150
-200
-1.5
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 4. SMALL SIGNAL PULSE RESPONSE
FIGURE 5. LARGE SIGNAL PULSE RESPONSE
200
150
100
50
2.0
1.5
1.0
0.5
0
A
= -1
A = -1
V
V
0
-50
-100
-0.5
-1.0
-150
-200
-1.5
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 6. SMALL SIGNAL PULSE RESPONSE
FIGURE 7. LARGE SIGNAL PULSE RESPONSE
6
HFA1109
o
Typical Performance Curves V
= ±5V, T = 25 C, R = Value From the Optimum Feedback Resistor Table,
SUPPLY
A
F
R
= 100Ω, Unless Otherwise Specified (Continued)
L
2.0
200
150
100
50
1.5
A
= +5
A
= +5
V
V
1.0
0.5
0
A
= +10
A
= +10
V
A
= +10
V
V
0
A
= +10
V
-0.5
-1.0
-50
-100
A
= +5
V
A
= +5
V
-150
-200
-1.5
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 9. LARGE SIGNAL PULSE RESPONSE
FIGURE 8. SMALL SIGNAL PULSE RESPONSE
V
= 200mV
P-P
V
= 200mV
P-P
OUT
OUT
3
3
0
A
= +2
V
GAIN
A
= +1
GAIN
V
0
A
= +10
-3
-3
V
A
= +5
V
A
= +1
V
A
= +2
PHASE
V
PHASE
A
V
= -1
0
0
90
90
A
= +1
A
= +10
V
V
180
270
180
270
A
= +5
V
A
= -1
V
0.3
1
10
FREQUENCY (MHz)
100
700
0.3
1
10
FREQUENCY (MHz)
100
700
FIGURE 10. FREQUENCY RESPONSE
FIGURE 11. FREQUENCY RESPONSE
116
106
96
86
76
66
56
46
36
26
V
= 200mV
P-P
OUT
0.1
0
A
= +1
V
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
0
45
90
135
180
A
= +2
V
0.01
0.1
0.3
1
3
6 10 30 100
500
1
10
FREQUENCY (MHz)
100
500
FREQUENCY (MHz)
FIGURE 12. GAIN FLATNESS
FIGURE 13. OPEN LOOP TRANSIMPEDANCE
7
HFA1109
o
Typical Performance Curves V
= ±5V, T = 25 C, R = Value From the Optimum Feedback Resistor Table,
SUPPLY
A
F
R
= 100Ω, Unless Otherwise Specified (Continued)
L
-30
-40
-50
-20
A
= +1
A
= +1
V
V
100MHz
-30
-40
100MHz
-50
50MHz
50MHz
-60
-70
-80
-90
-60
20MHz
10MHz
-70
20MHz
10MHz
-80
-90
-100
-6
-3
0
3
6
9
12
-6
-3
0
3
6
9
12
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 14. 2nd HARMONIC DISTORTION vs P
FIGURE 15. 3rd HARMONIC DISTORTION vs P
OUT
OUT
-30
-40
-50
-30
-40
-50
A
= +2
A
= +2
V
V
100MHz
100MHz
50MHz
10MHz
50MHz
-60
-70
-80
-90
-60
-70
-80
-90
20MHz
20MHz
10MHz
-6
-3
0
3
6
9
12
15
-6
-3
0
3
6
9
12
15
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 16. 2nd HARMONIC DISTORTION vs P
FIGURE 17. 3rd HARMONIC DISTORTION vs P
OUT
OUT
-20
-30
-40
-50
-60
-70
-80
-20
-30
-40
-50
-60
-70
-80
V
= 2V
P-P
V
= 2V
P-P
OUT
OUT
A
= +1
= -1
V
A
V
A
= +2
V
A
= +2, -1
V
A
= +1
V
A
= +1
20
V
0
10
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90 100
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 18. 2nd HARMONIC DISTORTION vs FREQUENCY
FIGURE 19. 3rd HARMONIC DISTORTION vs FREQUENCY
8
HFA1109
o
Typical Performance Curves V
= ±5V, T = 25 C, R = Value From the Optimum Feedback Resistor Table,
SUPPLY
A
F
R
= 100Ω, Unless Otherwise Specified (Continued)
L
3.6
A
= +2
V
+V
OUT
(R = 100Ω)
L
3.4
3.2
3.0
|-V
OUT
| (R = 100Ω)
L
1K
100
10
+V
OUT
(R = 50Ω)
L
+V
OUT
(R = 50Ω)
L
2.8
2.6
1
|-V
OUT
| (R = 100Ω)
L
0.1
0.01
2.4
2.2
|-V
OUT
| (R = 50Ω)
L
2.0
1.8
1.6
0.3
1
10
100
1000
-75
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
FREQUENCY (MHz)
FIGURE 20. CLOSED LOOP OUTPUT RESISTANCE
FIGURE 21. OUTPUT VOLTAGE vs TEMPERATURE
14
17
16
15
14
13
12
11
10
9
13.5
13
V
= ±8V
12.5
12
S
11.5
11
V
= ±5V
S
10.5
10
8
7
9.5
9
V
= ±4V
S
6
5
8.5
4
-75
4
4.5
5
5.5
6
6.5
7
7.5
8
-50
-25
0
25
50
75
100
125
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
FIGURE 22. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 23. SUPPLY CURRENT vs TEMPERATURE
100
100
A
= +2
V
V
= 2V
OUT
0.1
I
NI-
0.05
I
NI+
0.025
0
10
10
-0.025
-0.05
E
NI
I
-0.1
NI+
1
100
1
0.1
10
20 30 40 50
60
70 80
90 100
1
10
TIME (ns)
FREQUENCY (kHz)
FIGURE 24. INPUT NOISE CHARACTERISTICS
FIGURE 25. SETTLING RESPONSE
9
HFA1109
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
59 mils x 80 mils x 19 mils
Type: Nitride
1500µm x 2020µm x 483µm
Thickness: 4kÅ ±0.5kÅ
METALLIZATION:
TRANSISTOR COUNT:
Type: Metal 1: AICu(2%)/TiW
130
Thickness: Metal 1: 8kÅ ±0.4kÅ
SUBSTRATE POTENTIAL (Powered Up):
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kÅ 0.8kÅ
Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1109
NC
NC
NC
NC
V+
-IN
OUT
NC
NC
+IN
V-
NC
NC
10
HFA1109
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INCHES MILLIMETERS
INDEX
AREA
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
A
A1
A2
B
-
4
-B-
-C-
-A-
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
D
E
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
BASE
PLANE
-
A2
A
SEATING
PLANE
B1
C
8, 10
L
C
L
-
D1
B1
eA
A1
A
D1
D
5
e
C
eC
D1
E
5
B
eB
0.010 (0.25)
C
B
S
M
0.325
0.280
8.25
7.11
6
E1
e
5
NOTES:
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
e
e
6
A
-
0.430
0.150
-
10.92
3.81
7
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
B
L
0.115
2.93
4
9
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
N
8
8
4. Dimensions A, A1 and L are measured with the package seated
Rev. 0 12/93
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
11
HFA1109
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
M
M
B
0.25(0.010)
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
o
D
h x 45
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
M
M
S
B
0.25(0.010)
C
A
N
α
8
8
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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12
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