HFA1109IBZ [INTERSIL]
450MHz, Low Power, Current Feedback Video Operational Amplifier; 450MHz的低功耗，电流反馈视频运算放大器
| 型号： | HFA1109IBZ |
| 厂家： | 
Intersil |
| 描述： | 450MHz, Low Power, Current Feedback Video Operational Amplifier |
| 文件： | 总12页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFA1109
®
Data Sheet
April 23, 2007
FN4019.5
450MHz, Low Power, Current Feedback
Video Operational Amplifier
Features
• Wide - 3dB Bandwidth (A = +2) . . . . . . . . . . . . . 450MHz
V
The HFA1109 is a high speed, low power, current feedback
amplifier built with Intersil’s proprietary complementary
bipolar UHF-1 process. This amplifier features a unique
combination of power and performance specifically tailored
for video applications.
• Gain Flatness (To 250MHz) . . . . . . . . . . . . . . . . . . . 0.8dB
• Very Fast Slew Rate (A = +2). . . . . . . . . . . . . . 1100V/μs
V
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 1.7MΩ
• Differential Gain/Phase . . . . . . . . . . . . . . . . . 0.02%/0.02°
• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Pb-Free Plus Anneal Available (RoHS Compliant)
The HFA1109 is a standard pinout op amp. It is a higher
performance, drop-in replacement (no feedback resistor
change required) for the CLC409.
If a comparably performing op amp with an output disable
function (useful for video multiplexing) is required, please
refer to the HFA1149 data sheet..
Applications
• Professional Video Processing
• Video Switchers and Routers
• Medical Imaging
Ordering Information
TEMP.
PART
NUMBER
PART
MARKING
RANGE
(°C)
PKG.
DWG. #
• PC Multimedia Systems
• Video Distribution Amplifiers
• Flash Converter Drivers
• Radar/IF Processing
PACKAGE
HFA1109IB
1109IB
-40 to +85 8 Ld SOIC (150MIL) M8.15
HFA1109IBZ
(Note 1)
HFA1109
IBZ
-40 to +85 8 Ld SOIC (150MIL) M8.15
(Pb-free)
HFA1109IBZ96 HFA1109
(Note 1) IBZ
-40 to +85 8 Ld SOIC (150MIL) M8.15
(Pb-free)
Pinout
HFA11XXEVAL DIP Evaluation Board for High Speed Op Amps
(Note 2)
HFA1109
(8 LD SOIC)
TOP VIEW
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
NC
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC
V+
-
+
OUT
NC
2. Requires a SOIC-to-DIP adapter. See “Evaluation Board” section
inside.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2004, 2007. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HFA1109
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Thermal Resistance (Typical, Note 3)
θ
(°C/W)
170
JA
SUPPLY
8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
Output Current (Note 4) . . . . . . . . . . . . . . . . .Short Circuit Protected
30mA Continuous
60mA ≤ 50% Duty Cycle
ESD Rating
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . +175°C
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .1400V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . . .2000V
Machine Model (Per EIAJ ED-4701Method C-111) . . . . . . . . . .50V
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
4. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output
current must not exceed 30mA for maximum reliability.
Electrical Specifications
V
= ±5V, A = +2, R = 250Ω, R = 100Ω, Unless Otherwise Specified.
SUPPLY V F L
(NOTE 5)
TEST
PARAMETER
INPUT CHARACTERISTICS
Input Offset Voltage
TEST CONDITIONS
LEVEL
TEMP. (°C)
MIN
TYP
MAX
UNITS
A
A
B
A
A
A
A
A
A
B
A
A
A
A
B
A
A
A
A
A
A
B
25
Full
Full
25
-
1
2
5
8
-
mV
mV
-
Average Input Offset Voltage Drift
-
10
50
48
53
51
4
μV/°C
dB
Input Offset Voltage
Common-Mode Rejection Ratio
DV
= ±2V
47
-
CM
Full
25
45
-
dB
Input Offset Voltage
Power Supply Rejection Ratio
DV = ±1.25V
PS
50
-
dB
Full
25
47
-
dB
Non-Inverting Input Bias Current
-
10
15
-
μA
Full
Full
25
-
5
μA
Non-Inverting Input Bias Current Drift
-
30
0.5
0.5
2
nA/°C
μA/V
μA/V
μA
Non-Inverting Input Bias Current
Power Supply Sensitivity
DV = ±1.25V
PS
-
1
3
10
15
-
Full
25
-
Inverting Input Bias Current
-
Full
Full
25
-
3
μA
Inverting Input Bias Current Drift
-
40
3
nA/°C
μA/V
μA/V
μA/V
μA/V
MΩ
MΩ
Ω
Inverting Input Bias Current
Common-Mode Sensitivity
DV
= ±2V
-
6
8
5
8
-
CM
Full
25
-
-
3
Inverting Input Bias Current
Power Supply Sensitivity
DV = ±1.25V
PS
1.6
1.6
1.7
1.4
60
Full
25, 85
-40
25
-
Non-Inverting Input Resistance
DV
= ±2V
0.8
0.5
-
CM
-
Inverting Input Resistance
-
FN4019.5
April 23, 2007
2
HFA1109
Electrical Specifications
V
= ±5V, A = +2, R = 250Ω, R = 100Ω, Unless Otherwise Specified. (Continued)
SUPPLY
V
F
L
(NOTE 5)
TEST
PARAMETER
TEST CONDITIONS
LEVEL
TEMP. (°C)
MIN
-
TYP
1.6
MAX
UNITS
pF
Input Capacitance
B
A
25
-
-
Input Voltage Common Mode Range
Full
±2
±2.5
V
(Implied by V CMRR, +R , and -I
CMS
IO IN
BIAS
tests)
Input Noise Voltage Density (Note 6)
f = 100kHz
B
B
25
25
-
-
4
-
-
nV/√Hz
pA/√Hz
Non-Inverting Input Noise Current Density
(Note 4)
2.4
Inverting Input Noise Current Density
(Note 4)
f = 100kHz
B
25
-
40
-
pA/√Hz
TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain (Note 6)
Minimum Stable Gain
B
B
25
-
-
500
1
-
-
kΩ
Full
V/V
AC CHARACTERISTICS
-3dB Bandwidth
A
= -1, R = 200Ω
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
25
Full
25
300
290
280
260
390
350
-
375
360
-
MHz
MHz
MHz
MHz
MHz
MHz
dB
V
F
(V
= 0.2V , Note 6)
P-P
OUT
-
A
= +1, +R = 550Ω (PDIP),
330
-
V
S
+R = 700Ω (SOIC)
S
Full
25
320
-
A
= +2
450
-
V
Full
25
410
-
Gain Peaking
Gain Flatness
A
= +2, V
= 0.2V
P-P
0
0.2
V
OUT
Full
25
-
0
0.5
dB
To 125MHz
To 200MHz
To 250MHz
To 125MHz
To 200MHz
To 250MHz
-1.0
-1.1
-1.6
-1.7
-1.9
-2.2
±0.3
±0.4
±0.8
±0.9
±1.3
±1.4
-0.45
-0.45
-0.75
-0.75
-0.85
-0.85
±0.1
±0.1
±0.35
±0.35
±0.6
±0.6
-
-
-
-
-
-
-
-
-
-
-
-
dB
(A = +2, V
= 0.2V , Note 6)
V
OUT P-P
Full
25
dB
dB
Full
25
dB
dB
Full
25
dB
Gain Flatness
(A = +1, +R = 550Ω (PDIP),
dB
V
S
Full
25
dB
+R = 700Ω (SOIC), V
= 0.2V
,
P-P
S
OUT
(Note 6)
dB
Full
25
dB
dB
Full
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing, Unloaded
(Note 6)
A
= -1, R = Infinity
A
A
A
A
B
B
25
Full
25, 85
-40
±3
±2.8
±33
±30
-
±3.2
±3
-
-
-
-
-
-
V
V
L
V
Output Current
(Note 6)
A
= -1, R = 75Ω
±36
±33
120
0.05
mA
mA
mA
W
V
L
Output Short Circuit Current
A
= -1
25
V
Closed Loop Output Resistance (Note 6)
DC, A = +1
25
-
V
FN4019.5
April 23, 2007
3
HFA1109
Electrical Specifications
V
= ±5V, A = +2, R = 250Ω, R = 100Ω, Unless Otherwise Specified. (Continued)
SUPPLY
V
F
L
(NOTE 5)
TEST
PARAMETER
TEST CONDITIONS
20MHz
LEVEL
TEMP. (°C)
MIN
TYP
-55
-57
-68
-60
-65
MAX
UNITS
dBc
dBc
dBc
dBc
dB
Second Harmonic Distortion
B
B
B
B
B
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
(V
= 2V , Note 6)
P-P
OUT
60MHz
20MHz
60MHz
30MHz
Third Harmonic Distortion
(V = 2V , Note 6)
OUT
P-P
Reverse Isolation (S
)
12
TRANSIENT CHARACTERISTICS
Rise and Fall Times
V
V
= 0.5V
= 0.5V
B
B
B
B
B
B
B
B
25
Full
25
-
-
1.1
1.1
1.3
ns
ns
OUT
OUT
P-P
P-P
1.4
Overshoot
Slew Rate
-
0
2
5
-
%
Full
25
-
0.5
%
A
= -1, R = 200Ω
2300
2200
475
430
2600
2500
550
500
V/μs
V/μs
V/μs
V/μs
V
F
V
= 5V
OUT
P-P
Full
25
-
A
= +1, V
= 4V ,
P-P
-
V
OUT
+R = 550Ω (PDIP),
+R = 700Ω (SOIC)
S
Full
-
S
A
= +2, V
= 5V
P-P
B
B
B
B
B
B
25
Full
25
940
1100
950
19
-
-
-
-
-
-
V/μs
V/μs
ns
V
OUT
800
Settling Time
To 0.1%
-
-
-
-
(V
= +2V to 0V step, Note 6)
OUT
To 0.05%
To 0.01%
25
23
ns
25
36
ns
Overdrive Recovery Time
V
= ±2V
= 150Ω
= 75Ω
= 150Ω
= 75Ω
25
5
ns
IN
VIDEO CHARACTERISTICS
Differential Gain
(f = 3.58MHz)
R
R
R
R
B
B
B
B
B
B
B
B
25
Full
25
-
-
-
-
-
-
-
-
0.02
0.03
0.04
0.05
0.02
0.02
0.05
0.06
0.06
0.09
0.09
0.12
0.06
0.06
0.09
0.13
%
%
%
%
°
L
L
L
L
Full
25
Differential Phase
(f = 3.58MHz)
Full
25
°
°
Full
°
POWER SUPPLY CHARACTERISTICS
Power Supply Range
C
A
A
25
25
±4.5
-
±5.5
10
V
Power Supply Current (Note 6)
-
-
9.6
10
mA
mA
Full
11
NOTES:
5. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
6. See Typical Performance Curves for more information.
FN4019.5
April 23, 2007
4
HFA1109
ground plane is a must! Attention should be given to
Application Information
decoupling the power supplies. A large value (10μF)
tantalum in parallel with a small value (0.1μF) chip capacitor
works well in most cases.
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
amplifier’s unique relationship between bandwidth and R .
F
All current feedback amplifiers require a feedback resistor,
Care must also be taken to minimize the capacitance to ground
seen by the amplifier’s inverting input (-IN). The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. Thus it is recommended that
the ground plane be removed under traces connected to -IN,
and connections to -IN should be kept as short as possible.
even for unity gain applications, and R , in conjunction with
F
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to R . The HFA1109 design is
F
optimized for a 250Ω R at a gain of +2. Decreasing R
F
F
decreases stability, resulting in excessive peaking and
overshoot (Note: Capacitive feedback will cause the same
problems due to the feedback impedance decrease at higher
frequencies). At higher gains the amplifier is more stable, so
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
R can be decreased in a trade-off of stability for bandwidth.
F
TABLE 1. OPTIMUM FEEDBACK RESISTOR
avoided by placing a resistor (R ) in series with the output
GAIN (A
)
R
(W)
F
BANDWIDTH (MHz)
S
CL
prior to the capacitance.
R
and C form a low pass network at the output, thus
L
-1
200
400
350
S
limiting system bandwidth well below the amplifier
bandwidth. By decreasing R as C increases, the
+1
250 (+R = 550W) PDIP
S
250 (+R = 700W) SOIC
S
S
L
maximum bandwidth is obtained without sacrificing stability.
In spite of this, bandwidth still decreases as the load
capacitance increases.
+2
+5
250
100
90
450
160
70
+10
Evaluation Board
Table 1 lists recommended R values, and the expected
F
bandwidth, for various closed loop gains. For a gain of +1, a
The performance of the HFA1105 may be evaluated using
the HFA11XX Evaluation Board and a SOIC to DIP adaptor
like the Aries Electronics Part Number 14-350000-10. The
layout and schematic of the board are shown in Figure 1.
resistor (+R ) in series with +IN is required to reduce gain
S
peaking and increase stability
PC Board Layout
Please contact your local sales office for information. When
evaluating this amplifier, the two 510Ω gain setting resistors
on the evaluation board should be changed to 250Ω..
The frequency response of this amplifier depends greatly on
the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
510Ω
510Ω
50Ω
V
H
V
H
1
2
3
4
8
7
6
5
0.1µF
50Ω
10µF
+5V
1
IN
+IN
OUT
OUT
V-
V+
V
L
V
L
10µF
0.1µF
GND
GND
GND
-5V
FIGURE 1B. TOP LAYOUT
FIGURE 1. EVALUATION BOARD SCHEMATICS AND LAYOUT
FIGURE 1C. BOTTOM LAYOUT
FIGURE 1A. BOARD SCHEMATIC
FN4019.5
April 23, 2007
5
HFA1109
Typical Performance Curves V
= ±5V, T = +25°C, R = Value From the Optimum Feedback Resistor Table, R = 100Ω,
SUPPLY
A
F
L
Unless Otherwise Specified
200
2.0
1.5
1.0
0.5
0
A
= +2
A = +2
V
V
150
100
50
0
-50
-100
-0.5
-1.0
-150
-200
-1.5
-2.0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 2. SMALL SIGNAL PULSE RESPONSE
FIGURE 3. LARGE SIGNAL PULSE RESPONSE
200
150
100
50
2.0
1.5
1.0
0.5
0
A
= +1
A
= +1
V
V
0
-50
-100
-0.5
-1.0
-150
-200
-1.5
-2.0
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 4. SMALL SIGNAL PULSE RESPONSE
FIGURE 5. LARGE SIGNAL PULSE RESPONSE
FN4019.5
April 23, 2007
6
HFA1109
Typical Performance Curves V
= ±5V, T = +25°C, R = Value From the Optimum Feedback Resistor Table, R = 100Ω,
SUPPLY
A
F
L
Unless Otherwise Specified (Continued)
2.0
200
A
V
= -1
A
= -1
V
1.5
1.0
0.5
0
150
100
50
0
-0.5
-1.0
-50
-100
-1.5
-2.0
-150
-200
TIME (5ns/DIV)
TIME (5ns/DIV)
FIGURE 7. LARGE SIGNAL PULSE RESPONSE
FIGURE 6. SMALL SIGNAL PULSE RESPONSE
2.0
1.5
1.0
0.5
0
200
150
100
50
A
= +5
A
= +5
V
V
A
= +10
A
= +10
V
V
A
= +10
V
0
A
= +10
V
-50
-100
-0.5
-1.0
A
= +5
V
A
= +5
V
-150
-200
-1.5
-2.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 8. SMALL SIGNAL PULSE RESPONSE
FIGURE 9. LARGE SIGNAL PULSE RESPONSE
V
= 200mV
V
= 200mV
P-P
OUT
P-P
OUT
3
3
0
A
= +2
V
GAIN
A
= +1
GAIN
V
0
A
= +10
-3
-3
V
A
= +5
V
A
= +1
V
A
= +2
PHASE
V
PHASE
A
V
= -1
0
0
90
90
A
= +1
A
= +10
V
V
180
270
180
270
A
= +5
V
A
= -1
V
0.3M
1M
10M
FREQUENCY (Hz)
100M
700M
0.3M
1M
10M
FREQUENCY (Hz)
100M
700M
FIGURE 10. FREQUENCY RESPONSE
FIGURE 11. FREQUENCY RESPONSE
FN4019.5
April 23, 2007
7
HFA1109
Typical Performance Curves V
= ±5V, T = +25°C, R = Value From the Optimum Feedback Resistor Table, R = 100Ω,
SUPPLY
A
F
L
Unless Otherwise Specified (Continued)
116
106
V
= 200mV
P-P
OUT
0.1
0
A
= +1
V
96
86
76
66
56
46
36
26
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
0
45
90
A
= +2
V
135
180
0.01M
0.1M 0.3M 1M 3M 6M10M30M 100M 500M
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
100M
500M
FIGURE 13. OPEN LOOP TRANSIMPEDANCE
FIGURE 12. GAIN FLATNESS
-30
-40
-50
-20
A
= +1
A
= +1
V
V
100MHz
-30
-40
100MHz
-50
50MHz
50MHz
-60
-70
-80
-90
-60
20MHz
10MHz
-70
20MHz
10MHz
-80
-90
-100
-6
-3
0
3
6
9
12
-6
-3
0
3
6
9
12
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 14. 2nd HARMONIC DISTORTION vs P
FIGURE 15. 3rd HARMONIC DISTORTION vs P
OUT
OUT
-30
-40
-50
-30
-40
-50
A
= +2
A
= +2
V
V
100MHz
100MHz
50MHz
10MHz
50MHz
-60
-70
-80
-90
-60
-70
-80
-90
20MHz
20MHz
10MHz
-6
-3
0
3
6
9
12
15
-6
-3
0
3
6
9
12
15
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 16. 2nd HARMONIC DISTORTION vs P
FIGURE 17. 3rd HARMONIC DISTORTION vs P
OUT
OUT
FN4019.5
April 23, 2007
8
HFA1109
Typical Performance Curves V
= ±5V, T = +25°C, R = Value From the Optimum Feedback Resistor Table, R = 100Ω,
SUPPLY
A
F
L
Unless Otherwise Specified (Continued)
-20
-20
V
= 2V
P-P
V
= 2V
P-P
OUT
OUT
-30
-40
-50
-60
-70
-80
-30
-40
-50
A
= +1
= -1
V
A
V
A
= +2
V
A
= +2, -1
V
-60
A
= +1
V
-70
-80
A
= +1
V
0M 10M 20M 30M 40M 50M 60M 70M 80M 90M 100M
FREQUENCY (Hz)
0M 10M 20M 30M 40M 50M 60M 70M 80M 90M 100M
FREQUENCY (Hz)
FIGURE 18. 2nd HARMONIC DISTORTION vs FREQUENCY
FIGURE 19. 3rd HARMONIC DISTORTION vs FREQUENCY
3.6
A
= +2
V
+V
(R = 100Ω)
L
3.4
3.2
3.0
OUT
|-V
| (R = 100Ω)
L
OUT
1k
100
10
+V
(R = 50Ω)
L
OUT
+V
OUT
(R = 50Ω)
L
2.8
2.6
1
|-V
| (R = 100Ω)
L
OUT
0.1
0.01
2.4
2.2
|-V
| (R = 50Ω)
OUT
L
2.0
1.8
1.6
0.3
1M
10M
100M
1000M
-75
-50
-25
0
25
50
75
100
125
FREQUENCY (Hz)
TEMPERATURE (°C)
FIGURE 21. OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 20. CLOSED LOOP OUTPUT RESISTANCE
14.0
17
16
15
14
13
12
11
10
9
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.50
9.00
8.50
V
= ±8V
S
V
= ±5V
S
8
7
V
= ±4V
S
6
5
4
-75
4
4.5
5
5.5
6
6.5
7
7.5
8
-50
-25
0
25
50
75
100
125
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
FIGURE 22. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 23. SUPPLY CURRENT vs TEMPERATURE
FN4019.5
April 23, 2007
9
HFA1109
Typical Performance Curves V
= ±5V, T = +25°C, R = Value From the Optimum Feedback Resistor Table, R = 100Ω,
SUPPLY
A
F
L
Unless Otherwise Specified (Continued)
100
100
A
= +2
V
V
= 2V
OUT
0.1
I
NI-
0.05
0.025
0
I
NI+
10
10
-0.025
-0.05
E
NI
I
NI+
-0.1
1
100k
1
0.1k
1k
10k
10
20
30
40 50
60
70 80
90 100
FREQUENCY (Hz)
TIME (ns)
FIGURE 24. INPUT NOISE CHARACTERISTICS
FIGURE 25. SETTLING RESPONSE
FN4019.5
April 23, 2007
10
HFA1109
GLASSIVATION:
Die Characteristics
Type: Nitride
Thickness: 4kÅ ±0.5kÅ
DIE DIMENSIONS:
59milsx80milsx19mils
TRANSISTOR COUNT:
1500μmx2020μmx483μm
130
METALLIZATION:
SUBSTRATE POTENTIAL (POWERED UP):
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.4kÅ
Floating (Recommend Connection to V-)
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
Metallization Mask Layout
HFA1109
NC
NC
NC
NC
V+
-IN
OUT
NC
NC
+IN
V-
NC
NC
FN4019.5
April 23, 2007
11
HFA1109
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4019.5
April 23, 2007
12
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