HFA1110883 [INTERSIL]
750MHz, Low Distortion 750MHz, Low Distortion; 750MHz的低失真750MHz的，低失真
| 型号： | HFA1110883 |
| 厂家： | 
Intersil |
| 描述： | 750MHz, Low Distortion 750MHz, Low Distortion |
| 文件： | 总13页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFA1110/883
750MHz, Low Distortion
Unity Gain, Closed Loop Buffer
November 1998
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HFA1110/883 is a unity gain, closed loop buffer which
achieves a high degree of gain accuracy, wide bandwidth,
and low distortion. Manufactured on Intersil’s proprietary
complementary bipolar UHF-1 process, the HFA1110/883
also offers very fast slew rates, and high output current.
• Fixed Gain of +1
• Wide -3dB Bandwidth . . . . . . . . . . . . . . . 750MHz (Typ)
• Very Fast Slew Rate. . . . . . . . . . . . . . . . 1250V/µs (Typ)
• Low Differential Gain and Phase . . . 0.04%/0.025 Deg.
• Low Distortion (HD3, 30MHz) . . . . . . . . . . -80dBc (Typ)
• Excellent Gain Flatness (to 100MHz) . . . ±0.03dB (Typ)
• Excellent Gain Accuracy. . . . . . . . . . . . . .0.99V/V (Typ)
• High Output Current . . . . . . . . . . . . . . . . . . 60mA (Typ)
Component and composite video systems will also benefit
from this buffer’s performance, as indicated by the excellent
gain flatness, and 0.04%/0.025 Degree Differential
Gain/Phase specifications (R = 75Ω).
L
For buffer applications desiring a standard op amp pinout, or
selectable gain (-1, +1, +2), please refer to the HFA1112/883
and HFA1113/883 (featuring programmable output clamps)
datasheets.
Ordering Information
Applications
• Video Switching and Routing
• Pulse and Video Amplifiers
• Wideband Amplifiers
• RF/IF Signal Processing
• Flash A/D Driver
TEMP.
o
PART NUMBER RANGE ( C)
PACKAGE
PKG. NO.
HFA1110MJ/883
-55 to 125
8 Ld CERDIP
F8.3A
• Medical Imaging Systems
Pinout
HFA1110/883
(CERDIP)
TOP VIEW
V+
OPT V+
NC
1
2
3
4
8
7
6
5
OUT
NC
+
-
OPT V-
V-
IN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 511083-883
File Number 3620.2
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
HFA1110/883
Absolute Maximum Ratings
Thermal Information
o
o
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Voltage at Input Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to V-
Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . .±55mA
ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V
Thermal Resistance (Typical, Note 1)
CERDIP Package . . . . . . . . . . . . . . . .
Maximum Package Power Dissipation at 75 C
θ
( C/W)
JA
θ
( C/W)
JC
120
35
o
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.83W
Package Power Dissipation Derating Factor above 75 C
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.3mW/ C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Storage Temperature Range. . . . . . . . . . . . . . . -65 C ≤ T ≤ 150 C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . 300 C
o
o
Operating Conditions
o
Supply Voltage (±V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5V
S
o
o
A
R
≥ 50Ω
L
o
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . -55 C ≤ T ≤ 125 C
A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: V
SUPPLY
= ±5V, R
SOURCE
= 0Ω, R = 100Ω, V
= 0V, Unless Otherwise Specified.
L
OUT
GROUP A
SUBGROUPS
TEMPERATURE
o
PARAMETER
SYMBOL
CONDITIONS
( C)
MIN
-25
-40
39
MAX
UNITS
mV
Output Offset Voltage
V
V
= 0V
CM
1
25
25
40
-
OS
2, 3
1
125, -55
25
mV
Power Supply
Rejection Ratio
PSRRP
PSRRN
∆V
SUP
= ±1.25V
dB
V+ = 6.25V, V- = -5V
V+ = 3.75V, V- = -5V
2, 3
125, -55
35
-
dB
∆V
SUP
= ±1.25V
1
25
39
35
-
-
dB
dB
V+ = 5V, V- = -6.25V
V+ = 5V, V- = -3.75V
2, 3
125, -55
Input Current
I
V
= 0V
CM
1
25
-40
-65
-
40
65
40
50
µA
µA
BSP
2, 3
1
125, -55
25
Input Current Common
Mode Rejection
CMS
∆V
CM
V+ = 3V, V- = -7V
V+ = 7V, V- = -3V
= ±2V
µA/V
µA/V
IBP
2, 3
125, -55
-
Input Resistance
R
Note 2
1
2, 3
1
25
125, -55
25
25
-
kΩ
kΩ
V/V
V/V
V
IN
20
-
Gain (V
OUT
= 2V
P-P
)
A
V
= -1V to +1V
IN
0.980
1.020
VP1
2, 3
1
125, -55
25
0.975
1.025
Output Voltage Swing
Output Voltage Swing
V
R
R
= 100Ω, V = +3.3V
IN
3
2.5
-
-
-
OP100
ON100
L
L
2, 3
1
125, -55
25
V
V
= 100Ω, V = -3.3V
IN
-3
V
2, 3
1
125, -55
25
-
-2.5
-
V
V
R
R
= 50Ω, V = +2.7V
IN
2.5
2.5
1.5
-
V
OP50
L
L
= 50Ω, V = +3.3V
IN
2
125
-
V
3
-55
-
V
V
R
R
= 50Ω, V = -2.7V
IN
1
25
-2.5
-2.5
-1.5
V
ON50
L
L
= 50Ω, V = -3.3V
IN
2
125
-
V
3
-55
-
V
Spec Number 511083-883
2
HFA1110/883
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: V
SUPPLY
= ±5V, R
SOURCE
= 0Ω, R = 100Ω, V
= 0V, Unless Otherwise Specified.
L
OUT
GROUP A
SUBGROUPS
TEMPERATURE
o
PARAMETER
Output Current
SYMBOL
CONDITIONS
( C)
MIN
50
30
-
MAX
-
UNITS
mA
+I
Note 3
1, 2
3
25, 125
-55
OUT
-
mA
-I
Note 3
1, 2
3
25, 125
-55
-50
-30
26
33
-14
-
mA
OUT
-
mA
Quiescent Power
Supply Current
I
R
R
= 100Ω
= 100Ω
1
25
14
-
mA
CC
L
L
2, 3
1
125, -55
25
mA
I
-26
-33
mA
EE
2, 3
125, -55
mA
NOTES:
2. Guaranteed from Input Common Mode Rejection Test, by: R = 1/CMS
IN
.
IBP
3. Guaranteed from V
OUT
Test with R = 50Ω, by: I
= V /50Ω.
OUT
L
OUT
TABLE 2. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
SUBGROUPS (SEE TABLE 1)
Interim Electrical Parameters (Pre Burn-In)
Final Electrical Test Parameters
Group A Test Requirements
1
1 (Note 7), 2, 3
1, 2, 3
Groups C and D Endpoints
1
NOTE:
4. PDA applies to Subgroup 1 only.
Spec Number 511083-883
3
HFA1110/883
Test Circuit (Applies to Table 1)
V+
+
10
0.1
I
CC
V
Y
V
=
OS
100
0.1
+
-
V
470pF
Y
510
x100
510
1
1
K1
1K
8
4
V
IN
V
DUT
5
OUT
0.1
2
100
100
100K (0.01%)
V
Z
I
=
BIAS
100K
K3
-
+
V
Z
0.1
10
0.1
HA-5177
+
NOTE:
I
EE
All Resistors = ±1% (Ω)
All Capacitors = ±10% (µF)
Unless Otherwise Noted
V-
Chip Components Recommended
Spec Number 511083-883
4
HFA1110/883
Test Waveforms
SIMPLIFIED TEST CIRCUIT FOR LARGE AND SMALL SIGNAL PULSE RESPONSE (Applies to Table 3)
A
= +1 TEST CIRCUIT
V+
V
1
V
8
4
OUT
V
IN
2
50Ω
R
50Ω
S
5
50Ω
V-
NOTE: V = ±5V
S
S
L
R
R
= 50Ω
= 100Ω For Small and Large Signals
V
V
OUT
OUT
+2.5V
+2.5V
250mV
250mV
90%
90%
90%
90%
+SR
-SR
t
, +OS
t , -OS
F
R
10%
10%
10%
10%
-2.5V
-2.5V
-250mV
-250mV
FIGURE 1. LARGE SIGNAL WAVEFORM
FIGURE 2. SMALL SIGNAL WAVEFORM
Burn-In Circuit
HFA1110MJ/883 CERAMIC DIP
D4
V+
D2
8
7
6
5
1
2
3
4
R2
C2
D3
C1
V-
R1
D1
NOTES:
R1 = 1kΩ, ±5% (Per Socket)
R2 = 100Ω, ±5% (Per Socket)
C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum
D1 = D2 = 1N4002 or Equivalent (Per Board)
D3 = D4 = 1N4002 or Equivalent (Per Socket)
V+ = +5.5V ± 0.5V
V- = -5.5V ± 0.5V
Spec Number 511083-883
5
HFA1110/883
Typical Design Information
The information contained in this section has been developed through characterization by Intersil and is for use as application and design information only. No
guarantee is implied.
o
Typical Performance Curves V
= ±5V, T = 25 C, R = 100Ω. Unless Otherwise Specified.
SUPPLY
A
L
120
80
1.2
0.8
0.4
0
40
0
-40
-80
-120
-0.4
-0.8
-1.2
5ns/DIV
5ns/DIV
FIGURE 3. SMALL SIGNAL PULSE RESPONSE
FIGURE 4. LARGE SIGNAL PULSE RESPONSE
2
1
0
GAIN
OUT
R
= 1kΩ
V
= 200mV
L
+6
+3
0
P-P
= 1V
V
OUT
P-P
R
= 100Ω
L
0
-1
-2
-3
-4
-45
R
= 50Ω
L
-90
-3
-6
-135
-180
0
PHASE
OUT
-5
-6
-225
-270
-90
-180
V
= 200mV
P-P
-7
-8
-270
-360
R
= 1kΩ
L
0
200M
400M
600M
800M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. FORWARD GAIN AND PHASE
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
+2
890
870
850
830
810
790
770
750
+1
0
-1
-2
-3
-4
-5
-6
-7
-8
V
= 200mV
OUT
P-P
= 2.5V
P-P
V
OUT
V
= 4V
P-P
OUT
730
710
-50 -30 -10 +10 +30 +50 +70 +90 +110 +130
1M
10M
FREQUENCY (Hz)
100M
1G
o
TEMPERATURE ( C)
FIGURE7. FREQUENCYRESPONSEFORVARIOUSOUTPUT
VOLTAGES
FIGURE 8. -3dB BANDWIDTH vs TEMPERATURE
Spec Number 511083-883
6
HFA1110/883
o
Typical Performance Curves V
= ±5V, T = 25 C, R = 100Ω. Unless Otherwise Specified. (Continued)
SUPPLY
A
L
+0.25
+0.20
+0.15
+0.10
+0.05
0
+2.0
+1.5
+1.0
+0.5
0
-0.5
-1.0
-1.5
-2.0
-0.05
-0.10
0
15
30
45
60
75
90 105 120 135 150
1M
10M
100M 200M
FREQUENCY (Hz)
FREQUENCY (MHz)
FIGURE 9. GAIN FLATNESS
FIGURE 10. DEVIATION FROM LINEAR PHASE
50
40
30
20
10
0
+135
+90
-20
-30
-40
-50
-60
PHASE
GAIN
+45
0
V
= 1V
P-P
OUT
0
200M
400M
600M
800M
1G
0
50
100
150
200
250
300
350
400
FREQUENCY (Hz)
FREQUENCY (MHz)
FIGURE 11. REVERSE GAIN AND PHASE
FIGURE 12. 2 TONE, 3RD ORDER INTERMODULATION
INTERCEPT
-30
-40
-50
-60
-70
-80
-90
-100
-30
-40
100 MHz
100 MHz
-50
50 MHz
30 MHz
-60
-70
50 MHz
-80
-90
30 MHz
-100
-5
-3
-1
1
3
5
7
9
11
13
-5
-3
-1
1
3
5
7
9
11
13
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 13. 2ND HARMONIC DISTORTION vs P
FIGURE 14. 3RD HARMONIC DISTORTION vs P
OUT
OUT
Spec Number 511083-883
7
HFA1110/883
o
Typical Performance Curves V
= ±5V, T = 25 C, R = 100Ω. Unless Otherwise Specified. (Continued)
SUPPLY
A
L
21
18
15
12
9
V
= 2.0V
P-P
O
0.8
0.4
0.2
0
-0.2
-0.4
V
= 1.0V
P-P
O
V
= 0.5V
P-P
-0.8
O
6
3
0
-5
0
5
10
15 20 25
TIME (ns)
30
35 40
45
200
300
400
500
600
700
800
900
1000
INPUT RISE TIME (ps)
FIGURE 15. SETTLING RESPONSE (V
OUT
= 1V)
FIGURE 16. OVERSHOOT vs INPUT RISETIME
+0.04
22
21
20
19
18
17
16
15
14
13
12
11
10
9
R
= 200Ω
L
+0.02
0
R
= 100Ω
= 1kΩ
L
R
L
-0.02
-0.04
8
7
6
5
5
6
7
8
9
10
-3.0
-2.0
-1.0
0
+1.0
+2.0
+3.0
INPUT VOLTAGE (V)
TOTAL SUPPLY VOLTAGE (V+ - V-, V)
FIGURE 17. INTEGRAL LINEARITY ERROR
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
25
24
23
22
21
20
19
18
17
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
-60
-40
-20
0
+20 +40 +60 +80 +100 +120
o
-60
-40 -20
0
+20 +40 +60 +80 +100 +120
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 19. SUPPLY CURRENT vs TEMPERATURE
FIGURE 20. BIAS CURRENT vs TEMPERATURE
Spec Number 511083-883
8
HFA1110/883
o
Typical Performance Curves V
= ±5V, T = 25 C, R = 100Ω. Unless Otherwise Specified. (Continued)
SUPPLY
A
L
10
9.8
9.6
9.4
9.2
9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3
+V
OUT
(R = 100Ω)
+V (R = 50Ω)
OUT L
L
8.8
8.6
8.4
8.2
8
|-V
OUT
|(R = 50Ω)
|-V |(R = 100Ω)
OUT L
L
2.9
2.8
7.8
-60
-40
-20
0
+20 +40 +60 +80 +100 +120
o
-60 -40 -20
0
+20 +40 +60 +80 +100 +120
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 21. OFFSET VOLTAGE vs TEMPERATURE
FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE
100
80
60
40
20
0
200
160
120
80
INI
40
ENI
0
100K
100
1K
10K
FREQUENCY (Hz)
FIGURE 23. INPUT NOISE vs FREQUENCY
Spec Number 511083-883
9
HFA1110/883
PC Board Layout
Evaluation Board
The frequency response of this buffer depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resis-
tors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
The performance of this buffer may be evaluated using the
HFA1110 Evaluation Board. The layout and schematic of the
board are shown in Figure 25.
To order evaluation boards, please contact your local sales
office.
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
TOP LAYOUT
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section. Removing the GND plane under the output
trace helps minimize this capacitance.
1
An example of a good high frequency layout is the Evalua-
tion Board shown in Figure 25.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the buffer’s phase
margin resulting in frequency response peaking and possi-
ble oscillations. In most cases, the oscillation can be avoided
BOTTOM LAYOUT
by placing a resistor (R ) in series with the output prior to
S
the capacitance.
Figure 24 details starting points for the selection of this resis-
tor. The points on the curve indicate the R and C combina-
S
L
tions for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.
R
and C form a low pass network at the output, thus limit-
L
S
ing system bandwidth well below the buffer bandwidth of
750MHz. By decreasing R as C increases (as illustrated in
S
L
Figure 24), the maximum bandwidth is obtained without sac-
rificing stability. Even so, bandwidth does decrease as you
move to the right along the curve.
50
45
40
35
30
25
20
15
10
5
50Ω
+5V
0.1µF
1
2
3
4
8
7
6
5
OUT
-5V
R
S
10µF
50Ω
HFA1110
IN
10µF
0.1µF
0
0
40
80 120 160 200 240 280 320 360 400
LOAD CAPACITANCE (pF)
FIGURE 25. EVALUATION BOARD SCHEMATIC AND LAYOUT
FIGURE 24. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
Spec Number 511083-883
10
HFA1110/883
TABLE 3. TYPICAL PERFORMANCE SPECIFICATIONS
Device Characterized at: V
= ±5V, R = 100Ω, Unless Otherwise Specified
SUPPLY
L
TEMPERATURE
o
PARAMETER
CONDITIONS
( C)
TYPICAL
8
UNITS
Output Offset Voltage (See Note)
Average Offset Voltage Drift
Power Supply Rejection Ratio
Input Current (See Note)
Input Resistance
V
= 0V
25
Full
25
mV
CM
Versus Temperature
o
10
µV/ C
∆V
= ±1.25V
45
dB
µA
SUP
V
= 0V
25
10
CM
∆V
= ±2V
25
50
kΩ
CM
Input Capacitance
25
2.2
pF
Input Noise Voltage (See Note)
Input Noise Current (See Note)
Input Common Mode Range
Gain
f = 100kHz
f = 100kHz
25
14
nV/√Hz
pA/√Hz
V
25
51
Full
25
±2.8
0.99
0.003
±3.3
±3.0
±60
±50
0.3
V
= 2V
P-P
V/V
%
OUT
DC Non-Linearity (See Note)
Output Voltage (See Note)
±2V Full Scale
25
R
R
R
R
= 100Ω
= 100Ω
= 50Ω
25
V
L
L
L
L
Full
25 to 125
-55 to 0
25
V
Output Current (See Note)
mA
= 50Ω
mA
DC Closed Loop Output Resistance
Quiescent Supply Current (See Note)
-3dB Bandwidth (See Note)
Slew Rate
W
R
= Open
Full
25
24
mA
L
V
V
V
= 200mV
750
1250
150
±0.01
±0.02
±0.03
±0.3
-72
MHz
V/µs
MHz
dB
OUT
OUT
OUT
P-P
= 5V
= 4V
25
P-P
Full Power Bandwidth (See Note)
Gain Flatness (See Note)
25
P-P
To 30MHz
To 50MHz
25
25
dB
To 100MHz
To 100MHz
25
dB
Linear Phase Deviation (See Note)
2nd Harmonic Distortion (See Note)
25
Degrees
dBc
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dBm
dBm
dBm
dB
30MHz, V
50MHz, V
= 2V
= 2V
25
OUT
P-P
25
-57
OUT
P-P
100MHz, V
= 2V
P-P
25
-42
OUT
3rd Harmonic Distortion (See Note)
30MHz, V
50MHz, V
= 2V
25
-80
OUT
P-P
P-P
= 2V
25
-74
OUT
100MHz, V
100MHz
300MHz
100MHz
150MHz
200MHz
40MHz
= 2V
P-P
25
-51
OUT
3rd Order Intercept (See Note)
1dB Gain Compression
25
30
25
10
25
14
25
10
25
7
Reverse Isolation (S ) (See Note)
12
25
-70
100MHz
600MHz
25
-60
dB
25
-27
dB
Rise and Fall Time
Overshoot (See Note)
Differential Gain
V
V
= 0.5V
P-P
25
600
9
ps
OUT
OUT
= 0.5V , Input t /t = 600ps
25
%
P-P
R
F
R
R
= 75Ω, NTSC
25
0.04
0.025
%
L
L
Differential Phase
= 75Ω, NTSC
25
Degrees
NOTE: See Typical Performance Curves for more information.
Spec Number 511083-883
11
HFA1110/883
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
63 x 44 x 19 mils ± 1 mils
Type: Nitride
1600 x 1130 x 483µm ± 25.4µm
Thickness: 4kÅ ±0.5kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
5
2
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.4kÅ
Type: Metal 2: AICu(2%)
2.0 x 10 A/cm at 47.5mA
TRANSISTOR COUNT:
Thickness: Metal 2: 16kÅ ±0.8kÅ
52
SUBSTRATE POTENTIAL (Powered Up):
Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1110/883
NC
IN
V-
NC
NC
NC
NC
V+
OUT
Spec Number 511083-883
12
HFA1110/883
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
(c)
METAL
INCHES MILLIMETERS
MIN
E
b1
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.405
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
10.29
7.87
NOTES
M
M
A
b
-
-
-B-
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
SECTION A-A
S
S
S
D
bbb
C A - B
D
b1
b2
b3
c
3
-
BASE
PLANE
Q
4
A
-C-
SEATING
PLANE
2
L
α
c1
D
3
S1
b2
eA
A A
e
5
E
0.220
5.59
5
b
C A - B
eA/2
c
e
0.100 BSC
2.54 BSC
-
M
S
S
M
S
S
D
ccc
D
aaa
C A - B
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
NOTES:
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
Q
0.015
0.005
0.38
0.13
6
S1
7
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
2, 3
8
N
8
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
Spec Number 511083-
13
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