HA-5137A [INTERSIL]

63MHz, Ultra-Low Noise Precision Operational Amplifier; 63MHz ,超低噪声精密运算放大器
HA-5137A
型号: HA-5137A
厂家: Intersil    Intersil
描述:

63MHz, Ultra-Low Noise Precision Operational Amplifier
63MHz ,超低噪声精密运算放大器

运算放大器
文件: 总9页 (文件大小:537K)
中文:  中文翻译
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HA-5137A  
TM  
Data Sheet  
April 2000  
File Number 2908.5  
63MHz, Ultra-Low Noise Precision  
Operational Amplifier  
Features  
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/µs  
The HA-5137 operational amplifier features an unparalleled  
combination of precision DC and wideband high speed  
characteristics. Utilizing the Intersil Dielectric Isolation  
technology and advanced processing techniques, this  
unique design unites low noise (3nV Hz ) precision  
instrumentation performance with high speed (20V/µs)  
wideband capability.  
• Wide Gain Bandwidth (A 5) . . . . . . . . . . . . . . . 63MHz  
V
• Low Noise. . . . . . . . . . . . . . . . . . . . . . . 3nV/ Hz at 1kHz  
• Low V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µV  
OS  
• High CMRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126dB  
• High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800V/mV  
This amplifier’s impressive list of features include low V  
OS  
Applications  
(10µV), wide gain bandwidth (63MHz), high open loop gain  
(1800V/mV), and high CMRR (126dB). Additionally, this  
flexible device operates over a wide supply range (±5V to  
±20V) while consuming only 140mW of power.  
• High Speed Signal Conditioners  
• Wide Bandwidth Instrumentation Amplifiers  
• Low Level Transducer Amplifiers  
• Fast, Low Level Voltage Comparators  
• Highest Quality Audio Preamplifiers  
• Pulse/RF Amplifiers  
Using the HA-5137 allows designers to minimize errors while  
maximizing speed and bandwidth in applications requiring  
gains greater than five.  
This device is ideally suited for low level transducer signal  
amplifier circuits. Other applications which can utilize the  
HA-5137’s qualities include instrumentation amplifiers, pulse  
or RF amplifiers, audio preamplifiers, and signal conditioning  
circuits.  
• For Further Design Ideas See Application Note AN553  
Ordering Information  
TEMP.  
PKG.  
NO.  
This device can easily be used as a design enhancement by  
directly replacing the 725, OP25, OP06, OP07, OP27 and  
OP37 where gains are greater than five. For the military  
grade product, refer to the HA-5137/883 data sheet.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
HA7-5137A-5 0 to 75  
8 Ld CERDIP  
F8.3A  
Pinout  
HA-5137A  
(CERDIP)  
TOP VIEW  
BAL  
-IN  
+IN  
V-  
1
2
3
4
8
7
6
5
BAL  
V+  
-
+
OUT  
NC  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000  
1
HA-5137A  
o
Absolute Maximum Ratings T = 25 C  
Thermal Information  
A
o
o
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 44V  
Differential Input Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . 0.7V  
Output Current . . . . . . . . . . . . . . . . . . . . Full Short Circuit Protection  
Thermal Resistance (Typical, Note 2)  
CERDIP Package. . . . . . . . . . . . . . . . .  
θ
( C/W)  
θ
( C/W)  
JA  
JC  
115  
28  
o
Maximum Junction Temperature (Hermetic Package) . . . . . . . 175 C  
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C  
o
o
Operating Conditions  
o
Temperature Range  
HA-5137A-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C  
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTES:  
1. For differential input voltages greater than 0.7V, the input current must be limited to 25mA to protect the back-to-back input diodes.  
2. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Electrical Specifications  
V
= ±15V, C 50pF, R 100Ω  
SUPPLY L S  
TEMP.  
o
PARAMETER  
INPUT CHARACTERISTICS  
Offset Voltage  
TEST CONDITIONS  
( C)  
MIN  
TYP  
MAX  
UNITS  
25  
Full  
Full  
25  
-
10  
30  
25  
60  
0.6  
40  
60  
35  
50  
-
µV  
µV  
-
o
Average Offset Voltage Drift  
Bias Current  
-
0.2  
10  
µV/ C  
-
nA  
nA  
nA  
nA  
V
Full  
25  
-
20  
Offset Current  
-
7
Full  
Full  
25  
-
15  
Common Mode Range  
±10.3  
±11.5  
6
Differential Input Resistance (Note 3)  
Input Noise Voltage (Note 4)  
1.5  
-
MΩ  
0.1Hz to 10Hz  
f = 10Hz  
25  
-
-
-
-
-
-
-
0.08  
3.5  
3.1  
3.0  
1.7  
1.0  
0.4  
0.18  
8.0  
4.5  
3.8  
4.0  
2.3  
0.6  
µV  
P-P  
Input Noise Voltage Density  
(Note 5)  
25  
nV/ Hz  
nV/ Hz  
f = 100Hz  
f = 1000Hz  
f = 10Hz  
25  
25  
nV/ Hz  
pA/ Hz  
Input Noise Current Density  
(Note 5)  
25  
f = 100Hz  
f = 1000Hz  
25  
pA/ Hz  
pA/ Hz  
25  
TRANSFER CHARACTERISTICS  
Large Signal Voltage Gain  
R
V
= 2k,  
25  
Full  
Full  
25  
1000  
600  
114  
5
1800  
1200  
126  
-
-
-
-
-
-
-
V/mV  
V/mV  
dB  
L
= ±10V  
OUT  
V = ±10V  
CM  
Common Mode Rejection Ratio  
Minimum Stable Gain  
V/V  
Gain-Bandwidth-Product  
f = 10kHz  
f = 1MHz  
25  
60  
80  
MHz  
MHz  
25  
-
63  
OUTPUT CHARACTERISTICS  
Output Voltage Swing  
R
R
= 600Ω  
= 2kΩ  
25  
Full  
25  
±10.0  
±11.7  
220  
-
±11.5  
±13.8  
320  
70  
-
-
-
-
-
V
V
L
L
Full Power Bandwidth (Note 6)  
Output Resistance  
Output Current  
kHz  
Open Loop  
25  
25  
16.5  
25  
mA  
TRANSIENT RESPONSE (Note 7)  
Rise Time  
25  
25  
25  
25  
-
14  
-
-
100  
ns  
V/µs  
µs  
Slew Rate  
V
= ±3V  
20  
1.0  
20  
-
-
OUT  
Note 8  
Settling Time  
Overshoot  
-
40  
%
POWER SUPPLY CHARACTERISTICS  
Supply Current  
25  
-
-
3.5  
-
-
mA  
mA  
Full  
4.0  
2
HA-5137A  
Electrical Specifications  
V
= ±15V, C 50pF, R 100(Continued)  
SUPPLY  
L
S
TEMP.  
o
PARAMETER  
Power Supply Rejection Ratio  
NOTES:  
TEST CONDITIONS  
= ±4V to ±18V  
( C)  
MIN  
TYP  
MAX  
UNITS  
V
Full  
-
2
4
µV/V  
S
3. This parameter value is based upon design calculations.  
4. Refer to Typical Performance section of the data sheet.  
5. The limits for this parameter are based on lab characterization, and reflect lot-to-lot variation.  
Slew Rate  
6. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = ---------------------------- .  
2πV  
PEAK  
7. Refer to Test Circuits section of the data sheet.  
8. Settling time is specified to 0.1% of final value for a 10V output step and A = -5.  
V
Test Circuits and Waveforms  
IN  
+
OUT  
-
1.6k  
50pF  
400Ω  
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT  
IN  
IN  
OUT  
OUT  
Vertical Scale: Input = 1V/Div.  
Output = 5V/Div.  
Vertical Scale: Input = 20mV/Div.  
Output = 100mV/Div.  
Horizontal Scale: 1µs/Div.  
Horizontal Scale: 100ns/Div.  
LARGE SIGNAL RESPONSE  
SMALL SIGNAL RESPONSE  
+15V  
2N4416  
5kΩ  
+15V  
TO  
1000Ω  
400Ω  
OSCILLOSCOPE  
2kΩ  
NOTES:  
+
OUT  
9. A = -5.  
V
-
IN  
10. Feedback and summing resistors should be  
0.1% matched.  
50pF  
-15V  
11. Clipping diodes are optional. HP5082-2810  
recommended.  
2kΩ  
FIGURE 2. SETTLING TIME TEST CIRCUIT  
3
Schematic Diagram  
V+  
7
1
8
BALANCE  
R
Q
R
1
25  
R
16  
R
R
R
R
Q
R
17  
C
15  
2
20  
21  
7
P32  
Q
P37  
Q
P38  
Q
Q
P35  
P43  
P44  
D
1
Q
Q
Q
P55  
N45  
D8  
C
C
5
Q
N19  
Q
N46  
4
Q
N13  
Q
P56  
Q
Q
N15  
N14  
Q
N47  
R
1A  
R
2A  
C
Q
N29  
1
Q
N20  
Q
Q
P17  
P16  
Q
D33  
R
7
R
3
Q
Q
R
N52  
N51  
Q
D9  
C
Q
6
R
R
P26  
12  
14  
Q
Q
N4  
N3  
Q
Q
D54  
D53  
Q
Q
Q
P26  
6
R
P36  
P27  
9
18  
OUT-  
PUT  
Q
N2  
Q
P36A  
R
Q
24  
D41  
Q
R
N18  
13  
Q
N12  
Q
Q
Q
N1A  
N1  
N2A  
Q
Q
D34  
Q
Q
P40  
N7  
Q
D22  
Q
R
P30  
Q
19  
D23  
Q
Q
Z58  
P21  
Q
R
N42  
4
Q
D59  
N6  
C
3
Q
N42A  
Q
Q
N5  
Q
N48  
N25  
Q
Q
N24  
N49  
Q
Q
N50  
N57  
Q
N39  
C
2
Q
D60  
R
R
R
8
R
10  
R
22  
R
5
6
23  
Q
N10  
Q
N11  
3
2
-INPUT  
4
+INPUT  
V-  
SUBSTRATE  
HA-5137A  
Application Information  
R
P
10K  
1
2
3
4
8
7
6
5
V+  
-
+
NOTE: Tested Offset Adjustment Range is |V  
+ 1mV| minimum referred to output. Typical range is ±4mV with R = 10k.  
P
OS  
FIGURE 3. SUGGESTED OFFSET VOLTAGE ADJUSTMENT  
C
S
R
1
+
-
R
2
R
1
-
+
R
3
R
R
3
2
C
3
NOTE: Low resistances are preferred for low noise applications as a 1kresistor has 4nV/Hz of thermal noise. Total resistances of greater than  
10kon either input can reduce stability. In most high resistance applications, a few picofarads of capacitance across the feedback resistor will  
improve stability.  
FIGURE 4. SUGGESTED STABILITY CIRCUITS  
o
Typical Performance Curves Unless Otherwise Specified: T = 25 C, V  
= ±15V  
SUPPLY  
A
12  
6
5
o
30  
V
= ±15V, T = 25 C  
S
A
20  
10  
10  
0
8
6
4
3
-10  
-20  
-30  
-40  
-50  
-60  
NOISE VOLTAGE  
NOISE CURRENT  
4
2
1
0
2
0
-60  
-40 -20  
0
20  
40  
60  
o
80  
100 120  
1
10  
100  
1K  
10K  
100K  
1M  
TEMPERATURE ( C)  
FREQUENCY (Hz)  
FIGURE 5. OFFSET VOLTAGE DRIFT vs TEMPERATURE  
FIGURE 6. NOISE CHARACTERISTICS  
5
HA-5137A  
o
Typical Performance Curves Unless Otherwise Specified: T = 25 C, V  
= ±15V (Continued)  
SUPPLY  
A
0.14  
140  
120  
100  
80  
o
T
= 25 C  
A
0.12  
0.1  
0.08  
0.06  
60  
40  
0.04  
0.02  
0
20  
0
10  
100  
1K  
10K  
100K  
1M  
10M  
4
6
8
10  
12  
14  
16  
18  
20  
FREQUENCY (Hz)  
SUPPLY VOLTAGE (±V)  
FIGURE 8. CMRR vs FREQUENCY  
FIGURE 7. NOISE vs SUPPLY VOLTAGE  
2.60  
2.58  
2.56  
2.54  
2.52  
2.50  
2.48  
2.46  
2.44  
2.42  
2.40  
1.10  
1.00  
0.90  
0.80  
0.70  
0.60  
0.50  
BANDWIDTH  
-SLEW RATE  
+SLEW RATE  
4
6
8
10  
12  
14  
16  
18  
20  
5
10  
15  
20  
SUPPLY VOLTAGE (±V)  
SUPPLY VOLTAGE (±V)  
FIGURE 9. SUPPLY CURRENT vs SUPPLY VOLTAGE  
FIGURE 10. BANDWIDTH AND SLEW RATE vs SUPPLY  
VOLTAGE  
140  
120  
40  
30  
GAIN  
20  
10  
0
100  
-PSRR  
80  
0
PHASE  
60  
40  
+PSRR  
-10  
-20  
90  
20  
0
180  
10  
100  
1K  
10K  
100K  
1M  
10M  
100  
1K  
10K  
100K  
1M  
10M  
100M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 11. PSRR vs FREQUENCY  
FIGURE 12. CLOSED LOOP GAIN AND PHASE vs FREQUENCY  
6
HA-5137A  
o
Typical Performance Curves Unless Otherwise Specified: T = 25 C, V  
= ±15V (Continued)  
SUPPLY  
A
17  
16  
15  
14  
13  
12  
11  
10  
9
1.05  
1.04  
1.03  
1.02  
1.01  
o
o
T
= 25 C  
R
= 2K, C = 50pF, T = 25 C  
A
L
L
A
A
VOL  
V
OUT  
1.0  
0.99  
8
0.98  
0.97  
0.96  
7
6
5
4
0.95  
0
2
4
6
8
10  
-60  
-40 -20  
0
20  
40  
60  
o
80 100 120  
LOAD RESISTANCE (k)  
TEMPERATURE ( C)  
FIGURE 13. A  
VOL  
AND V  
OUT  
vs LOAD RESISTANCE  
FIGURE 14. NORMALIZED SLEW RATE vs TEMPERATURE  
28  
o
= 2K, C = 50pF, T = 25 C  
R
V
= 0V, V = ±15V  
S
2.82  
2.80  
L
L
A
O
24  
20  
16  
12  
8
2.78  
2.76  
2.74  
2.72  
2.70  
2.68  
4
0
0.4  
0.8  
1.2  
1.6  
2
-55  
25  
TEMPERATURE ( C)  
125  
o
FREQUENCY (MHz)  
FIGURE 15. SUPPLY CURRENT vs TEMPERATURE  
FIGURE 16. V  
MAX (UNDISTORTED SINEWAVE OUTPUT)  
OUT  
vs FREQUENCY  
140  
120  
100  
80  
60  
40  
20  
0
GAIN  
0
PHASE  
-45  
-90  
-135  
-180  
10M 100M  
A
= 25,000V/V  
CL  
Horizontal Scale = 1s/Div.  
Vertical Scale = 0.002µV/Div., E = 0.08µV  
10  
100  
1K  
10K  
100K  
1M  
FREQUENCY (Hz)  
RTI  
N
P-P  
FIGURE 17. OPEN LOOP GAIN AND PHASE vs FREQUENCY  
FIGURE 18. PEAK-TO-PEAK NOISE VOLTAGE (0.1Hz TO 10Hz)  
7
HA-5137A  
Die Characteristics  
DIE DIMENSIONS:  
PASSIVATION:  
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)  
104 mils x 65 mils x 19 mils  
3
4
2
2650µm x 1650µm x 483µm  
Silox Thickness: 12kÅ ±2kÅ  
Nitride Thickness: 3.5kÅ ±1.5kÅ  
METALLIZATION:  
TRANSISTOR COUNT:  
Type: Al, 1% Cu  
Thickness: 16kÅ ±2kÅ  
63  
SUBSTRATE POTENTIAL (POWERED UP):  
PROCESS:  
V-  
Bipolar Dielectric Isolation  
Metallization Mask Layout  
HA-5137A  
BAL  
BAL  
-IN  
V+  
+IN  
OUT  
NC  
V-  
8
HA-5137A  
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)  
c1 LEAD FINISH  
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)  
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE  
-D-  
E
-A-  
INCHES  
MIN  
MILLIMETERS  
BASE  
(c)  
METAL  
SYMBOL  
MAX  
0.200  
0.026  
0.023  
0.065  
0.045  
0.018  
0.015  
0.405  
0.310  
MIN  
-
MAX  
5.08  
0.66  
0.58  
1.65  
1.14  
0.46  
0.38  
10.29  
7.87  
NOTES  
b1  
A
b
-
-
M
M
(b)  
0.014  
0.014  
0.045  
0.023  
0.008  
0.008  
-
0.36  
0.36  
1.14  
0.58  
0.20  
0.20  
-
2
-B-  
b1  
b2  
b3  
c
3
SECTION A-A  
bbb  
C A - B  
D
D
S
S
S
-
4
BASE  
PLANE  
Q
A
2
-C-  
SEATING  
PLANE  
c1  
D
3
L
α
5
S1  
b2  
eA  
A A  
e
E
0.220  
5.59  
5
b
C A - B  
eA/2  
aaa M C A - B S  
c
e
0.100 BSC  
2.54 BSC  
-
eA  
eA/2  
L
0.300 BSC  
0.150 BSC  
7.62 BSC  
3.81 BSC  
-
ccc  
D
D
S
M
S
S
-
NOTES:  
0.125  
0.200  
0.060  
-
3.18  
5.08  
1.52  
-
-
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark.  
Q
0.015  
0.005  
0.38  
0.13  
6
S1  
7
o
o
o
o
90  
105  
90  
105  
-
α
2. The maximum limits of lead dimensions b and c or M shall be  
measured at the centroid of the finished lead surfaces, when  
solder dip or tin plate lead finish is applied.  
aaa  
bbb  
ccc  
M
-
-
-
-
0.015  
0.030  
0.010  
0.0015  
-
-
-
-
0.38  
0.76  
0.25  
0.038  
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness.  
-
2, 3  
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a  
partial lead paddle. For this configuration dimension b3 replaces  
dimension b2.  
N
8
8
Rev. 0 4/94  
5. This dimension allows for off-center lid, meniscus, and glass  
overrun.  
6. Dimension Q shall be measured from the seating plane to the  
base plane.  
7. Measure dimension S1 at all four corners.  
8. N is the maximum number of terminal positions.  
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
10. Controlling dimension: INCH  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Mercure Center  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
Intersil (Taiwan) Ltd.  
7F-6, No. 101 Fu Hsing North Road  
Taipei, Taiwan  
Republic of China  
TEL: (886) 2 2716 9310  
FAX: (886) 2 2715 3029  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (321) 724-7000  
FAX: (321) 724-7240  
9

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