首页 |元器件品牌

CA3054_05 [INTERSIL]

Dual Independent Differential Amp for Low Power Applications from DC to 120MHz; 双独立差分放大器，适用于低功耗应用，从DC到120MHz的
CA3054_05
型号： CA3054_05
厂家： Intersil    Intersil
描述：

Dual Independent Differential Amp for Low Power Applications from DC to 120MHz
双独立差分放大器，适用于低功耗应用，从DC到120MHz的

放大器
文件： 总8页 (文件大小：206K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
CA3054  
Data Sheet  
September 22, 2005  
FN388.6  
Dual Independent Differential Amp for  
Low Power Applications from DC to  
120MHz  
Features  
• Two Differential Amplifiers on a Common Substrate  
• Independently Accessible Inputs and Outputs  
The CA3054 consists of two independent differential  
amplifiers with associated constant current transistors on a  
common monolithic substrate. The six NPN transistors which  
comprise the amplifiers are general purpose devices which  
• Maximum Input Offset Voltage . . . . . . . . . . . . . . . . . ±5mV  
• Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to 85°C  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
exhibit low 1/f noise and a value of f in excess of 300MHz.  
T
These feature make the CA3054 useful from DC to 120MHz.  
Bias and load resistors have been omitted to provide  
maximum application flexibility.  
Applications  
• Dual Sense Amplifiers  
• Dual Schmitt Triggers  
The monolithic construction of the CA3054 provides close  
electrical and thermal matching of the amplifiers. This  
feature makes these devices particularly useful in dual  
channel applications where matched performance of the two  
channels is required.  
• Multifunction Combinations  
- RF/Mixer/Oscillator; Converter/IF  
• IF Amplifiers (Differential and/or Cascode)  
• Product Detectors  
Ordering Information  
• Doubly Balanced Modulators and Demodulators  
• Balanced Quadrature Detectors  
• Cascade Limiters  
PART NUMBER  
(BRAND)  
TEMP.  
RANGE (°C)  
PKG.  
DWG. #  
PACKAGE  
14 Ld SOIC  
CA3054M96  
(3054)  
0 to 85  
0 to 85  
0 to 85  
M14.15  
M14.15  
Tape and Reel  
• Synchronous Detectors  
CA3054MZ  
(CA3054MZ)  
14 Ld SOIC  
(Pb-free)  
• Pairs of Balanced Mixers  
• Synthesizer Mixers  
CA3054MZ96  
(CA3054MZ)  
14 Ld SOIC Tape M14.15  
and Reel (Pb-free)  
• Balanced (Push-Pull) Cascode Amplifiers  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free  
material sets; molding compounds/die attach materials and 100%  
matte tin plate termination finish, which are RoHS compliant and  
compatible with both SnPb and Pb-free soldering operations. Intersil  
Pb-free products are MSL classified at Pb-free peak reflow  
temperatures that meet or exceed the Pb-free requirements of  
IPC/JEDEC J STD-020.  
Pinout  
CA3054 (SOIC)  
TOP VIEW  
1
2
3
4
5
6
7
14  
Q
1
Q
3
2
13  
12  
Q
11  
Q
4
SUBSTRATE  
10 NC  
9
8
Q
Q
6
5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.  
Copyright Harri Corporation 1998. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
CA3054  
Absolute Maximum Ratings T = 25°C  
Thermal Information  
A
Collector-to-Emitter Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . 15V  
Thermal Resistance (Typical, Note 2)  
θJA (°C/W)  
CEO  
. . . . . . . . . . . . . . . . . . . . . . . . 20V  
Collector-to-Base Voltage, V  
CBO  
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
140  
Collector-to-Substrate Voltage, V  
(Note 1). . . . . . . . . . . . . . 20V  
CIO  
. . . . . . . . . . . . . . . . . . . . . . . . . . 5V  
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . . 175°C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C  
Maximum Storage Temperature Range. . . . . . . . . . -65°C to 150°C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C  
(Lead Tips Only)  
Emitter-to-Base Voltage, V  
EBO  
Collector Current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA  
C
Operating Conditions  
Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW  
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTES:  
1. The collector of each transistor of the CA3054 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage  
which is more negative than any collector voltage in order to maintain isolation between transistors and provide for normal transistor action. The  
substrate should be maintained at signal (AC) ground by means of a suitable grounding capacitor, to avoid undesired coupling between transistors.  
2. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Maximum Voltage Ratings  
Maximum  
Current Ratings  
The following chart gives the range of voltages which can be applied to the terminals listed vertically with respect to the termi-  
nals listed horizontally. For example, the voltage range of the vertical Terminal 2 with respect to Terminal 4 is +15V to -5V.  
(NOTE 4)  
(NOTE 4)  
TERM  
TERM  
NO.  
I
I
OUT  
IN  
mA mA  
NO.  
13  
14  
1
13  
14  
1
2
3
4
6
7
8
9
11  
12  
5
0, -20 Note 3 +5, -5 Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3  
Note 3 Note 3 Note 3 +20, 0 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 +20, 0  
+20, 0 Note 3 +20, 0 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 +20, 0  
Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3  
+1, -5 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3  
Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3  
0, -20 Note 3 +5, -5 Note 3 +15, -5 Note 3  
Note 3 Note 3 Note 3 Note 3 +20, 0  
13  
14  
1
5
50  
50  
5
0.1  
0.1  
0.1  
0.1  
0.1  
50  
2
2
3
3
5
4
4
0.1  
5
6
6
0.1  
0.1  
0.1  
0.1  
0.1  
50  
7
7
50  
50  
5
8
+20, 0 Note 3 Note 3 +20, 0  
8
9
Note 3 +15, -5 Note 3  
9
11  
12  
5
-1, -5 Note 3  
11  
12  
5
Note 3  
0.1  
Ref.  
Sub-  
strate  
NOTES:  
3. Voltages are not normally applied between these terminals. Voltages appearing between these terminals will be safe  
if the specified limits between all other terminals are not exceeded.  
4. Terminal No. 10 of CA3054 is not used.  
Electrical Specifications T = 25°C  
A
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DC CHARACTERISTICS For Each Differential Amplifier  
Input Offset Voltage (Figure 8)  
V
V
V
V
V
= 3V, I  
= 3V, I  
= 3V, I  
= 3V, I  
= I  
= I  
= I  
= I  
= 2mA  
= 2mA  
= 2mA  
= 2mA  
-
-
-
-
0.45  
0.3  
10  
5
2
mV  
µA  
µA  
-
IO  
CB  
CB  
CB  
CB  
E(Q3)  
E(Q3)  
E(Q3)  
E(Q3)  
E(Q4)  
E(Q4)  
E(Q4)  
E(Q4)  
Input Offset Current (Figure 9)  
I
IO  
Input Bias Current (Figure 5)  
I
24  
-
I
Quiescent Operating Current Ratio  
(Figure 5)  
0.98 to  
1.02  
I
I
C(Q1)  
C(Q5)  
-----------------  
-----------------  
or  
I
I
C(Q2)  
C(Q6)  
Temperature Coefficient Magnitude of  
Input Offset Voltage (Figure 7)  
V
= 3V, I  
= I  
= 2mA  
-
1.1  
-
µV/°C  
CB  
E(Q3)  
E(Q4)  
∆V  
IO  
-----------------  
∆T  
2
CA3054  
Electrical Specifications T = 25°C (Continued)  
A
PARAMETER  
FOR EACH TRANSISTOR  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DC Forward Base-to-Emitter Voltage  
(Figure 8)  
V
V
= 3V  
I
I
I
I
= 50µA  
= 1mA  
= 3mA  
= 10mA  
-
-
-
-
-
0.630  
0.715  
0.750  
0.800  
-1.9  
0.700  
0.800  
0.850  
0.900  
-
V
V
BE  
CB  
C
C
C
C
V
V
Temperature Coefficient of Base-to-Emitter  
Voltage (Figure 6)  
V
V
= 3V, I = 1mA  
µV/°C  
CB  
CB  
C
∆V  
BE  
---------------  
∆T  
Collector Cutoff Current (Figure 4)  
Collector-to-Emitter Breakdown Voltage  
Collector-to-Base Breakdown Voltage  
I
= 10V, I = 0  
-
0.002  
24  
100  
nA  
V
CBO  
E
V
V
I
I
I
= 1mA, I = 0  
15  
20  
20  
-
-
-
(BR)CEO  
(BR)CBO  
C
C
C
B
= 10µA, I = 0  
60  
V
E
Collector-to-Substrate Breakdown  
Voltage  
V
= 10µA, I = 0  
CI  
60  
V
(BR)CIO  
Emitter-to-Base Breakdown Voltage  
V
I
= 10µA, I = 0  
5
7
-
V
(BR)EBO  
E
C
DYNAMIC CHARACTERISTICS  
Common Mode Rejection Ratio for each  
Amplifier (Figures 1, 10)  
CMRR  
AGC  
A
V
V
= 12V, V = -6V,  
EE  
= -3.3V, f = 1kHz  
-
-
-
-
-
100  
75  
-
-
-
-
-
dB  
dB  
dB  
dB  
dB  
CC  
X
AGC Range, One Stage (Figures 2, 11)  
V
V
= 12V, V = -6V,  
EE  
= -3.3V, f = 1kHz  
CC  
X
Voltage Gain, Single Stage Double-Ended  
Output (Figures 2, 11)  
V
V
= 12V, V = -6V,  
EE  
= -3.3V, f = 1kHz  
32  
CC  
X
AGC Range, Two Stage (Figures 3, 12)  
AGC  
A
V
V
= 12V, V = -6V,  
EE  
= -3.3V, f = 1kHz  
105  
60  
CC  
X
Voltage Gain, Two Stage Double-Ended Output  
(Figures 3, 12)  
V
V
= 12V, V = -6V,  
EE  
= -3.3V, f = 1kHz  
CC  
X
Low Frequency, Small SignalEquivalent Circuit Char-  
acteristics (For Single Transistor)  
Forward Current Transfer Ratio (Figure 13)  
h
f = 1kHz, V  
f = 1kHz, V  
f = 1kHz, V  
= 3V, I = 1mA  
-
-
-
110  
3.5  
-
-
-
-
FE  
CE  
CE  
CE  
C
Short Circuit Input Impedance (Figure 13)  
h
= 3V, I = 1mA  
kΩ  
µS  
IE  
C
Open Circuit Output Impedance  
(Figure 13)  
h
= 3V, I = 1mA  
15.6  
OE  
C
Open Circuit Reverse Voltage Transfer  
Ratio (Figure 13)  
h
f = 1kHz, V  
= 3V, I = 1mA  
-
1.8 x  
10  
-
-
RE  
CE  
C
-4  
1/f Noise Figure for Single Transistor  
NF  
f = 1kHz, V = 3V  
CE  
-
-
3.25  
550  
-
-
dB  
Gain Bandwidth Product for Single  
Transistor (Figure 14)  
f
V
= 3V, I = 3mA  
C
MHz  
T
CE  
Admittance Characteristics; Differential  
Circuit Configuration (For Each Amplifier)  
Forward Transfer Admittance (Figure 15)  
Y
Y
Y
Y
V
= 3V, f = 1MHz  
-
-
-
-
-20 + j0  
-
-
-
-
mS  
mS  
mS  
mS  
21  
11  
22  
12  
CB  
Each Collector IC ≈ 1.25mA  
Input Admittance (Figure 16)  
V
= 3V, f = 1MHz  
0.22 +  
j0.1  
CB  
Each Collector IC ≈ 1.25mA  
Output Admittance (Figure 17)  
V
= 3V, f = 1MHz  
0.01 +  
j0  
CB  
Each Collector IC ≈ 1.25mA  
Reverse Transfer Admittance (Figure 18)  
V
= 3V, f = 1MHz  
-0.003  
+ j0  
CB  
Each Collector IC ≈ 1.25mA  
3
CA3054  
Electrical Specifications T = 25°C (Continued)  
A
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Admittance Characteristics; Cascode Circuit Con-  
figuration (For Each Amplifier)  
Forward Transfer Admittance (Figure 19)  
Y
Y
Y
V
= 3V, f = 1MHz  
CB  
-
-
68 - j0  
-
-
mS  
mS  
21  
11  
22  
Total Stage IC ≈ 2.5 mA  
Input Admittance (Figure 20)  
V
= 3V, f = 1MHz  
0.55 +  
j0  
CB  
Total Stage IC ≈ 2.5 mA  
Output Admittance (Figure 21)  
Reverse Transfer Admittance (Figure 22)  
Noise Figure  
V
= 3V, f = 1MHz  
-
-
-
0 +  
j0.02  
-
-
-
mS  
µS  
dB  
CB  
Total Stage IC ≈ 2.5 mA  
Y
V
= 3V, f = 1MHz  
CB  
0.004 -  
j0.005  
12  
Total Stage IC ≈ 2.5 mA  
NF  
f = 100MHz  
8
Test Circuits  
V
V
= +12V  
V
V
= +12V  
CC  
X
CC  
X
0.1µF  
0.1µF  
1kΩ  
1kΩ  
V
= 0.3V  
V
= 10mV  
IN RMS  
IN  
RMS  
11  
11  
7
8
7
10µF  
10µF  
9
9
6
V
V
OUT  
OUT  
ICUT  
12  
ICUT  
12  
1kΩ  
6
SIGNAL  
SOURCE  
SIGNAL  
SOURCE  
8
0.5kΩ  
1kΩ  
0.5kΩ  
1kΩ  
0.5kΩ  
1kΩ  
V
= +12V  
V
= +12V  
CC  
CC  
0.1µF  
0.1µF  
V
= -6V  
EE  
V
= -6V  
EE  
FIGURE 1. COMMON MODE REJECTION RATIO TEST SETUP  
FIGURE 2. SINGLE STAGE VOLTAGE GAIN TEST SETUP  
V
= +12V  
CC  
1µF  
1kΩ  
1kΩ  
1kΩ  
0.1µF  
0.1µF  
V
= 1mV  
IN  
RMS  
0.5kΩ  
2
10µF  
7
1
9
6
4
12  
1kΩ  
1kΩ  
V
SIGNAL  
SOURCE  
OUT  
ICUT  
8
3
V
= -6V  
EE  
11  
14  
13  
V
0.5kΩ  
X
1kΩ  
1kΩ  
1kΩ  
V
= +12V  
CC  
1µF  
FIGURE 3. TWO STAGE VOLTAGE GAIN TEST SETUP  
4
CA3054  
Typical Performance Curves  
100  
10.0  
1.0  
2
10  
V
T
= 3V  
CB  
= 25°C  
I
= 0  
A
E
10  
V
= 15V  
CB  
= 10V  
V
CB  
= 5V  
1
V
CB  
-1  
10  
-2  
-3  
-4  
10  
10  
10  
0
25  
50  
75  
100  
125  
0.1  
1.0  
10  
TEMPERATURE (°C) (NOTE)  
COLLECTOR CURRENT (mA)  
NOTE: For CA3054 use data from 0°C to 85°C only.  
FIGURE 4. COLLECTOR-TO-BASE CUTOFF CURRENT vs  
TEMPERATURE FOR EACH TRANSISTOR  
FIGURE 5. INPUT BIAS CURRENT vs COLLECTOR CURRENT  
FOR EACH TRANSISTOR  
5
V
= 3V  
CB  
V
= 3V  
CB  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
4
3
I
= 10mA  
E
2
0.75  
0.50  
0.25  
0
I
= 1mA  
E
I
= 3mA  
E
I
= 1mA  
E
I
= 0.5mA  
E
I
= 0.1mA  
E
-75  
-50  
-25  
0
25  
50  
75  
100  
125  
-75  
-50 -25  
0
25  
50  
75  
100  
125  
TEMPERATURE (°C) (NOTE)  
TEMPERATURE (°C) (NOTE)  
NOTE: For CA3054 use data from 0°C to 85°C only.  
NOTE: For CA3054 use data from 0°C to 85°C only.  
FIGURE 6. BASE-TO-EMITTER VOLTAGE FOR EACH  
TRANSISTOR vs TEMPERATURE  
FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE FOR  
DIFFERENTIAL PAIRS  
0.8  
10  
4
V
T
= 3V  
V
T
= 3V  
CB  
= 25°C  
CB  
= 25°C  
A
A
0.7  
0.6  
0.5  
0.4  
3
1.0  
0.1  
V
BE  
2
1
0
V
= |V  
BE1  
- V  
0.1  
|
BE2  
IO  
0.01  
0.01  
0.1  
1.0  
10  
0.01  
1.0  
10  
COLLECTOR CURRENT (mA)  
EMITTER CURRENT (mA)  
FIGURE 8. STATIC BASE-TO-EMITTER VOLTAGE AND INPUT  
OFFSET VOLTAGE FOR DIFFERENTIAL PAIRS vs  
EMITTER CURRENT  
FIGURE 9. INPUT OFFSET CURRENT FOR MATCHED  
DIFFERENTIAL PAIRS vs COLLECTOR CURRENT  
5
CA3054  
Typical Performance Curves (Continued)  
100  
V
V
= 12V  
= -6V  
V
V
= 12V  
= -6V  
CC  
EE  
CC  
EE  
110  
100  
90  
f = 1kHz  
75  
50  
25  
0
f = 1kHz  
SIGNAL INPUT = 10mV  
RMS  
-25  
-50  
80  
0
-1  
-2  
-3  
-4  
-5  
-6  
-7  
0
-1  
-2  
-3  
-4  
BIAS VOLTAGE ON TERMINAL 11 (V)  
BIAS VOLTAGE ON TERMINAL 11 (V)  
FIGURE 10. COMMON MODE REJECTION RATIO  
CHARACTERISTIC  
FIGURE 11. SINGLE STAGE VOLTAGE GAIN CHARACTERISTIC  
100  
100  
V
V
= 12V  
= -6V  
CC  
V
= 3V  
CB  
f = 1kHz  
EE  
h
h
h
h
= 110  
= 3.5kΩ  
= 1.88 x 10  
h
FE  
IE  
RE  
OE  
OE  
f = 1kHz  
SIGNAL INPUT = 1mV  
75  
50  
25  
0
T
= 25°C  
A
AT  
1mA  
-4  
RMS  
h
IE  
= 15.6µS  
10  
1.0  
0.1  
h
RE  
h
FE  
-25  
-50  
h
RE  
h
IE  
0.01  
0.1  
1.0  
10  
0
-1  
-2  
-3  
-4  
-5  
-6  
-7  
BIAS VOLTAGE ON TERMINALS 3 AND 11 (V)  
COLLECTOR CURRENT (mA)  
FIGURE 12. TWO STAGE VOLTAGE GAIN CHARACTERISTIC  
FIGURE 13. FORWARD CURRENT TRANSFER RATIO (h ),  
FE  
SHORT CIRCUIT INPUT IMPEDANCE (h ), OPEN  
IE  
CIRCUIT OUTPUT IMPEDANCE (h ), AND OPEN  
OE  
CIRCUIT REVERSE VOLTAGE TRANSFER RATIO  
(h ) vs COLLECTOR CURRENT FOR EACH  
RE  
TRANSISTOR  
30  
20  
V
T
= 3V  
CB  
= 25°C  
DIFFERENTIAL CONFIGURATION  
I
(EACH TRANSISTOR) ≅ 1.25mA  
A
C
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
V
T
= 3V  
CB  
= 25°C  
A
10  
0
b
g
21  
-10  
-20  
21  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14  
0.1  
1.0  
10  
100  
COLLECTOR CURRENT (mA)  
FREQUENCY (MHz)  
FIGURE 14. GAIN BANDWIDTH PRODUCT (f ) vs COLLECTOR  
T
FIGURE 15. FORWARD TRANSFER ADMITTANCE (Y ) vs  
21  
CURRENT  
FREQUENCY  
6
CA3054  
Typical Performance Curves (Continued)  
3
2
1
0
DIFFERENTIAL CONFIGURATION  
DIFFERENTIAL CONFIGURATION  
(EACH TRANSISTOR) ≅ 1.25mA  
I
(EACH TRANSISTOR) ≅ 1.25mA  
C
I
C
5
4
3
2
1
0
0.5  
0.4  
0.3  
0.2  
0.1  
0
V
= 3V  
CB  
= 25°C  
V
= 3V  
CB  
= 25°C  
T
A
T
A
b
11  
b
22  
g
11  
g
22  
0.1  
1
10  
FREQUENCY (MHz)  
100  
0.1  
1
10  
FREQUENCY (MHz)  
100  
FIGURE 16. INPUT ADMITTANCE (Y  
)
FIGURE 17. OUTPUT ADMITTANCE (Y ) vs FREQUENCY  
22  
11  
1000  
100  
10  
10  
DIFFERENTIAL CONFIGURATION  
= 3V  
V
80  
CB  
I
(EACH TRANSISTOR) ≅ 1.25mA  
C
1
0.1  
T
= 25°C  
g
A
60  
40  
20  
0
21  
CASCODE CONFIGURATION  
(STAGE) ≅ 2.5mA  
b
12  
I
C
V
= 3V  
CB  
= 25°C  
T
A
g
12  
0.01  
1
-g  
12  
0.1  
0.001  
0.0001  
-20  
-40  
b
21  
0.01  
0.1  
1
10  
FREQUENCY (MHz)  
100  
1000  
0.1  
1
10  
100 200  
FREQUENCY (MHz)  
FIGURE 18. REVERSE TRANSFER ADMITTANCE (Y ) vs  
12  
FIGURE 19. FORWARD TRANSFER ADMITTANCE (Y ) vs  
21  
FREQUENCY  
FREQUENCY  
CASCODE CONFIGURATION  
g
22  
I
(STAGE) ≅ 2.5mA  
C
6
5
4
3
2
1
0
0
V
= 3V  
CB  
= 25°C  
2
1
T
A
-2  
-4  
CASCODE CONFIGURATION  
(STAGE) ≅ 2.5mA  
I
C
V
= 3V  
CB  
= 25°C  
-6  
-8  
T
A
b
g
22  
-10  
-12  
11  
0
b
11  
0.1  
1
10  
FREQUENCY (MHz)  
100  
0.1  
1
10  
FREQUENCY (MHz)  
100 200  
FIGURE 20. INPUT ADMITTANCE (Y ) vs FREQUENCY  
11  
FIGURE 21. OUTPUT ADMITTANCE (Y ) vs FREQUENCY  
22  
7
CA3054  
Typical Performance Curves (Continued)  
100  
CASCODE CONFIGURATION  
(STAGE) ≅ 2.5mA  
I
C
V
= 3V  
10  
1
CB  
= 25°C  
T
A
g
12  
-b  
12  
0.1  
0.01  
0.001  
0.1  
1
10  
100 200  
FREQUENCY (MHz)  
FIGURE 22. REVERSE TRANSFER ADMITTANCE (Y ) vs FREQUENCY  
12  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
8

相关型号：

CA3058

 CA3058
RENESAS

CA3059

 ZERO VOLTAGE SWITCH
MOTOROLA

CA3059

 Zero-Voltage Switches for 50Hz-60Hz and 400Hz Thyristor Control Applications
INTERSIL

CA3059

 Zero Voltage Switch
ONSEMI

CA3059/D

 Zero Voltage Switches
MOTOROLA

CA3059E

 Analog IC
ETC

CA3059H

 IC,ZERO-CROSSING DETECTOR,BIPOLAR,DIE
RENESAS

CA3059_06

 Zero Voltage Switch
ONSEMI

CA3060

 110kHz, Operational Transconductance Amplifier Array
INTERSIL

CA3060

 110kHz, Operational Transconductance Amplifier Array
HARRIS

CA3060BD

 Operational Amplifier
ETC

CA3060BD/3

 Operational Amplifier
ETC
©2020 ICPDF网 联系我们和版权申明