CA3059 [INTERSIL]
Zero-Voltage Switches for 50Hz-60Hz and 400Hz Thyristor Control Applications; 零电压开关用于交流50Hz - 60Hz的和400Hz的晶闸管控制中的应用
| 型号： | CA3059 |
| 厂家： | 
Intersil |
| 描述： | Zero-Voltage Switches for 50Hz-60Hz and 400Hz Thyristor Control Applications |
| 文件： | 总12页 (文件大小：801K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
CA3059, CA3079
Zero-Voltage Switches for 50Hz-60Hz and
400Hz Thyristor Control Applications
Oct 1999
Features
Description
• Relay Control
• Valve Control
The CA3059 and CA3079 zero-voltage switches are mono-
lithic silicon integrated circuits designed to control a thyristor
in a variety of AC power switching applications for AC input
voltages of 24V, 120V, 208/230V, and 277V at 50Hz-60Hz
and 400Hz. Each of the zero-voltage switches incorporates
• Synchronous Switching of Flashing Lights
• On-Off Motor Switching
4 functional blocks (see the Functional Block Diagram) as
follows:
• Differential Comparator with Self-Contained Power
Supply for Industrial Applications
• Photosensitive Control
• Power One-Shot Control
• Heater Control
1. Limiter-Power Supply - Permits operation directly from an
AC line.
2. Differential On/Off Sensing Amplifier - Tests the condition
of external sensors or command signals. Hysteresis or
proportional-control capability may easily be implement-
ed in this section.
• Lamp Control
Type Features
CA3059 CA3079
• 24V, 120V, 208/230V, 277V at 50/60 . . .
or 400Hz Operation
X
X
3. Zero-Crossing Detector - Synchronizes the output pulses
of the circuit at the time when the AC cycle is at zero volt-
age point; thereby eliminating radio-frequency interfer-
ence (RFI) when used with resistive loads.
• Differential Input . . . . . . . . . . . . . . . . . .
X
1
X
2
• Low Balance Input Current (Max) - µA. . .
• Built-In Protection Circuit for . . . . . . . .
Opened or Shorted Sensor (Term 14)
X
X
4. Triac Gating Circuit - Provides high-current pulses to the
gate of the power controlling thyristor.
• Sensor Range (Rx) - kΩ. . . . . . . . . . . . . 2 - 100 2 - 50
In addition, the CA3059 provides the following important
auxiliary functions (see the Functional Block Diagram).
• DC Mode (Term 12) . . . . . . . . . . . . . . . .
• External Trigger (Term 6) . . . . . . . . . . .
• External Inhibit (Term 1) . . . . . . . . . . . .
X
X
1. A built-in protection circuitthatmay be actuatedto remove
drive from the triac if the sensor opens or shorts.
X
• DC Supply Volts (Max) . . . . . . . . . . . . .
14
10
2. Thyristor firing may be inhibited through the action of an
internal diode gate connected to Terminal 1.
o
• Operating Temperature Range ( C) . . . -55 to +125
3. High-power dc comparator operation is provided by over-
riding the action of the zero-crossing detector. This is ac-
complished by connecting Terminal 12 to Terminal 7.
Gate current to the thyristor is continuous when Terminal
13 is positive with respect to Terminal 9.
Ordering Information
PART NUMBER
TEMPERATURE
-55oC to +125oC
-55oC to +125oC
PACKAGE
CA3059
14 Lead Plastic DIP
14 Lead Plastic DIP
The CA3059 and CA3079 are supplied in 14 lead dual-in-
line plastic packages.
CA3079
Pinouts
CA3059 (PDIP)
CA3079 (PDIP)
TOP VIEW
TOP VIEW
DO NOT USE
1
14
1
2
3
4
5
6
7
14
INHIBIT
FAIL-SAFE
DO NOT USE
DC SUPPLY
DC SUPPLY 2
13 SENSE AMP IN
13 SENSE AMP IN
HIGH CURRENT
3
HIGH CURRENT
NEG. TRIGGER
DO NOT USE
12
11
12
11
ZCD OVERRIDE
R DRIVER (COM)
NEG. TRIGGER
TRIGGER OUT
TRIGGER OUT
R DRIVER (COM)
4
5
6
7
10 R DRIVER V+
10 R DRIVER V+
AC IN
AC IN
9
9
8
DO NOT USE
COMMON
SENSE AMP REF
COMMON
TRIGGER IN
COMMON
SENSE AMP REF
8
COMMON
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
FN490.5
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
3
CA3059, CA3079
Functional Block Diagram
12
IC
RS
RL
POWER
SUPPLY
5
LIMITER
CURRENT
BOOST
“0”
CROSSING
DET.
3
MT2
MT1
EXTERNAL
INHIBIT
IC
2
AC INPUT
VOLTAGE
TRIAC
GATING
CIRCUIT
1
4
G
PROTECTION
CIRCUIT
RP
RX
14
INHIBIT
13
8
ON/OFF
+
-
100µF
15V
SENSING
AMPL.
7
* NTC SENSOR
* NEGATIVE TEMPERATURE COEFFICIENT
9
10 11
6
IC
AC INPUT VOLTAGE (50/60 OR 400Hz)
V AC
INPUT SERIES RESISTOR (RS)
DISSIPATION RATING FOR RS
W
kΩ
24
120
2
0.5
2
10
20
25
208/230
277
4
5
NOTE: Circuitry within shaded areas, not included in CA3079
See chart
IC = Internal connection - DO NOT USE (Terminal restriction applies only to CA3079)
FOR DC MODE
OR 400Hz
RP
RSENSOR
CF
100µF
15V
12
IC
R1
5K
OPERATION
RS
COMMON
2
13
COMMON
5
AC
LINE
INPUT
D7
D13
D3
R2
27K
R7
10K
R3
12K
R4
10K
D2
D1
D6
10
9
D8
D9
Q6
Q2
Q3
R8
15
11
Q5
Q4
Q1
R5
9.6K
D4
D5
3
R10
40K
8
TO
COMMON
R6
15K
R9
25
FOR
INCREASED
GATE DRIVE
D12
Q7
Q8
D10
Q10
Q9
D11
D15
4
TO
THYRISTOR
GATE
FAIL-SAFE INPUT
14
7
1
6
IC
IC
IC
FOR
EXTERNAL
TRIGGER
TO
COMMON
INHIBIT
INPUT
All resistance values are in Ω
NOTE: Circuitry within shaded areas
not included in CA3079
IC = Internal connection - DO NOT USE (Terminal restriction applies only to
FIGURE 1. SCHEMATIC DIAGRAM OF CA3059 AND CA3079
4
Specifications CA3059, CA3079
Absolute Maximum Ratings TA = +25oC
Thermal Information
DC Supply Voltage (Between Terminals 2 & 7)
Thermal Resistance
θJA
CA3059. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
CA3079. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
DC Supply Voltage (Between Terminals 2 & 8)
CA3059. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
CA3079. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
Peak Supply Current (Terminals 5 & 7) . . . . . . . . . . . . . . . . . . .±50mA
Output Pulse Current (Terminal 4) . . . . . . . . . . . . . . . . . . . . .150mA
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100oC/W
Power Dissipation
Up to TA = +55oC CA3059, CA3079 . . . . . . . . . . . . . . . . . 950mW
Above TA = +55oC CA3059, CA3079 . .Derate Linearly 10mW/oC
Ambient Temperature
Operating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At distance 1/16” ± 1/32” (1.59 ± 0.79) from case
for 10 seconds max
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications TA = +25oC, For all Types, Unless Otherwise Specified. All voltages are measured with respect to
Terminal 7. For Operating at 120VRMS, 50-60Hz (AC Line Voltage) (Note 1)
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
DC SUPPLY VOLTAGE (Figure 2A, 2B, 2C)
Inhibit Mode
At 50/60Hz
At 400Hz
VS
RS = 8kΩ, IL = 0
6.1
6.5
6.8
6.4
6.4
6.7
6.3
105
7
-
V
V
RS = 10kΩ, IL = 0
RS = 5kΩ, IL = 0
-
-
At 50/60Hz
At 50/60Hz
At 400Hz
-
V
Pulse Mode
VS
RS = 8kΩ, IL = 0
6
-
7
-
V
RS = 10kΩ, IL = 0
RS = 5kΩ, IL = 0
V
At 50/60Hz
-
-
V
Gate Trigger Current (Figures 3, 4A)
IGT
Terminals 3 and 2 Connected,
-
-
mA
Terminal 4 VGT = 1V
PEAK OUTPUT CURRENT (PULSED) (Figures 4, 5)
With Internal Power Supply
IOM
Terminal 3 open, Gate Trigger
50
90
-
84
-
-
mA
mA
Figure 4a, 4b
Terminal 4 Voltage (VGT) = 0
Terminals 3 and 2 Connected, Gate
Trigger Voltage (VGT) = 0
124
With External Power Supply
Figure 5a, 5b, 5c
IOM
Terminal 3 open, V+ = 12V, VGT = 0
170
240
-
-
mA
mA
Terminal 4
Terminals 3 and 2 Connected,
V+ = 12V, VGT = 0
Inhibit Input Ratio (Figure 6)
V9/V2
Voltage Ratio of Terminals 9 to 2
0.465 0.485 0.520
-
TOTAL GATE PULSE DURATION (Note 2) (Figure 7A, 7B, 7C, 7D)
For Positive dv/dt
For Negative dv/dt
50-60Hz
400Hz
tP
CEXT = 0
70
-
100
12
140
µs
µs
µs
µs
CEXT = 0, REXT = ∞
CEXT = 0
-
140
-
50-60Hz
400Hz
tN
70
-
100
10
CEXT = 0, REXT = ∞
PULSE DURATION AFTER ZERO CROSSING (50-60Hz) (Figure 7A)
For Positive dv/dt
tP1
tN1
CEXT = 0, REXT = ∞
-
-
50
60
-
-
µs
µs
For Negative dv/dt
OUTPUT LEAKAGE CURRENT (Figure 8)
Inhibit Mode
I4
-
0.001
10
µA
INPUT BIAS CURRENT (Figure 9)
CA3059
II
-
-
-
220
220
1000
2000
-
nA
nA
V
CA3079
Common-mode Input Voltage Range
VCMR
Terminals 9 and 13 Connected
1.5 to
5
5
Specifications CA3059, CA3079
Electrical Specifications TA = +25oC, For all Types, Unless Otherwise Specified. All voltages are measured with respect to
Terminal 7. For Operating at 120VRMS, 50-60Hz (AC Line Voltage) (Note 1) (Continued)
PARAMETERS
SENSITIVITY (Note 3) (Figures 4(a), 11)
Pulse Mode
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
∆V13
Terminal 12 open
-
6
-
mV
NOTES:
1. The values given in the Electrical Characteristics Chart at 120V also apply for operation at input voltages of 208/230V, and 277V, except
for Pulse Duration. However, the series resistor (RS) must have the indicated value, shown in the chart in the Functional Block Diagram,
for the specified input voltage.
2. Pulse Duration in 50Hz applications is approximately 15% longer than shown in Figure 7(b).
3. Required voltage change at Terminal 13 to either turn OFF the triac when ON or turn ON the triac when OFF.
Maximum Voltage Ratings TA = +25oC
MAXIMUM
CURRENT
RATINGS
MAXIMUM VOLTAGE RATINGS TA = +25oC
NOTES
2, 3
14
TERM.
NO.
IIN
mA
IOUT
mA
NOTE 3
1
NOTE 1 NOTE 3
NOTE 3
12
2
3
4
5
6
7
8
9
10
11
13
1
Note 4 Note 4 Note 4 Note 4
15
0
10
-2
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
10
0.1
Note 3
2
0
0
2
0
0
0
0
0
0
Note 4
0
0
150
10
-15
-15
-14
-14 Note 5 Note 5 -14
-14 -14
-14
-14
-14
-14
3
4
0
-15
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
Note 4
2
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
0.1
50
150
10
-10
5
Note 4
7
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
Note 1
-7
6
14
0
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
Note 3
7
Note 4
14
0
Note 4
20
0
2.5
-2.5
14
0
6
-6
Note 4 Note 4
0.1
8
10
0
Note 4 Note 4 Note 4 Note 4 Note 4
2
9
Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
Note 4 Note 4 Note 4 Note 4 Note 4 Note4
Note 4 Note 4 Note 4 Note 4 Note4
10
11
12
Note 4 Note 4
50
50
Note 3
13
Note 4 Note 4 Note4
14
2
2
Note 3
This chart gives the range of voltages which can be applied to the terminals listed horizontally with respect to the terminals listed vertically.
For example, the voltage range of horizontal Terminal 6 to vertical Terminal 4 is 2V to -10V.
NOTES:
1. Resistance should be inserted between Terminal 5 and external supply or line voltage for limiting current into Terminal 5 to less than
50mA.
2. Resistance should be inserted between Terminal 14 and external supply for limiting current into Terminal 14 to less than 2mA.
3. For the CA3079 indicated terminal is internally connected and, therefore, should not be used.
4. Voltages are not normally applied between these terminals; however, voltages appearing between these terminals are safe, if the spec-
ified voltage limits between all other terminals are not exceeded.
5. For CA3079 (0V to -10V).
6
CA3059, CA3079
4.6K
13
PULSE
120VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS) = 10kΩ
NO EXTERNAL LOAD
0.3K
INHIBIT
2
7.00
6.75
6.50
INHIBIT MODE
4.6K
RL
RS
AC LINE
PULSE MODE
5
7
CA3059
CA3079
100µF
VS
11
6.25
6.00
5.75
IL
EXTERNAL
LOAD
CURRENT
8
4
9
10
-75
-50
-25
0
25
50
75 100 125
ALL RESISTANCE
VALUES ARE IN Ω
AMBIENT TEMPERATURE (oC)
FIGURE 2A. DC SUPPLY VOLTAGE TEST CIRCUIT FOR CA3059
AND CA3079
FIGURE 2B. DC SUPPLY VOLTAGE vs AMBIENT TEMPERA-
TURE FOR CA3059 AND CA3079
120VRMS, 50/60Hz OPERATION
T
120VRMS, 50/60Hz OPERATION
A = +25oC
TA = +25oC
130
6.5
6.0
5.5
5.0
4.5
4.0
3.5
RS = 5kΩ
(INHIBIT
MODE)
120
110
100
TERMINALS 2 AND 3
CONNECTED
90
80
70
60
50
40
RS = 10kΩ
(INHIBIT
MODE)
RS = 5kΩ
(PULSE
MODE)
RS = 10kΩ
(PULSE
MODE)
TERMINAL 3 OPEN
0
1
2
3
0
1
2
3
4
5
6
7
8
EXTERNAL LOAD CURRENT (mA)
GATE TRIGGER (V)
FIGURE 3. GATE TRIGGER CURRENT vs GATE TRIGGER
VOLTAGE FOR CA3059 AND CA3079
FIGURE 2C. DC SUPPLY VOLTAGE vs EXTERNAL LOAD
CURRENT FOR CA3059 AND CA3079
9
10 11
120VRMS, 50/60Hz OPERATION
GATE TRIGGER, VGT = 0 (V)
RS
10K
5
7
CA3059
CA3079
175
AC LINE
4
OSCILLOSCOPE
WITH
HIGH GAIN
INPUT
I
OM (4)
OR
GT(4)
150
TERMINALS 2 AND 3
CONNECTED
1Ω
±1%
I
125
100
75
TERMINAL 3 OPEN
13
8
2
3
50
-75 -50 -25
0
25
50
75 100 125
VGT
AMBIENT TEMPERATURE (oC)
6K
5K
100µF
FIGURE 4A. PEAK OUTPUT (PULSED) AND GATE TRIGGER
CURRENT WITH INTERNAL POWER SUPPLY
TEST CIRCUIT FOR CA3059 AND CA3079
FIGURE 4B. PEAK OUTPUT CURRENT (PULSED) vs AMBIENT
TEMPERATURE FOR CA3059 AND CA3079
7
CA3059, CA3079
V+
120VRMS, 50/60Hz OPERATION
GATE TRIGGER, VGT = 0 (V)
300
100µF
TERMINALS 2 AND 3
3
2
250
200
150
100
50
CONNECTED
5K
6K
RS
10K
TERMINAL 3 OPEN
13
5
7
120VRMS
60Hz
CA3059
4
11
OSCILLOSCOPE
WITH
HIGH GAIN
INPUT
IOM(4)
1Ω
±1%
10
9
8
0
5
VGT
0
5
10
15
20
EXTERNAL POWER SUPPLY, V+ (V)
ALL RESISTANCE VALUES ARE IN Ω
FIGURE 5B. PEAK OUTPUT CURRENT (PULSED) vs EXTER-
NAL POWER SUPPLY VOLTAGE FOR CA3059
FIGURE 5A. PEAK OUTPUT CURRENT (PULSED) WITH EXTER-
NAL POWER SUPPLY TEST CIRCUIT FOR CA3059
9
6
10 11
RS
10K
5
7
250
120VRMS
60Hz
CA3059
CA3079
4
EXTERNAL
SUPPLY
V+ = 13V
8
2
13
14
200
R1
R2
12V
10V
ALL RESISTANCE
VALUES IN Ω
100µF
150
100
50
13V
12V
8V
FIGURE 6(A). INPUT INHIBIT VOLTAGE RATIO TEST CIRCUIT
FOR CA3059 AND CA3079
10V
120VRMS, 50/60Hz OPERATION
0.60
8V
5V
0.55
0.50
0.45
0.40
0.35
0.30
5V
3V
3V
120VRMS, 50/60Hz OPERATION
GATE TRIGGER VOLTS (VGT) = 0
TERMINALS 2 AND 3 CONNECTED
TERMINAL 3 OPEN
0
-50
-20
10
40
70
100 130
-50 -25
0
25
50
75 100 125
AMBIENT TEMPERATURE (oC)
AMBIENT TEMPERATURE (oC)
FIGURE 6B. INPUT INHIBIT VOLTAGE RATIO vs AMBIENT TEM-
PERATURE FOR CA3059 AND CA3079
FIGURE 5C. PEAK OUTPUT CURRENT (PULSED) vs AMBIENT
TEMPERATURE FOR CA3059
8
CA3059, CA3079
GATE
PULSE
120VRMS, 50/60Hz OPERATION
TA = +25oC
AC LINE
300
+ dv/dt
- dv/dt
0V
tP (POSITIVE dv/dt)
tP1
tP
tN1
tN
200
9
RS
10K
10
11
tN (NEGATIVE dv/dt)
5
CA3059
CA3079
120VRMS
60Hz
C(EXT)
100
0
4
OSC.
WITH
HIGH
GAIN
INPUT
7
1M
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
8
2
12
13
6K
5K
EXTERNAL CAPACITANCE (µF)
REXT
100µF
NOTE: Circuitry within shaded area not included in CA3079.
All resistance values are in Ω
FIGURE 7B. TOTAL GATE PULSE DURATION vs EXTERNAL
CAPACITANCE FOR CA3059 AND CA3079
FIGURE 7A. GATE PULSE DURATION TEST CIRCUIT WITH
ASSOCIATED WAVEFORM FOR CA3059 AND
CA3079
40
700
120VRMS, 50/60Hz OPERATION
120VRMS, 50/60Hz OPERATION
TA = +25oC
TA = +25oC
600
30
500
tN1 (NEGATIVE dv/dt)
400
300
20
tP (POSITIVE dv/dt)
tP1 (POSITIVE dv/dt)
200
100
0
10
tN (NEGATIVE dv/dt)
0
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
10
100
EXTERNAL CAPACITANCE (µF)
EXTERNAL RESISTANCE (kΩ)
FIGURE 7C. PULSE DURATION AFTER ZERO CROSSING vs
EXTERNAL CAPACITANCE FOR CA3059 & CA3079
FIGURE 7D. TOTAL GATE PULSE DURATION vs EXTERNAL
RESISTANCE FOR CA3059
100
V+ = 6V
2
120VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS = 100kΩ
NO EXTERNAL LOAD
10
CA3059
CA3079
1
9
+3V
8
7
13
0.1
II
-80 -60 -40 -20
0
20 40 60 80 100 120 140
AMBIENT TEMPERATURE (oC)
FIGURE 9. INPUT BIAS CURRENT TEST CIRCUIT FOR CA3059
AND CA3079
FIGURE 8. OUTPUT LEAKAGE CURRENT (INHIBIT MODE) vs
AMBIENT TEMPERATURE FOR CA3059 AND CA3079
9
CA3059, CA3079
600
220VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS) = 10kΩ
220VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS) = 20kΩ
50Hz, tP
(+ dv/dt)
300
200
100
0
60Hz, tP
(+ dv/dt)
60Hz, tP
(+ dv/dt)
400
200
0
50Hz, tP
(+ dv/dt)
60Hz, tN
(- dv/dt)
60Hz, tN
(- dv/dt)
50Hz, tN
(- dv/dt)
50Hz, tN
(- dv/dt)
0
0.02
0.04
0.06
0.08
0.1
0
0.02
0.04
0.06
0.08
0.1
EXTERNAL CAPACITANCE (µF)
EXTERNAL CAPACITANCE (µF)
FIGURE 10A.
FIGURE 10B.
600
220VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS) = 20kΩ
220VRMS, 50/60Hz OPERATION
INPUT RESISTANCE (RS) = 10kΩ
50Hz, tN1
(- dv/dt)
600
400
200
0
60Hz, tN1
(- dv/dt)
60Hz, tN1
(- dv/dt)
400
200
0
50Hz, tN1
(- dv/dt)
50Hz, tP1
(+ dv/dt)
60Hz, tP1
(+ dv/dt)
60Hz, tP1
(+ dv/dt)
50Hz, tP1
(+ dv/dt)
0
0.02
0.04
0.06
0.08
0.1
0
0.02
0.04
0.06
0.08
0.1
EXTERNAL CAPACITANCE (µF)
EXTERNAL CAPACITANCE (µF)
FIGURE 10C.
FIGURE 10D.
FIGURE 10. RELATIVE PULSE WIDTH AND LOCATION OF ZERO CROSSING FOR 220V OPERATION FOR CA3059 AND CA3079
7
THYRISTOR TURN-OFF
SENSOR RESISTANCE = 5kΩ
AREA OF UNCERTAIN
OPERATION
30
20
10
0
18
12
6
6
5
4
3
2
1
0
TERMINALS 7 AND 12 CONNECTED
DC GATE CURRENT MODE
(CA3058 & CA3059)
AREA OF NORMAL
OPERATION
TERMINAL 12 OPEN
PULSED GATE CURRENT MODE
(ALL TYPES)
AREA OF UNCERTAIN
OPERATION
THYRISTOR TURN-OFF
0
-75 -50
-25
0
25
50
75 100 125
-50
-25
0
25
50
75
AMBIENT TEMPERATURE (oC)
AMBIENT TEMPERATURE (oC)
FIGURE 11. SENSITIVITY vs AMBIENT TEMPERATURE FOR
CA3059 AND CA3079
FIGURE 12. OPERATING REGIONS FOR BUILT-IN PROTEC-
TION CIRCUIT FOR CA3059
10
CA3059, CA3079
OFF
ON
10KΩ
RL
2W
RL
10KΩ
2W
5
6
1
MT2
120VAC
60Hz
5
6
1
3
MT2
MT1
ON
+
OFF
C1
120VAC
2
14
13
6
60Hz
2
14
9
G
MT1
100µF
15VDC
G
C1
R1
+
-
4
CA3059
10 11
-
100µF
15VDC
CA3059
CA3079
4
R1
8
7
7
12
3
9
12
13 10 11
tON = 0.67 R1C1
R1(max. value allowable) = 1mΩ
td = 0.67 R1C1
FIGURE 13. LINE-OPERATED ONE-SHOT TIMER
FIGURE 14. LINE-OPERATED THYRISTOR CONTROL TIME
DELAY TURN-ON CIRCUIT
ON
OFF
10KΩ
2W
RL
R1
6
MT2
C1
5
1
R2
2
14
13
6
G
RP
120VAC
60Hz
+
-
MT1
100µF
15VDC
4
CA3059
10 11
NTC
SENSOR
7
td = RTC1
12
3
9
R1R2
RT
=
R1 + R2
FIGURE 15. ON/OFF TEMPERATURE CONTROL CIRCUIT WITH DELAYED TURN-ON
12
SWITCHED
LOAD
10
11
MT2
MT1
5
1
120VAC
5KΩ
2W
13
8
T2300B
MAX LOAD = 2.5A
CA3059
1KΩ
RECTIFIER
AND TRIAC
CONTROL
4
G
7
6
9
100µF
10
KΩ
2
+
-
10KΩ
R2
68KΩ
R6
2MΩ
R3
100KΩ
R1
C1
1
7
5
13
12
11
R7
5KΩ
SENSOR
RESET
11
16
2
4
VDD
+
PULSE GENERATOR
CA3097E THYRISTOR/
TRANSISTOR ARRAY
9
6
OUTPUT
IN
10
COS/MOS CD4040A
12-STAGE COUNTER
14
NOTE:
1
Terminal 1 goes “High”
(Logic “1”) after 2048
pulses are applied to
Terminal 10.
3
8
15
10 16
R5
1KΩ
8
R4
10KΩ
For 8 hour delay:
R1 = 12MΩ
C1 = 2µF
FIGURE 16A. LINE-OPERATED IC TIMER FOR LONG TIME PERIODS
11
CA3059, CA3079
“NIGHT”
“DAY”
SENSOR ILLUMINATION
COUNTER RESET
(TERMINAL 11 OF CD4040)
e.g., 8 HRS
“CLOCK” PULSES
(TERMINAL 9 OF CA3097E)
1 PULSE/SEC
COUNTER OUTPUT
(TERMINAL 1 OF CD4040)
TERMINAL 6 OF CA3059 AND
TERMINAL 5 OF CA3097E
TERMINAL 4 OF CA3059
AND POWER IN LOAD
FIGURE 16B. TIMING DIAGRAM FOR FIGURE 16A
C1
100µF
2
RL
10
11
10K
2W
120VAC
60Hz
120pps
13
14
6
5
9
T2302B
MAX LOAD = 2.5A
TRIAC
CA3059
RESET
SW1
RUN
CONTROL
4
RECTIFIER
PULSE
GENERATOR
200Ω
TRIAC
1K
G
1
8
10K
MONOSTABLE
7
4
1K
ASTABLE
SW2
RESET
+VDD (≅ +6.5V)
120pps
11
16
+VDD (≅ +6.5V)
10
8
COS/MOS CD4020A
14-STAGE BINARY
COUNTER
C2
0.001
2
16
10
H
G
F
VDD Kd
Ka
27 28 29 210 211 212 213 214
CD4048A
EXPANDABLE
8 INPUT GATE
E
D
C
B
A
a
b
c
d
e
f
g
h
1
OUTPUT
PROGRAMMING
INTERCONNECTIONS
VSS Kb
Kc
9
8
7
15
EXP
FIGURE 17A. PROGRAMMABLE ULTRA-ACCURATE LINE-OPERATED TIMER.
12
CA3059, CA3079
TIME PERIODS (t = 0.5333 s)
1t
a
2t
b
4t
c
8t
16t
32t
f
64t
g
128t
h
tO
CD4020A TERMINALS
d
e
CD4048A TERMINALS
A
C
B
NC
C
C
NC
NC
NC
C
D
NC
NC
NC
NC
NC
NC
NC
C
E
F
G
H
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1t
NC
C
2t
3t
C
NC
C
NC
NC
C
4t
C
5t
NC
C
C
6t
C
C
7t
NC
C
NC
NC
C
NC
NC
NC
NC
C
8t
C
9t
NC
C
C
10t
11t
12t
13t
14t
15t
111t
112t
113t
C
C
NC
C
NC
NC
C
C
C
C
NC
C
C
C
C
C
C
C
C
C
C
NC
C
NC
NC
NC
NC
NC
NC
C
C
C
C
C
C
C
C
C
C
C
C
C
255t
NOTES:
1. tO = Total time delay = n1 t + n2 t + . . . nnt.
2. C = Connect. For example, interconnect terminal a of the CD4020A and terminal A of the CD4048A.
3. NC = No Connection. For example, terminal b of the CD4020A open and terminal B of the CD4048A connected to +VDD bus.
AC
SUPPLY
VOLTAGE
CA3059
OUTPUT
(PIN 4 AND PIN 6)
CD4048A
OUTPUT
AC IN LOAD (R L
)
FIGURE 17B. “PROGRAMMING” TABLE FOR FIGURE 17(A).
13
CA3059, CA3079
Operating Considerations
Power Supply Considerations for CA3059 and CA3079
2. Set the value of R and sensor resistance (R ) between
P X
2kΩ and 100kΩ.
The CA3059 and CA3079 are intended for operation as self-
powered circuits with the power supplied from and AC line
through a dropping resistor. The internal supply is designed
to allow for some current to be drawn by the auxiliary power
circuits. Typical power supply characteristics are given in
Figures 2(b) and 2(c).
3. The ratio of R to R , typically, should be greater than
X
P
0.33 and less than 3. If either of these ratios is not met
with an unmodified sensor over the entire anticipated
temperature range, then either a series or shunt resistor
must be added to avoid undesired activation of the circuit.
Power Supply Considerations for CA3059
If operation of the protection circuit is desired under condi-
tions other than those specified above, then apply the data
given in Figure 12.
The output current available from the internal supply may not
be adequate for higher power applications. In such applica-
tions an external power supply with a higher voltage should External Inhibit Function for the CA3059
be used with a resulting increase in the output level. (See
A priority inhibit command may be applied to Terminal 1. The
presence of at least +1.2V at 10µA will remove drive from
Figure 4 for the peak output current characteristics.) When
an external power supply is used, Terminal 5 should be con-
nected to Terminal 7 and the synchronizing voltage applied
to Terminal 12 as illustrated in Figure 5(a).
the thyristor. This required level is compatible with DTL or
2
T L logic. A logical 1 activates the inhibit function.
DC Gate Current Mode for the CA3059
Operation of Built-In Protection for the CA3059
Connecting Terminals 7 and 12 disables the zero-crossing
detector and permits the flow of gate current on demand
from the differential sensing amplifier. This mode of opera-
tion is useful when comparator operation is desired or when
inductive loads are switched. Care must be exercised to
avoid overloading the internal power supply when operating
in this mode. A sensitive gate thyristor should be used with a
resistor placed between Terminal 4 and the gate in order to
limit the gate current.
A special feature of the CA3059 is the inclusion of a protec-
tion circuit which, when connected, removes power from the
load if the sensor either shorts or opens. The protection cir-
cuit is activated by connecting Terminal 14 to Terminal 13 as
shown in the Functional Block Diagram. To assure proper
operation of the protection circuit the following conditions
should be observed:
1. Use the internal supply and limit the external load current
to 2mA with a 5kΩ dropping resistor.
Dimensions in parentheses are in millimeters and are derived from
the basic inch dimensions as indicated. Grid gradations are in mils
(10-3 inch).
The photographs and dimensions represent a chip when it is par of
the wafer. When the wafer is cut into chips, the cleavage angles are
57o instead of 90o with respect to the face of the chip. Therefore, the
isolated chip is actually 7 mils (0.17mm) larger in both dimensions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
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