CA3060 [HARRIS]
110kHz, Operational Transconductance Amplifier Array; 110kHz ，运算跨导放大器阵列
| 型号： | CA3060 |
| 厂家： | 
HARRIS CORPORATION |
| 描述： | 110kHz, Operational Transconductance Amplifier Array |
| 文件： | 总12页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Semiconductor
CA3060
110kHz, Operational
Transconductance Amplifier Array
January 1999
Features
Description
• Low Power Consumption as Low as 100mW Per
Amplifier
The CA3060 monolithic integrated circuit consists of an array of
three independent Operational Transconductance Amplifiers
(see Note). This type of amplifier has the generic characteris-
tics of an operational voltage amplifier with the exception that
the forward gain characteristic is best described by transcon-
ductance rather than voltage gain (open-loop voltage gain is the
product of the transconductance and the load resistance,
[ /Title
(CA30
60)
/Sub-
ject
• Independent Biasing for Each Amplifier
• High Forward Transconductance
• Programmable Range of Input Characteristics
• Low Input Bias and Input Offset Current
• High Input and Output Impedance
g R ). When operated into a suitable load resistor and with
M L
provisions for feedback, these amplifiers are well suited for a
wide variety of operational-amplifier and related applications. In
addition, the extremely high output impedance makes these
types particularly well suited for service in active filters.
(110k
Hz,
• No Effect on Device Under Output Short-Circuit
Conditions
Opera-
tional
Transc
onduc-
tance
Ampli-
fier
Array)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
triple,
transco
nduc-
tance
ampli-
fier,
low
power
op
The three amplifiers in the CA3060 are identical push-pull
Class A types which can be independently biased to achieve a
wide range of characteristics for specific application. The elec-
trical characteristics of each amplifier are a function of the
• Zener Diode Bias Regulator
Applications
amplifier bias current (I
). This feature offers the system
• For Low Power Conventional Operational Amplifier
Applications
ABC
designer maximum flexibility with regard to output current capa-
bility, power consumption, slew rate, input resistance, input bias
current, and input offset current. The linear variation of the
parameters with respect to bias and the ability to maintain a
constant DC level between input and output of each amplifier
also makes the CA3060 suitable for a variety of nonlinear appli-
cations such as mixers, multipliers, and modulators.
• Active Filters
• Comparators
• Gyrators
• Mixers
In addition, the CA3060 incorporates a unique Zener diode
regulator system that permits current regulation below sup-
ply voltages normally associated with such systems.
• Modulators
• Multiplexers
• Multipliers
NOTE: Generic applications of the OTA are described in AN-6668.
For improved input operating ranges, refer to CA3080 and CA3280
data sheets (File Nos. 475 and 1174) and application notes AN6668
and AN6818.
• Strobing and Gating Functions
• Sample and Hold Functions
Pinout
Part Number Information
CA3060
(PDIP)
TEMP.
PKG.
NO.
o
TOP VIEW
PART NUMBER RANGE ( C)
PACKAGE
16 Ld PDIP
CA3060E -40 to 85
E16.3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REGULATOR OUT
REGULATOR IN
V+
OUTPUT NO. 1
BIAS
REG.
BIAS NO. 1
AMP 1
NON-INV. INPUT NO. 1
INV. INPUT NO. 1
INV. INPUT NO. 2
NON-INV. INPUT NO. 2
BIAS NO. 2
INV. INPUT NO. 3
NON-INV. INPUT NO. 3
BIAS NO. 3
amp,
AMP
3
AMP
2
OUTPUT NO. 3
V-
OUTPUT NO. 2
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 537.4
Copyright © Harris Corporation 1999
3-1
CA3060
Absolute Maximum Ratings
Operating Conditions
o
o
Supply Voltage (Between V+ and V- Terminals). . . . . . . 36V (±18V)
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to V-
Differential Input Voltage (Each Amplifier) . . . . . . . . . . . . . . . . . . 5V
Input Current (Each Amplifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1mA
Amplifier Bias Current (Each Amplifier) . . . . . . . . . . . . . . . . . . .2mA
Bias Regulator Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA
Output Short Circuit Duration (Note 1) . . . . . . . . . . . . . . . . Indefinite
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
Thermal Information
o
Thermal Resistance (Typical, Note 2)
θJA ( C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
o
Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications
T = 25 C, V
= ±15V
A
SUPPLY
AMPLIFIER BIAS CURRENT
= 10µA
I
= 1µA
I
I
= 100µA
ABC
ABC
ABC
PARAMETER
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Offset Voltage
(See Figure 1)
V
-
-
-
-
1
3
-
-
1
-
-
1
5
mV
IO
Input Offset Current
(See Figure 2)
I
-
-
-
-
-
-
30
-
-
-
-
-
250
1000
5000
-
nA
nA
µA
IO
Input Bias Current
(See Figures 3, 4)
I
33
2.3
300
26
2500
240
IB
Peak Output Current
(See Figures 5, 6)
I
150
OM
Peak Output Voltage
(See Figure 7)
Positive
V
+
-
-
-
13.6
14.7
8.5
-
-
-
-
-
-
13.6
14.7
85
-
-
-
12
12
-
13.6
14.7
850
-
-
V
V
OM
Negative
V
-
OM
Amplifier Supply Current (Each
Amplifier)
I
1200
µA
A
(See Figures 8, 9)
Power Consumption
(Each Amplifier)
P
-
0.26
-
-
2.6
-
-
26
36
mW
Input Offset Voltage Sensitivity
(Note 3)
Positive
∆V /∆V+
IO
-
-
-
1.5
20
-
-
-
-
-
-
2
-
-
-
-
-
-
2
150
150
-
µV/V
µV/V
V
Negative
∆V /∆V-
IO
20
30
Amplifier Bias Voltage
(Note 4, See Figure 10)
V
0.54
0.60
0.66
ABC
DYNAMIC CHARACTERISTICS At 1kHz, Unless Otherwise Specified
Forward Transconductance
(Large Signal)
(See Figures 11, 12)
g
-
1.55
-
-
-
18
-
30
70
102
90
-
mS
21
Common Mode Rejection
Ratio
CMRR
-
110
-
-
-
-
110
-
-
-
-
-
-
-
-
dB
V
Common Mode Input Voltage
Range
V
+12 to +13 to
-12
+12 to +13 to
-12
+12 to +13 to
-12
ICR
-14
-14
-14
Slew Rate (Test Circuit)
(See Figure 17)
SR
-
0.1
-
1
-
8
V/µs
kHz
Open Loop (g ) Bandwidth
21
BW
OL
-
20
-
45
-
110
(See Figure 13)
3-2
CA3060
o
Electrical Specifications
T = 25 C, V
SUPPLY
= ±15V (Continued)
A
AMPLIFIER BIAS CURRENT
= 10µA
I
= 1µA
I
I
= 100µA
ABC
ABC
ABC
PARAMETER
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Impedance Components
Resistance (See Figure 14)
R
C
-
-
1600
2.7
-
-
-
-
170
2.7
-
-
10
-
20
-
-
kΩ
I
I
Capacitance at 1MHz
2.7
pF
Output Impedance Components
Resistance (See Figure 15)
R
C
-
-
200
4.5
-
-
-
-
20
-
-
-
-
2
-
-
MΩ
O
Capacitance at 1MHz
4.5
4.5
pF
O
ZENER BIAS REGULATOR CHARACTERISTICS I = 0.1mA
2
Voltage (See Figure 16)
V
Temperature
Coefficient = 3mV/ C
6.2
-
6.7
7.9
V
Z
o
Impedance
NOTES:
Z
200
300
Ω
Z
3. Conditions for Input Offset Voltage Sensitivity:
a. Bias current derived from the regulator with an appropriate resistor connected from Terminal 1 to the bias terminal on the amplifier
under test V+ is reduced to +13V for V+ sensitivity and V- is reduced to -13V for V- sensitivity.
V
– V
Offset
µV ⁄ V = ------------------------------------------------------------------------------------------------------------------------------ ,
for +13V and -15V Supplies
Offset
b. V+ Sensitivity in
1V
V
– V
Offset
V- Sensitivity in µV ⁄ V = ------------------------------------------------------------------------------------------------------------------------------.
for -13V and +15V Supplies
Offset
1V
= 1µA); -2.1mV/ C (at V
o
o
o
4. Temperature Coefficient; -2.2mV/ C (at V
ABC
= 0.54, I
ABC
= 0.060V, I
ABC
= 10µA); -1.9mV/ C (at V = 0.66V,
ABC
ABC
I
= 100µA)
ABC
Schematic Diagram
BIAS REGULATOR AND ONE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
ZENER BIAS REGULATOR
D
4
V+
2
1
3
D
2
Q
4
Q
Q
5
10
Q
Q
7
6
D
5
-
INVERTING INPUT
(NOTE 5)
Q
Q
OUTPUT (NOTE 8)
1
2
+
NON-INVERTING INPUT
(NOTE 6)
Q
8
I
ABC
D
3
AMPLIFIER BIAS INPUT
(NOTE 7)
Q
3
D
1
V-
8
NOTES:
5. Inverting Input of Amplifiers 1, 2 and 3 is on Terminals 13, 12 and 4, respectively.
6. Non-inverting Input of Amplifiers 1, 2 and 3 is Terminals 14, 11 and 5, respectively.
7. Amplifier Bias Current of Amplifiers 1, 2 and 3 is on Terminals 15, 10 and 6, respectively.
8. Output of Amplifiers 1, 2 and 3 is on Terminals 16, 9 and 7, respectively.
3-3
CA3060
Typical Performance Curves
2.0
1000
MAXIMUM
TYPICAL
SUPPLY VOLTAGE:
V
V
= ±6
= ±15
S
S
1.5
1.0
0.5
0.0
100
10
1
o
125 C
o
25 C
o
o
-55 C
T
= 25 C
A
SUPPLY VOLTAGE:
V
V
= ±6
S
S
= ±15
1
10
100
1000
1
10
100
1000
AMPLIFIER BIAS CURRENT (µA)
AMPLIFIER BIAS CURRENT (µA)
FIGURE 1. INPUT OFFSET VOLTAGE vs AMPLIFIER BIAS
CURRENT
FIGURE 2. INPUT OFFSET CURRENT vs AMPLIFIER BIAS
CURRENT
10
10
SUPPLY VOLTAGE: V = ±6
S
MAXIMUM
V
= ±15
S
I
= 100µA
= 10µA
ABC
TYPICAL
1
1.0
0.1
I
ABC
0.1
o
T
= 25 C
A
SUPPLY VOLTAGE:
V
V
= ±6
= ±15
S
S
I
= 1µA
ABC
0.01
0.01
1
10
100
1000
-75
-50
-25
0
25
50
o
75
100
125
AMPLIFIER BIAS CURRENT (µA)
TEMPERATURE ( C)
FIGURE 3. INPUT BIAS CURRENT vs AMPLIFIER BIAS CURRENT
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
1000
1000
TYPICAL
I
= 100µA
= 30µA
ABC
I
I
ABC
ABC
MINIMUM
100
10
1
100
= 10µA
I
I
= 3µA
= 1µA
ABC
ABC
o
10
1
T
= 25 C
A
SUPPLY VOLTAGE:
V
V
= ±6
= ±15
S
S
SUPPLY VOLTAGE: V = ±6
S
S
V
= ±15
-75
-50
-25
0
25
50
o
75
100
125
1
10
100
1000
AMPLIFIER BIAS CURRENT (µA)
TEMPERATURE ( C)
FIGURE 5. PEAK OUTPUT CURRENT vs AMPLIFIER BIAS
CURRENT
FIGURE 6. PEAK OUTPUT CURRENT vs TEMPERATURE
3-4
CA3060
Typical Performance Curves (Continued)
14
10,000
o
T = 25 C
A
13
12
6
V
+ (TYP)
OM
±15V SUPPLY
SUPPLY VOLTAGE:
V
= ±6
= ±15
V
+ (MIN)
S
S
OM
±15V SUPPLY
V
5
TYPICAL
1000
100
10
4
MAXIMUM
3
V
+ (TYP)
OM
±6V SUPPLY
V
+ (MIN)
OM
±6V SUPPLY
-3
V
- (MIN)
OM
±6V SUPPLY
-4
-5
-6
-12
-13
-14
-15
V
- (TYP)
V
- (MIN)
OM
±6V SUPPLY
V
- (TYP)
OM
±15V SUPPLY
OM
±15V SUPPLY
1
10
100
1000
1
10
100
1000
AMPLIFIER BIAS CURRENT (µA)
AMPLIFIER BIAS CURRENT (µA)
FIGURE 7. PEAK OUTPUT VOLTAGE vs AMPLIFIER BIAS
CURRENT
FIGURE 8. AMPLIFIER SUPPLY CURRENT (EACH AMPLIFIER)
vs AMPLIFIER BIAS CURRENT
800
1000
SUPPLY VOLTAGE: VV = ±6
S
I
= 100µA
= 30µA
V
= ±15
ABC
S
750
700
650
600
550
500
I
I
ABC
100
10
1
= 10µA
= 3µA
= 1µA
ABC
I
ABC
I
ABC
SUPPLY VOLTAGE: V+ = 6V, V- = -6V
V+ = 15V, V- = -15V
1
10
100
1000
-75
-50
-25
0
25
50
o
75
100
125
AMPLIFIER BIAS CURRENT (µA)
TEMPERATURE ( C)
FIGURE 9. AMPLIFIER SUPPLY CURRENT (EACH AMPLIFIER)
vs TEMPERATURE
FIGURE 10. AMPLIFIER BIAS VOLTAGE vs AMPLIFIER BIAS
CURRENT
1000
o
1000
o
T
= 25 C, f = 1kHz
T
= 25 C, f = 1kHz
A
A
SUPPLY VOLTAGE: V = ±6
SUPPLY VOLTAGE:
V
V
= ±6
= ±15
S
S
S
V
= ±15
S
100
10
1
I
= 100µA
TYPICAL
ABC
100
10
1
I
= 30µA
ABC
MINIMUM
I
= 10µA
ABC
I
= 1µA
ABC
-50 -25
0
25
50
75
100 125
1
10
100
1000
o
AMPLIFIER BIAS CURRENT (µA)
TEMPERATURE ( C)
FIGURE 11. FORWARD TRANSCONDUCTANCE vs AMPLIFIER
BIAS CURRENT
FIGURE 12. FORWARD TRANSCONDUCTANCE vs
TEMPERATURE
3-5
CA3060
Typical Performance Curves (Continued)
100
0
10,000
I
= 100µA
ABC
o
T
= 25 C, f = 1kHz
A
-50
SUPPLY VOLTAGE:
V
V
= ±6
= ±15
S
S
10
-100
-150
-200
-250
-300
-350
I
= 10µA
= 1µA
ABC
I
ABC
1000
100
10
1.0
o
0.1
T
= 25 C
I
= 10µA
A
ABC
SUPPLY VOLTAGE:
V
V
I
= 1µA
= ±6
= ±15
ABC
S
S
TYPICAL
MINIMUM
100
AMPLIFIER BIAS CURRENT (µA)
0.01
0.001
0.01
0.1
1.0
10
100
1
10
1000
PHASE ANGLE
FORWARD TRANS.
FREQUENCY (MHz)
FIGURE 13. FORWARD TRANSCONDUCTANCE vs FREQUENCY FIGURE 14. INPUT RESISTANCE vs AMPLIFIER BIAS CURRENT
7.0
6.75
6.5
1000
100
10
o
T
= 25 C
o
A
T
= 25 C, f = 1kHz
A
SUPPLY VOLTAGE:
SUPPLY VOLTAGE:
V
V
= ±6
= ±15
S
S
V
V
= ±6
= ±15
S
S
TYPICAL
TYPICAL
6.25
1
1
10
100
1000
0
200
400
600
800
1000 1200 1400
BIAS REGULATOR CURRENT (µA)
AMPLIFIER BIAS CURRENT (µA)
FIGURE 15. OUTPUT RESISTANCE vs AMPLIFIER BIAS CURRENT
FIGURE 16. BIAS REGULATOR VOLTAGE vs BIAS
REGULATOR CURRENT
Test Circuit
V
is measured between Terminal 1 and 8
R
F
Z
V
is measured between Terminals 15 and 8
ABC
V+
V
– V
ABC
IN-
PUT
[(V+) – (V- ) – 0.7]
Z
-----------------------------------------------
R
=
, R
= ----------------------------
R
-
Z
ABC
S
3
I
I
2
ABC
13
14
OUT- EXTERNAL
PUT LOAD
Supply Voltage: For both ±6V and ±15V
R
C
AMPLIFIER
1
16
C
TYPICAL SLEW RATE TEST CIRCUIT PARAMETERS
SLEW
C
13
pF
+
10
MΩ
15
1
I
RATE
V/µs
8
I
R
R
R
R
R
C
C
8
ABC
2
ABC
S
F
B
C
2
R
B
µA
µA
Ω
Ω
Ω
Ω
Ω
µF
0.02
0.005
0
I
ABC
100
10
1
200
62K
100K 100K 51K 100
1M 1M 510K 1K
6.2M 10M 10M 5.1M
R
Z
R
ABC
1
200 620K
I
2
0.1
2
∞
V-
FIGURE 17. SLEW RATE TEST CIRCUIT FOR AMPLIFIER 1 OF CA3060
3-6
CA3060
In addition, the high output impedance makes these amplifi-
ers ideal for applications where current summing is involved.
Application Information
The CA3060 consists of three operational amplifiers similar
in form and application to conventional operational amplifiers
but sufficiently different from the standard operational
amplifier (op amp) to justify some explanation of their
characteristics. The amplifiers incorporated in the CA3060
are best described by the term Operational Transconduc-
tance Amplifier (OTA). The characteristics of an ideal OTA
are similar to those of an ideal op amp except that the OTA
has an extremely high output impedance. Because of this
inherent characteristics the output signal is best defined in
terms of current which is proportional to the difference
between the voltages of the two input terminals. Thus, the
transfer characteristics is best described in terms of
transconductance rather than voltage gain. Other than the
difference given above, the characteristics tabulated are
similar to those of any typical op amp.
The design of a typical operational amplifier circuit (Figure
19) would proceed as follows:
Circuit Requirements
Closed Loop Voltage Gain = 10 (20dB)
Offset Voltage Adjustable to Zero
Current Drain as Low as Possible
Supply Voltage = ±6V
Maximum Input Voltage = ±50mV
Input Resistance = 20kΩ
Load Resistance = 20kΩ
Device: CA3060
+6V
0.1
R
3
F
200kΩ
The OTA circuitry incorporated in the CA3060 (Figure 18)
provides the equipment designer with a wider variety of
circuit arrangements than does the standard op amp;
because as the curves indicate, the user may select the
optimum circuit conditions for a specific application simply by
varying the bias conditions of each amplifier. If low power
consumption, low bias, and low offset current, or high input
impedance are primary design requirements, then low
current operating conditions may be selected. On the other
hand, if operation into a moderate load impedance is the
primary consideration, then higher levels of bias may be
used.
R
20kΩ
S
13
INPUT
-
AMPLIFIER
1
16
+6V
R
20kΩ
L
+
14
15
2.2MΩ
R
OFFSET
<4MΩ
8
18kΩ
R
ABC
560kΩ
0.1
-6V
TO +6V
-6V
V+
Q
D
D
6
11
5
FIGURE 19. 20dB AMPLIFIER USING THE CA3060
Q
Q
7
15
Calculation
D
D
7
1. Required Transconductance g . Assume that the
Q
10
21
Q
14
open loop gain A must be at least ten times the closed
loop gain. Therefore, the forward transconductance
required is given by:
Q
3
OL
8
D
INVERTING
INPUT
2
Q
2
g
= A /R
OL
Q
Q
13
-
21
L
Q
9
5
D
Q
3
= 100/18kΩ
+
5.5mS
OUTPUT
4
AMPLIFIER
BIAS
Q
(R = 20kΩ in parallel with 200kΩ 18kΩ)
12
L
CURRENT
NON-
2. Selection of Suitable Amplifier Bias Current. The ampli-
fier bias current is selected from the minimum value curve
of transconductance (Figure 11) to assure that the amplifi-
INVERTING
INPUT
Q
1
(ABC)
D
4
Q
Q
8
D
1
6
er will provide sufficient gain. For the required g
5.5mS an amplifier bias current I
ABC
of
of 20µA is suitable.
21
V-
V-
COMPLETE OTA CIRCUIT
3. Determination of Output Swing Capability. For a
closed loop gain of 10 the output swing is ±0.5V and the
peak load current is 25µA. However, the amplifier must
also supply the necessary current through the feedback
FIGURE 18. COMPLETE SCHEMATIC DIAGRAM SHOWING BIAS
REGULATOR AND ONE OF THE THREE
OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS
resistor and if R = 20kΩ, then R = 200kΩ for A = 10.
S
F
CL
Bias Consideration for Op Amp Applications
Therefore, the feedback loading = 0.5V/200kΩ = 2.5µA.
The total amplifier current output requirements are, there-
fore, ±27.5µA. Referring to the data given in Figure 5, we
see that for an amplifier bias current of 20µA the amplifier
output current is ±40µA. This is obviously adequate and it
is not necessary to change the amplifier bias current
The operational transconductance amplifiers allow the circuit
designer to select and control the operating conditions of the
circuit merely by the adjustment of the amplifier bias current
I
. This enables the designer to have complete control
ABC
over transconductance, peak output current and total power
consumption independent of supply voltage.
I
.
ABC
3-7
CA3060
4. Calculation of Bias Resistance. For minimum supply
current drain the amplifier bias current I should be fed
0
-20
-40
-60
-80
ABC
directly from the supplies and not from the bias regulator.
R
C
= 10kΩ
L
L
The value of the resistor R
using Ohm’s law.
may be directly calculated
ABC
= 0
V
– V
ABC
SUP
R
= -------------------------------------
ABC
I
ABC
12 – 0.63
= -------------------------
–6
R
R
ABC
ABC
20 × 10
R
C
= 10kΩ
L
L
= 15pF
= 568.5kΩ or 560kΩ
0.01
0.1
1.0
10
100
5. Calculation of Offset Adjustment Circuit. In order to
reduce the loading effect of the offset adjustment circuit
on the power supply, the offset control should be
arranged to provide the necessary offset current. The
source resistance of the non-inverting input is made
equal to the source resistance of the inverting input,
FREQUENCY (MHz)
FIGURE 20. EFFECT OF CAPACITIVE LOADING ON
FREQUENCY RESPONSE
A
B
C
D
E
F
G
1000
100
10
20kΩ × 200kΩ
20kΩ + 200kΩ
---------------------------------------
i.e.,
18kΩ
H
I
Because the maximum offset voltage is 5mV plus an
additional increment due to the offset current (Figure 2)
J
K
L
-9
flowing through the source resistance (i.e., 200 x 10
x
3
18 x 10 V), the Offset Voltage Range = 5mV + 3.6mV =
±8.6mV. The current necessary to provide this offset is:
8.6mV
18kΩ
-----------------
0.48µA
1
With a supply voltage of ±6V, this current can be
provided by a 10MΩ resistor. However, the stability of
such a resistor is often questionable and a more realistic
value of 2.2MΩ was used in the final circuit.
0.01
0.1
1.0
10
100
SLEW RATE (V/µs)
A. C = 10,000pF
B. C = 3,000pF
G. C = 10pF
L
H. C = 3pF
L
Capacitance Effects
L
L
C. C = 1000pF
L
I.
C = 1pF
L
The CA3060 is designed to operate at such low power levels
that high impedance circuits must be employed. In designing
such circuits, particularly feedback amplifiers, stray circuit
capacitance must always be considered because of its
adverse effect on frequency response and stability. For
example a 10kΩ load with a stray capacitance of 15pF has a
time constant of 1MHz. Figure 20 illustrates how a 10kΩ
15pF load modifies the frequency characteristic.
D. C = 300pF
J. C = 0.3pF
K. C = 0.1pF
L. C = 0.03pF
L
L
L
E. C = 100pF
L
L
F. C = 30pF
L
FIGURE 21. EFFECT OF LOAD CAPACITANCE ON SLEW RATE
Phase Compensation
In many applications phase compensation will not be
required for the amplifiers of the CA3060. When needed,
compensation may easily be accomplished by a simple RC
network at the input of the amplifier as shown in Figure 17.
The values given in Figure 17 provide stable operation for
the critical unity gain condition, assuming that capacitive
loading on the output is 13pF or less. Input phase compen-
sation is recommended in order to maintain the highest
possible slew rate.
Capacitive loading also has an effect on slew rate; because
the peak output current is established by the amplifier bias
current, I
(Figure 5), the maximum slew rate is limited to
ABC
the maximum rate at which the capacitance can be charged
by the I . Therefore, SR = dv/dt = I /C , where C is the
OM OM
L
L
total load capacitance including strays. This relationship is
shown graphically in Figure 21. When measuring slew rate
for this data sheet, care was taken to keep the total
capacitive loading to 13pF.
In applications such as integrators, two OTAs may be
cascaded to improve current gain. Compensation is best
accomplished in this case with a shunt capacitor at the
output of the first amplifier. The high gain following compen-
sation assures a high slew rate.
3-8
CA3060
Circuit Description
Typical Applications
Figure 23 shows the block diagram of a tri-level comparator
using the CA3060. Two of the three amplifiers are used to
compare the input signal with the upper limit and lower limit
reference voltages. The third amplifier is used to compare
the input signal with a selected value of intermediate limit
reference voltage. By appropriate selection of resistance
ratios this intermediate limit may be set to any voltage
between the upper limit and lower limit values. The output of
the upper limit and lower limit comparator sets the corre-
sponding upper or lower limit flip-flop. The activated flip-flop
retains its state until the third comparator (intermediate limit)
in the CA3060 initiates a reset function, thereby indicating
that the signal voltage has returned to the intermediate limit
selected. The flip-flops employ two CA3086 transistor array
ICs, with circuitry to provide separate “SET” and “POSITIVE
OUTPUT” terminals.
Having determined the operating points of the CA3060
amplifiers, they can now function in the same manner as
conventional op amps, and thus, are well suited for most op
amp applications, including inverting and non-inverting
amplifiers, integrators, differentiators, summing amplifiers
etc.
Tri-Level Comparator
Tri-level comparator circuits are an ideal application for the
CA3060 since it contains the requisite three amplifiers. A tri-
level comparator has three adjustable limits. If either the
upper lower limit is exceeded, the appropriate output is
activated until the input signal returns to a selected
intermediate limit. Tri-level comparators are particularly
suited to many industrial control applications.
SATURATES WHEN
V+ = 6V
V+ = 6V
UPPER LIMIT IS
EXCEEDED
3
INPUT SIGNAL
(E )
S
100
CA3086
REGULATOR
IN CA3060
1
LOAD
4.7K
8
20K
10K
V+ = 6V
2
8
6
5.1K
Q
1
25K
I
ABC
15
7
V- = -6V
SET
5.1K
5.1K
150K
5
1
13K
+
14
13
1/3
CA3060
16
11
9
10
4
2
E
WHEN
U
-
UPPER
LIMIT IS
R
10K
3
4
I
ABC
EXCEEDED
14
13
12
UPPER LIMIT
FLIP-FLOP
10
R
2
5.1K
1K
-
12
11
RESET
1/3
CA3060
UPPER LIMIT
REFERENCE
VOLTAGE
9
SATURATES WHEN
LOWER LIMIT IS
EXCEEDED
WHEN INTERMEDIATE REFERENCE
LIMIT IS EXCEEDED
V+ = 6V
+
100
CA3086
INTERMEDIATE LIMIT
REFERENCE VOLTAGE
LOAD
8
4.7K
150K
10K
E
- E
L
U
R
10K
3
I
2
ABC
6
Q
2
6
LOWER LIMIT
REFERENCE
VOLTAGE
7
5.1K
5.1K
5.1K
5
1
4
5
-
SET
E
L
1/3
7
10
11
9
4
2
CA3060
+
WHEN
LOWER
LIMIT IS
EXCEEDED
3
13
12
14
LOWER LIMIT
FLIP-FLOP
R
1K
1
NOTES:
9. Items in dashed boxes are external to the CA3086.
All resistance values are in ohms.
10.
E
E
> E = Q (ON), Q (OFF)
U 1 2
S
L
E
– E
L
2
U
-------------------
= Q (OFF), Q (OFF)
1 2
E
<
< E = Q (ON), Q (OFF)
S
U
2
1
FIGURE 22. TRI-LEVEL COMPARATOR CIRCUIT
3-9
CA3060
Active Filters - Using the CA3060 as a Gyrator
V+
CA3060
The high output impedance of the OTAs makes the CA3060
ideally suited for use as a gyrator in active filter applications.
Figure 24 shows two OTAs of the CA3060 connected as a
gyrator in an active filter circuit. The OTAs in this circuit can
make a 3µF capacitor function as a floating 10kH inductor
across Terminals A and B. The measured Q of 13 (at a
frequency of 1Hz) of this inductor compares favorably with a
calculated Q of 16. The 20kΩ to 2MΩ attenuators in this
circuit extend the dynamic range of the OTA by a factor of
100. The 100kΩ potentiometer, across V+ and V-, tunes the
TRI-LEVEL
DETECTOR
V+
UPPER LIMIT
REFERENCE
VOLTAGE
SET
CA3086
POSITIVE
OUTPUT
-
+
FLIP-FLOP
(WHEN UPPER
LIMIT IS
INPUT
SIGNAL
RESET
+
-
REACHED)
INTERMEDIATE
LIMIT REFER-
ENCE VOLTAGE
V+
SET
CA3086
FLIP-FLOP
POSITIVE
OUTPUT
+
-
LOWER LIMIT
REFERENCE
VOLTAGE
inductor by varying the g of the OTAs, thereby changing
21
(WHEN LOWER
LIMIT IS
REACHED)
the gyration resistance.
V-
Three Channel Multiplexer
FIGURE 23. FUNCTIONAL BLOCK DIAGRAM OF A TRI-LEVEL
COMPARATOR
Figure 25 shows a schematic of a three channel multiplexer
using a single CA3060 and a 3N153 MOSFET as a buffer
and power amplifier.
The circuit diagram of a tri-level comparator appears in Figure
22. Power is provided for the CA3060 via terminal 3 and 8 by
±6V supplies and the built-in regulator provides amplifier bias
current (I
) to the three amplifiers via terminal 1. Lower
ABC
V+ = 15V
V+ = 15V
limit and upper limit reference voltages are selected by appro-
priate adjustment of potentiometers R and R , respectively.
When resistors R and R are equal in value (as shown), the
intermediate limit reference voltage is automatically estab-
lished at a value midway between the lower limit and upper
limit values. Appropriate variation of resistors R and R per-
mits selection of other values of intermediate limit voltage.
Input signal (E ) is applied to the three comparators via termi-
nals 5, 12 and 14. The “SET” output lines trigger the appropri-
ate flip-flop whenever the input signal reaches a limit value.
When the input signal returns to an intermediate value, the
common flip-flop “RESET” line is energized. The loads in the
circuits, shown in Figure 22 are 5V, 25mA lamps.
1
2
0.01µF
3
4
3
2kΩ
4
5
-
7
2kΩ
3
4
+
8
6
S
0.02
300kΩ
µF
V- = -15V
STROBE
3N153
2kΩ
12
11
-
9
3
4
2
2kΩ
+
V+ = 6V
390Ω
3
AMP 1
15
TERMINAL
A
10
0.001µF
20kΩ
20kΩ
300kΩ
14
13
STROBE
16
OUTPUT
2kΩ
3kΩ
13
14
-
16
2kΩ
V+
V-
+
560kΩ
V- = -15V
20
kΩ
20
kΩ
15
100kΩ
2MΩ
L = 10kH
+15V STROBE “ON”
-15V STROBE “OFF”
300kΩ
560kΩ
STROBE
10
3µF
FIGURE 25. THREE CHANNEL MULTIPLEXER
12
11
When the CA3060 is connected as a high input impedance
voltage follower, and strobe “ON”, each amplifier is activated
and the output swings to the level of the input of the
amplifier. The cascade arrangement of each CA3060
amplifier with the MOSFET provides an open loop voltage
gain in excess of 100dB, thus assuring excellent accuracy in
the voltage follower mode with 100% feedback. Operation at
±6V is also possible with several minor changes. First, the
9
AMP 2
8
2MΩ
TERMINAL
B
V- = -6V
resistance in series with the amplifier bias current (I
) ter-
ABC
FIGURE 24. TWO OPERATIONAL TRANSCONDUCTANCE
AMPLIFIERS OF THE CA3060 CONNECTED AS A
GYRATOR IN AN ACTIVE FILTER CIRCUIT
minal of each amplifier should be decreased to maintain
100µA of strobe “ON” current at this lower supply voltage.
Second, the drain resistance for the MOSFET should be
3-10
CA3060
decreased to maintain the same value of source current. and 3 is shown in Figure 27 and a typical circuit is shown in
The low cost dual gate protected MOSFET, 40841 type, may Figure 28. The multiplier consists of a single CA3060 and,
be used when operating at the low supply voltage.
as in the two quadrant multiplier, exhibits no level shift
between input and output. In Figure 27, Amplifier 1 is
connected as an inverting amplifier for the X-input signal.
The output current of Amplifier 1 is calculated as follows:
The phase compensation network consists of a single 390Ω
resistor and a 1000pF capacitor, located at the interface of the
CA3060 output and the MOSFET gate. The bandwidth of the
system is 1.5MHz and the slew rate is 0.3V/µs. The system
slew rate is directly proportional to the value of the phase
compensation capacitor. Thus, with higher gain settings
where lower values of phase compensation capacitors are
possible, the slew rate is proportionally increased.
I (1) = [-V ] [g (1)]
21
EQ. 1
O
X
Amplifier 2 is a non-inverting amplifier so that
IO(2) = [+VX] [g (2)]
EQ. 2
21
Because the amplifier output impedances are high, the load
current is the sum of the two output currents, for an output
voltage
Non-Linear Applications
AM Modulator (Two Quadrant Multiplier)
V
= V R [g (2) - g (1)]
21 21
EQ. 3
O
X L
Figure 26 shows Amplifier 3 of the CA3060 used in an AM
modulator or two quadrant multiplier circuit. When modula-
tion is applied to the amplifier bias input, Terminal B, and the
carrier frequency to the differential input, Terminal A, the
waveform, shown in Figure 26 is obtained. Figure 26 is a
result of adjusting the input offset control to balance the
circuit so that no modulation can occur at the output without
a carrier input. The linearity of the modulator is indicated by
the solid trace of the superimposed modulating frequency.
The maximum depth of modulation is determined by the ratio
of the peak input modulating voltage to V-.
The transconductance is approximately proportional to the
amplifier bias current; therefore, by varying the bias current
the g is also controlled. Amplifier 2 bias current is propor-
21
tional to the Y-input signal and is expressed as
(V- ) + V
Y
------------------------
I
≈
EQ. 4
EQ. 5
ABC(2)
R
1
Hence,
(2) ≈ k [(V-) + V ]
g
21
Y
The two quadrant multiplier characteristic of this modulator is
easily seen if modulation and carrier are reversed as shown in
Figure 26. The polarity of the output must follow that of the dif-
ferential input; therefore, the output is positive only during, the
positive half cycle of the modulation and negative only in the
second half cycle. Note, that both the input and output signals
are referenced to ground. The output signal is zero when
Bias for Amplifier 1 is derived from the output of Amplifier 3
which is connected as a unity gain inverting amplifier.
I
, therefore, varies inversely with V . And by the same
ABC(1)
Y
reasoning as above
g
(1) ≈ k [(V-) - V ]
EQ. 6
21
Y
either the differential input or I
are zero.
ABC
Combining Equations 3, 5 and 6 yields:
≈ V x k x R {[(V-) + V ] - [(V-) - V ]} or
Four Quadrant Multiplier
V
O
X
L
Y
Y
The CA3060 is also useful as a four quadrant multiplier. A
block diagram of such a multiplier, utilizing Amplifiers 1, 2
V
≈ 2kR V V
L X Y
O
+6V
3
CARRIER
-
MODULATED
OUTPUT
4
TERM.
A
10kΩ
7
AMP 3
1kΩ
1kΩ
5
+
100kΩ
8
1MΩ
6
-6V
1MΩ
V+
MODULATION
TERM.
V-
100kΩ
B
10kΩ
FIGURE 26. TWO QUADRANT MULTIPLIER CIRCUIT USING THE CA3060 WITH ASSOCIATED WAVEFORMS
3-11
CA3060
Figures 29B and 29C, respectively, show the squaring of a
I
-
O(1)
triangular wave and a sine wave. Notice that in both cases
the output is always positive and returns to zero after each
cycle.
AMP
1
+
X
V
INPUT
O
R
R
1
2
I
I
ABC (1)
+
CA3060
R
L
X
INPUT
1MΩ
1MΩ
13
OUTPUT
AMP
-
AMP
1
2
16
15
14
I
O(2)
270Ω
1MΩ
1MΩ
100Ω
ABC (2)
270Ω
51kΩ
R
F
200kΩ
270Ω
Y
4
INPUT
R
IN
51
kΩ
-
Y
4
5
INPUT
AMP
3
AMP
3
560kΩ
7
6
100Ω
+
240kΩ
0.02µF
V+
V-
100kΩ
100kΩ
24kΩ
FIGURE 27. FOUR QUADRANT MULTIPLIER
3
1.1MΩ
Figure 28 shows the actual circuit including all the adjust-
ments associated with differential input and an adjustment
for equalizing the gains of Amplifiers 1 and 2. Adjustment of
the circuit is quite simple. With both the X and Y voltages at
zero, connect Terminal 10 to Terminal 8. This procedure
disables Amplifier 2 and permits adjusting the offset voltage
of Amplifier 1 to zero by means of the 100kΩ potentiometer.
Next, remove the short between Terminal 10 and 8 and
connect Terminal 15 to Terminal 8. This step disables
Amplifier 1 and permits Amplifier 2 to be zeroed with the
other potentiometer. With AC signals on both the X and Y
10
11
12
AMP
2
9
8
560kΩ
270Ω
FIGURE 28. TYPICAL FOUR QUADRANT MULTIPLIER CIRCUIT
inputs, R and R
are adjusted for symmetrical output
3
11
signals. Figure 29 shows the output waveform with the
multiplier adjusted. The voltage waveform in Figure 29A
shows suppressed carrier modulation of 1kHz carrier with a
triangular wave.
FIGURE 29A.
FIGURE 29B.
FIGURE 29C.
FIGURE 29. VOLTAGE WAVEFORMS OF FOUR QUADRANT MULTIPLIER CIRCUIT
3-12
相关型号：
©2020 ICPDF网 联系我们和版权申明