OPTIGA AUTHENTICATE S [INFINEON]
Consumer devices, home appliances and industrial machines are constantly exposed to the risk of counterfeit spares and accessories. Fakes can compromise functionality, user safety and – as a result – brand value. OPTIGA™ Authenticate S can solve this issue. It is a fully fledged, turnkey hardware-based security solution for any device authentication challenge. This anti-counterfeit solution offers unprecedented levels of configuration flexibility and a range of hardened security features.;
| 型号： | OPTIGA AUTHENTICATE S |
| 厂家： | 
Infineon |
| 描述： | Consumer devices, home appliances and industrial machines are constantly exposed to the risk of counterfeit spares and accessories. Fakes can compromise functionality, user safety and – as a result – brand value. OPTIGA™ Authenticate S can solve this issue. It is a fully fledged, turnkey hardware-based security solution for any device authentication challenge. This anti-counterfeit solution offers unprecedented levels of configuration flexibility and a range of hardened security features. |
| 文件： | 总24页 (文件大小：1267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Description
This short data sheet describes the OPTIGA™ Authenticate S authentication device together with its features
and functionality.
Features
Authentication
–
–
–
–
–
–
163-bit Elliptic Curve Cryptography (ECC) Engine
193-bit OPTIGA Digital Certificate (ODC)
Message Authentication Code (MAC) function for user data authentication
MAC based Host Authentication (selected sales codes)
Customizable kill (end-of-life) features
Unique Chip ID 96-bit
Non-Volatile Memory
–
–
–
Lockable User NVM memory
32-bit page granularity
Lifespan indicator
Communication Interface
–
–
–
I2C I/O interface
SWI I/O interface
GPO as output interface
Package
–
Package PG-TSNP-6-12
ESD
–
–
–
–
JESD22-A114 ESD HBM 2KV standard
JESC-C101 ESD CDM 500V standard
IEC-61000-4-2 contact discharge 8KV for I/O pins
IEC-61000-4-2 air discharge 15KV for I/O pins
Software
–
Host-side library
Please read the Important Notice and Warnings at the end of this document
page 1 of 24
www.infineon.com
2021-12-12
Revision 1.1
OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Table of contents
Table of contents
Description .................................................................................................................................... 1
Features ........................................................................................................................................ 1
Table of contents............................................................................................................................ 2
1
Overview............................................................................................................................... 3
Product Description ................................................................................................................................3
Functional Overview ...............................................................................................................................3
Typical Application..................................................................................................................................3
1.1
1.2
1.3
2
3
Device Types/Order Information .............................................................................................. 6
Signals Description................................................................................................................. 7
4
4.1
4.2
Packing Specification ............................................................................................................. 9
Package Marking .....................................................................................................................................9
Emboss Carrier Tape .............................................................................................................................10
5
Electrical Characteristics .......................................................................................................13
Absolute Maximum Ratings ..................................................................................................................13
Operating Conditions............................................................................................................................14
I2C Interface Characteristics (Standard Mode) ....................................................................................14
I2C Interface Timing Characteristics (Standard Mode)........................................................................15
I2C Interface Characteristics (Fast Mode).............................................................................................16
I2C Interface Timing Characteristics (Fast Mode) ................................................................................17
SWI I/O Characteristics..........................................................................................................................18
SWI Timing Characteristics ...................................................................................................................18
Random Number Generation Time ......................................................................................................20
Host Authentication Response Computation Time .............................................................................21
ECC Authentication Response Computation Time ..............................................................................21
NVM Characteristics ..............................................................................................................................21
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
6
Appendix..............................................................................................................................22
Revision history.............................................................................................................................23
Short Data Sheet
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1
Overview
1.1
Product Description
Infineon Technologies’ novel OPTIGA™ Authenticate S Authentication chip offers a robust cryptographic
solution that assists OEMs and system manufacturers to ensure the authenticity and safety of their original
products, and protection of their investments against unauthorized after-market replacements.
It leverages Infineon’s market leading security know-how into the battery and accessory authentication
markets. With its innovative asymmetric cryptography approach, it significantly reduces system cost whilst
making a leap in security.
1.2
Functional Overview
OPTIGA™ Authenticate S is designed to be used as a companion authentication device. This authentication
device resides away from the host system such that the host system is able to check if it is communicating with
an authenticated original device.
OPTIGA™ Authenticate S supports a configurable I2C interface and SWI interface to communicate with the Host
controller. It is designed to conform to the I2C- bus specification and the Infineon SWI Bus Interface
specification. The configuration of the interface link for the OPTIGA™ Authenticate S can be configured in the
application board.
1.3
Typical Application
OPTIGA™ Authenticate S can be integrated into a host system supporting I2C interface as shown in Figure 1. It
operates as an I2C slave device supporting 100 kHz and 400 kHz operating frequency. Depending on the
selected frequency, the appropriate pull-up resistors need to be applied. I2C uses two wires to transmit data
synchronously. One of the wires (SCL) carries the clock signal that is controlled by the I2C master and the other
wire (SDA) is used to send and receive data. I2C is a widely used protocol and the transmission protocol is well-
defined and well supported by many hardware architectures [1].
Apart from I2C communication support, OPTIGA™ Authenticate S also supports the Infineon SWI protocol. It
requires only a single GPIO for input and output. A pull-up resistor, Rp, is required for the open-drain
configuration. OPTIGA™ Authenticate S provides a combination of secured authentication function and user
read/write storage space via a single serial interface (SWI). SWI is able to perform bidirectional communication
on multiple devices on the bus without extra hardware. Communication on the SWI is using half-duplex
transmission in which master and slave cannot transmit and receive commands concurrently. In the SWI
architecture, an SWI master initiates and controls all the SWI operations. The SWI bus operates in command
and response sequences. An additional feature of the SWI interface is the ability of interrupt-based processing
which allows for concurrent processing.
Below figures show examples of a host system connection to an OPTIGA™ Authenticate S device in I2C and SWI
configurations.
Please read the Important Notice and Warnings at the end of this document
www.infineon.com
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Overview
Figure 1
Application diagram of OPTIGA™ Authenticate S with I2C connectivity
Figure 2
Application diagram of OPTIGA™ Authenticate S with SWI connectivity (direct powered)
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Overview
In another typical application, OPTIGA™ Authenticate S can operate in indirect power mode where it is powered
up by the communication line and is maintained powered during the communication transaction through the
SWI communication. The resistor, RP, maintains the power supply with a voltage drop of RP multiplied by IP. The
voltage is fed to the OPTIGA™ Authenticate S’s single wire interface port and its power supply through a diode.
Figure 3
Application diagram of OPTIGA™ Authenticate S with SWI connectivity (Indirect powered)
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Device Types/Order Information
2
Device Types/Order Information
The OPTIGA™ Authenticate S is available in the following standard temperature range shown in Table 1 and
extended temperature range shown in Table 2.
Table 1
Device Configuration for standard temperature
Device Name
SLE95401
SLE95402
SLE95405
SLE95411
SLE95412
SLE95415
Package
Remarks
PG-TSNP-6-12
PG-TSNP-6-12
PG-TSNP-6-12
PG-TSNP-6-12
PG-TSNP-6-12
PG-TSNP-6-12
1Kbit User NVM
2Kbit User NVM
5Kbit User NVM
Host Authentication with 1Kbit User NVM
Host Authentication with 2Kbit User NVM
Host Authentication with 5Kbit User NVM
Table 2
Device Configuration for extended temperature
Device Name
SLE95401
SLE95402
SLE95405
SLE95411
SLE95412
SLE95415
Package
Remarks
PG-TSNP-6-12
PG-TSNP-6-12
PG-TSNP-6-12
PG-TSNP-6-12
PG-TSNP-6-12
PG-TSNP-6-12
1Kbit User NVM
2Kbit User NVM
5Kbit User NVM
Host Authentication with 1Kbit User NVM
Host Authentication with 2Kbit User NVM
Host Authentication with 5Kbit User NVM
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Signals Description
3
Signals Description
OPTIGA™ Authenticate S is delivered in a PG-TSNP-6-12 package.
Figure 4
Pin configuration of OPTIGA™ Authenticate S
Table 3
Pin No.
1
I/O Signals
Name
Pin Type
Buffer Type
Function
SDA/SWI
I/O
OD
Serial Data (I2C Configuration)
SWI
6
SCL/MCL
I
OD
PP
Serial Clock (I2C Configuration)
Must be connected to LOW (SWI
Configuration)
3
GPO
O
GPO
Table 4
Pin No.
2
Power Supply
Name
Pin Type
Buffer Type
Function
VCC
PWR
-
Positive Power Input for device
Table 5
Pin No.
4,5
Ground Pins
Name
Pin Type
Buffer Type
Function
VSS
PWR
-
GND Pin
This is the common ground of the IC. Pin 4
is the main ground of the package
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Signals Description
Table 6
PG-TSNP-6-12 Package Dimensions
Symbol Values
Parameter
Unit
Note or Test
Condition
Min
Typ
1.50
1.50
0.38
0.30
0.30
0.60
0.50
Max
1.55
1.55
0.40
0.35
0.35
A
B
1.45
1.45
0.35
0.25
0.25
mm
mm
mm
mm
mm
mm
mm
Package Width
Package Length
Package Height
AC
BC
Solder Pad Width
Solder Pad Length
Solder Pad Pitch - X
Solder Pad Pitch - Y
Figure 5
Package Dimensions
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Packing Specification
4
Packing Specification
4.1
Package Marking
Figure 6
PG-TSNP-6-12 package marking and dimensions
Pin 1 Marking
"W"
Y
Z
4
5
6
7
a
b
c
d
e
f
g
h
j
Week
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
"W"
A
B
C
D
E
Week
1
2
3
4
5
6
7
8
F
"Y"
8
9
0
1
2
3
4
5
6
7
8
9
Year
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
G
H
J
K
L
N
P
Q
R
S
T
U
V
"W"
r
s
t
u
v
x
y
z
8
9
2
3
Week
41
42
43
44
45
46
47
48
49
50
51
52
9
10
11
12
13
14
15
16
17
18
19
20
k
l
n
p
q
0
X
Figure 7
Package laser marking
P refers to product number and CC refers to delivered customer code. S refers to sample code. YW refers to date
code. The date code can be decoded using the supplied table.
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Packing Specification
4.2
Emboss Carrier Tape
Each box contains a single reel with 5000 pieces. Reel diameter is 180 mm.
Figure 8
7-inch carrier tape specification
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Packing Specification
Figure 9
Box specification
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Packing Specification
Figure 10 7-inch reel specification
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Electrical Characteristics
5
Electrical Characteristics
5.1
Absolute Maximum Ratings
Stresses above the maximum values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
Table 7
Absolute Maximum Ratings
Values
Parameter Symbol
Unit Note / Test Condition
Min.
-0.3
-0.3
-0.3
Typ.
Max.
6.0
VCC
VSCL
VSDA
VCC Supply Voltage
SCL Voltage
–
–
-
V
V
V
6.0
SDA Voltage
6.0
According to JS-001-
2012
According to JS-002-
2018
According to EIA/
JESD78
VESD,HBM
VESD,CDM
ILU
ESD robustness HBM
ESD robustness CDM
Latch up
2000
500
100
-55
V
V
mA
Storage Temperature
TSTORE
150
°C
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Electrical Characteristics
5.2
Operating Conditions
Within the operational range, the IC operates as explained in the product description.
Typical Values: VCC=3.8V, TAMB=25 °C
Table 8
Operating Conditions
Values
Typ.
Parameter
Symbol
Unit Note / Test Condition
Min.
Max.
Measurement is at the
VCC pin. Ramp up of
VCC shall be slower
VCC
VCC supply voltage range
1.8
3.8
5.5
V
than 1s
VSCL
VSDA
SCL voltage range
SDA voltage range
Current consumption, active idle
mode
-0.3
-0.3
5.5
5.5
V
V
For I2C interface only
For I2C interface only
Idle Function Mode
Averaged over 1s
Averaged over
IVCC, Active-Idle
IVCC, Active-ECC
0.38
1.2
mA
mA
Current consumption, active
mode, authentication operation
Current consumption, active
mode, host authentication
operation
Authentication
Averaged over
Authentication
IVCC, Active-HA
1.2
1.0
mA
SDA is set at 0V
Maximum value
condition is set at VCC
4.35V @ 85 °C
Current consumption, power-
down mode
IVCC,PD
A
=
TAMB
Ambient temperature
Ambient temperature
-40
-40
25
25
85
110
°C
°C
TAMB,110
NVM Write Operation is
°C prohibited above
TAMB,120
Ambient temperature
-40
25
120
110°C
Power-down low time
Power-up delay
Power-up delay
Soft reset delay
tPDL
tPUD
tPUD
tSRD
225.0
s
ms
10.0
5.0
1.0
ms From 0 °C to 40 °C
ms
5.3
I2C Interface Characteristics (Standard Mode)
The table below defines the Standard Mode operation of the I2C interface. The I2C interface characteristics
have been extracted from the I2C-bus specification.
Table 9
I2C Interface Characteristics (Standard Mode)
Values
Typ.
Parameter
Symbol
Unit Note / Test Condition
Min.
-0.3
0.7*VCC
Max.
Low-Level input voltage
High-Level input voltage
VIL
VIH
0.3*VCC
V
V
1)
Open Drain or Open
Collector at 3mA sink
current; Vcc > Vcc(min)
Low-Level output voltage 1
VOL,1
0.4
V
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Electrical Characteristics
Values
Typ.
Parameter
Symbol
IOL
Unit Note / Test Condition
Min.
3.0
Max.
Low-Level output current
Output fall time from VIH(MIN) to
VIL(MAX)
mA VOL = 0.4V
ns
tOF
2502)
Input current for SDA/SCL pin
Capacitance for SDA/SCL pin
II
-10.0
10
10
µA 0.1VCC < VI < 0.9VCC(MAX)
pF
CI3)
1) Maximum VIH=VCC(MAX) + 0.5V or 5.5V whichever is lower
2) The maximum tF for the SDA and SCL bus lines quoted in the below table (300ns) is longer than the
specified maximum tOF for the output stages (250ns). This allows a series protection resistor to be
connected between SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified
tF.
3) Special purpose devices such as multiplexers and switches may exceed this capacitance because they
connect multiple paths together
5.4
I2C Interface Timing Characteristics (Standard Mode)
The table below defines the interface timing characteristics for Standard Mode operation of the I2C interface.
These have been extracted from the I2C-bus specification.
Table 10
I2C Interface Timing Characteristics (Standard Mode)
Values
Typ.
Parameter
Symbol
Unit Note / Test Condition
Min.
Max.
SCL Clock Frequency
fSCL
0.0
100.00
kHz
After this period, the
µs first clock pulse is
Hold time (repeated) START
condition
tHD,STA
4.0
generated
Low Period for SCL
High Period for SCL
tLOW
tHIGH
4.7
4.0
µs
µs
Setup Time for a repeated START
Condition
tSU,STA
4.7
µs
Data Hold Time
Data Setup Time
tHD,DAT
tSU,DAT
tR
tF
tSU,STO
0.0
250.0
µs
ns
Rise time for SCL or SDA
Fall time for SCL or SDA
Setup time for STOP Condition
Bus Free Time between STOP
and START Condition
Capacitance load for each bus
line
1000
300
ns Applicable to Master
ns
µs
4.0
4.7
tBUF
Cb
µs
pF
400.0
Data valid time
Data valid acknowledge time
tVD;DAT
tVD;ACK
3.452)
3.452)
µs
µs
For each connected
device (including
hysteresis)
Noise margin at the LOW level
VnL
0.1*VCC
V
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Electrical Characteristics
Values
Typ.
Parameter
Symbol
Unit Note / Test Condition
Min.
Max.
For each connected
Noise margin at the HIGH level
VnH
0.2*VCC
V
device (including
hysteresis)
1) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
2) The maximum tHD;DAT could be 3.45 us for Standard-mode, but must be less than the maximum of tVD;DAT
or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW
period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid before it releases
the clock.
5.5
I2C Interface Characteristics (Fast Mode)
The table below defines the Fast Mode operation of the I2C interface. The I2C interface characteristics have
been extracted from the I2C-bus specification.
Table 11
I2C Interface Characteristics (Fast Mode)
Values
Typ.
Parameter
Symbol
Min.
Unit Note / Test Condition
Max.
Low-Level input voltage
High-Level input voltage
Hysteresis of Schmitt trigger
inputs
VIL
VIH
-0.3
0.7*VCC
0.3*VCC
V
V
1)
VHYS
0.05*VCC
V
Open Drain or Open
Low-Level output voltage 1
VOL,1
0.0
0.4
V
V
Collector at 3mA sink
current; Vcc > Vcc(min)
Open Drain or
Open Collector at
2mA sink current2);
VCC<=VCC(MIN)
Low-Level output voltage 2
Low-Level output current
VOL,2
0.0
0.2*VCC
3.0
6.0
mA VOL = 0.4V
IOL
tOF
tSP
mA VOL = 0.6V 3)
Output fall time from VIH(MIN) to
VIL(MAX)
Pulse width of spikes that must
be suppressed by the input filter
20*(VCC/
2505)
506)
ns
5.5V)4)
ns
0.1*VCC < VI <
0.9*VCC(MAX). If VCC is
Input current for SDA/SCL pin
Capacitance for SDA/SCL pin
II
-10.0
10
10
µA switched off, I/O pins
must not obstruct the
SDA and SCL lines.
pF
CI
1) Maximum VIH=VCC(MAX) + 0.5V or 5.5V whichever is lower
2) The same resistor value to drive 3mA at 3.0V VCC provides the same RC time constant when using < 2V
VCC with a smaller currentdraw.
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Electrical Characteristics
3) In order to drive full bus load at 400kHz, 6mA IOL is required at 0.6V VOL. Parts not meeting this
specification can still function, but not at 400kHz and 400pF.
4) Necessary to be backwards compatible with Fast-Mode. For Fast-Mode Only.
5) The maximum tf for the SDA and SCL bus lines quoted in the below table (300ns) is longer than the
specified maximum tOF for the output stages (250ns). This allows a series protection resistor to be
connected between SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified
tF.
6) Special purpose devices such as multiplexers and switches may exceed this capacitance because they
connect multiple paths together
5.6
I2C Interface Timing Characteristics (Fast Mode)
The table below defines the interface timing characteristics for Fast Mode operation of the I2C interface. These
have been extracted from the I2C-bus specification.
Table 12
I2C Interface Timing Characteristics (Fast Mode)
Values
Typ.
Parameter
Symbol
Unit Note / Test Condition
Min.
Max.
SCL clock frequency
fSCL
0.0
400.00
kHz
After this period, the
µs first clock pulse is
Hold time (repeated) START
condition
tHD,STA
0.6
generated
Low period for SCL
High period for SCL
Setup time for a repeated START
Condition
Data hold time
Data setup time
tLOW
tHIGH
1.3
0.6
µs
µs
tSU,STA
0.6
µs
tHD,DAT
tSU,DAT
tR
0.01)
100.03)
20.0
20*(VCC/
5.5V)
0.6
µs
ns
Rise time for SCL or SDA
330.00
300.00
ns Applicable to Master
Fall time for SCL or SDA
tF
ns
µs
µs
Setup time for STOP Condition
Bus free time between STOP and
START conditions
tSU,STO
tBUF
1.3
Capacitance load for each bus
line
Data valid time
Cb
400.0
pF
tVD;DAT
tVD;ACK
0.92)
0.92)
µs
µs
Data valid acknowledge time
For each connected
device (including
hysteresis)
For each connected
device (including
hysteresis)
Noise margin at the LOW level
Noise margin at the HIGH level
VnL
VnH
0.1*VCC
0.2*VCC
V
V
1) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
2) The maximum tHD;DAT could be 0.9us for Fast-mode, but must be less than the maximum of tVD;DAT or tVD;ACK
by a transition time. This maximum must only be met if the device does not stretch the LOW period
(tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid before it releases the clock.
Short Data Sheet
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OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Electrical Characteristics
3) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT
250ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output
the next data bit to the SDA line tr(MAX) + tSU;DAT = 1000 acknowledge timing.
5.7
SWI I/O Characteristics
Table 13
SWI I/O Characteristics
Symbol
Values
Typ.
Parameter
Unit Note / Test Condition
Min.
Max.
VSWI should be lower
than VCC
VSWI,IH
VSWI,IL
SWI input high voltage
SWI input low voltage
1.2
V
0.8
V
No indirect powering,
measured at 1.0µA.
For Master Only
VSWI,OH
SWI output high voltage
1.30
V
VSWI,OL
CSWI,L
SWI output low voltage
SWI bus load
0.1
250
V
pF
Measured at 1mA
5.8
SWI Timing Characteristics
Table 14
SWI Timing Characteristics
Symbol
Values
Typ.
Parameter
Unit Note / Test Condition
Min.
Max.
Basic Timing Parameters
tSWI
fSWI
Time base
1.0
10.0
50
µs
Bus frequency
Peak data rate
Bus rise time
500.0 kHz 50% Zero, 50% One
500
200
200
kBit/s
tr
tf
ns
Bus fall time
ns
Transmit Timing Parameters
Duration for 0B
Duration for 1B
Duration for STOP
Receive Timing Parameters
Duration for 0B
tTO
tT1
tTS
tSWI
tSWI
tSWI
0.75
2.75
6.00
1.25
3.25
tRO
tR1
tRS
tSWI
tSWI
tSWI
0.6
2.6
4.5
1.0
3.0
1.4
3.4
Duration for 1B
Duration for STOP
Interrupt Timing Parameters
Interrupt arming time
tARM
tINT
tSWI
tSWI
4.75
0.75
Drive period for all
Slaves
Interrupt active time
1
1.25
Short Data Sheet
page 18 of 24
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Revision 1.1
OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Electrical Characteristics
Values
Typ.
Parameter
Symbol
Unit Note / Test Condition
Min.
Max.
Drive period for all
Slaves
tTRAIL
tSWI
Interrupt trailing time
3.25
Bus Time-Out Parameters
Please take note for
Time Base, tSWI equal
to 1µs.
Please take note for
Time Base, tSWI equal
to 2µs.
Please take note for
Time Base, tSWI equal
to 3µs.
Please take note for
Time Base, tSWI equal
to above 3µs.
Please take note for
Time Base, tSWI equal
to above 5µs.
tTOUT
tTOUT
tTOUT
tTOUT
tTOUT
tSWI
tSWI
tSWI
tSWI
tSWI
Bus Time-Out Period
44.0
22.0
14.0
12.0
10.0
Bus Time-Out Period
Bus Time-Out Period
Bus Time-Out Period
Bus Time-Out Period
Power and Reset Control Timing Parameters
tPDL
Communication Low Time
225.0
µs
Table 15
GPO
Values
Typ.
Parameter
Symbol
Unit Note / Test Condition
Min.
Max.
GPO output high Voltage
GPO output low Voltage
GPO internal pull-up resistance
GPO internal pull-down resistance
VGPO,OH
VGPO,OL
RPU(INT)
Rpd(INT)
VGPO-0.7
V
V
kΩ
kΩ
Measured at 1mA
Measured at 1mA
0.1
150
150
50
50
100
100
10%/90% VCC,
CLOAD=25pF
VCC=3.8V, CLOAD
25pF, 10%/90% of VCC
VCC=3.8V, CLOAD
25pF, 10%/90% of VCC
GPO frequency
GPO rise time
fGPO
1
MHz
ns
=
tGPO,r
15
=
GPO fall time
tGPO.f
15
25
ns
pF
GPO load capacitance
CLOAD
Short Data Sheet
page 19 of 24
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Revision 1.1
OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Electrical Characteristics
5.9
Random Number Generation Time
Table 16
Random Number Generation Time
Values
Typ.
Parameter
Symbol
Unit Note / Test Condition
Min.
Max.
Random number generation time
TRNG
55.0
60.0
µs
Short Data Sheet
page 20 of 24
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Revision 1.1
OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Electrical Characteristics
5.10
Host Authentication Response Computation Time
Table 17
Host Authentication Response Computation Time
Values
Typ.
Parameter
Symbol
Unit Note / Test Condition
Min.
Max.
Host Authentication Computation
Time
T1)
3.30
ms
HA
1) Min. value here refers to the host needing to wait at least max (THA) before accessing the device for the
response value. Max value here is optional (theoretically, the host can wait as long as it requires before
reading back the response value) but this is provided for the host opting to time-out the readback
process as a sign for abnormal activity.
5.11
ECC Authentication Response Computation Time
Table 18
ECC Authentication Response Computation Time
Values
Parameter
Symbol
Unit Note / Test Condition
ms
Min.
Typ.
Max.
Response Computation Time
ECCE-163
T1)
60.0
ECCE163
1) Min. value here refers to the host needing to wait at least max (TECCS163) before accessing the device for
the response value. Max value here is optional (theoretically, the host can wait as long as it requires
before reading back the response value) but this is provided for the host opting to time-out the
readback process as a sign for abnormal activity.
5.12
NVM Characteristics
Table 19
NVM Characteristics
Values
Typ.
Note /
Test Condition
500,000 Cycles 25°C
Parameter
Symbol
Unit
Min.
Max.
NCYC
Tretent
tPROG
NVM endurance
NVM retention
NVM programming time
NVM programming time for
MACCRx command
10
5.1
years 25°C
ms 25°C
4.59
tPROG, MACCRx
12.5
ms
Short Data Sheet
page 21 of 24
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Revision 1.1
OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Appendix
6
Appendix
[1] UM10204, I2C-Bus Specification and User Manual, NXP Semiconductors, Rev 6.00, 04 April 2014
Short Data Sheet
page 22 of 24
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Revision 1.1
OPTIGA™ Authenticate S Short Data Sheet
OPTIGA™ Authenticate Family
Revision history
Revision history
Document
version
Date of release
Description of changes
1.0
1.1
2021-02-24
2021-12-12
Initial Public Version (preliminary).
Product name renamed from Authenticate IDoT to Authenticate S
Updated Electrical Characteristics and minor typos
Short Data Sheet
page 23 of 24
2021-12-12
Revision 1.1
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