OPTIGA TPM SLB 9673 FW26 [INFINEON]

OPTIGA™ TPM SLB 9673 FW26.xx is the latest addition to the OPTIGA™ TPM family targeted at connected devices that require enhanced security features.;
OPTIGA TPM SLB 9673 FW26
型号: OPTIGA TPM SLB 9673 FW26
厂家: Infineon    Infineon
描述:

OPTIGA™ TPM SLB 9673 FW26.xx is the latest addition to the OPTIGA™ TPM family targeted at connected devices that require enhanced security features.

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OPTIGA™ TPM  
SLB 9673 TPM2.0  
Data Sheet  
Devices  
SLB 9673XU2.0 FW26.xx  
SLB 9673AU2.0 FW26.xx  
Key features  
Optimized TPM device for IoT and ICT applications  
Compliant to TPM Main Specification, Family "2.0", Level 00, Revision 01.59  
Certifications:  
CC, Version 3.1 Rev.5, level EAL4+, AVA_VAN.4 (moderate) according to TCG PC Client TPM Protection  
Profile (targeted)  
FIPS 140-2 level 2 (physical security level 3) (targeted)  
I2C interface  
Random Number Generator (RNG) implemented according to NIST SP800-90A using entropy source  
according to NIST SP800-90B  
Full personalization with 4 Endorsement Keys (EK) and 4 EK certificates (RSA 2048, RSA3072, ECC NIST P256,  
ECC NIST P384)  
Standard temperature range (-40°C .. +85°C) or enhanced temperature range (-40°C .. +105°C)  
PG-UQFN-32-1,-2 package  
Optimized for battery operated devices: low standby power consumption (typ. 120 µA)  
24 PCRs (SHA-1, SHA-256 or SHA384)  
51 kByte NV memory  
Unlimited amount of NV counters (only depending on NV memory utilization)  
Up to 3 loaded sessions (TPM_PT_HR_LOADED_MIN)  
Up to 64 active sessions (TPM_PT_ACTIVE_SESSIONS_MAX)  
Up to 3 loaded transient Objects (TPM_PT_HR_TRANSIENT_MIN)  
Up to 7 loaded persistent Objects (TPM_PT_HR_PERSISTENT_MIN)  
Pre-generation of up to 7 RSA key pairs  
RSA key generation (1024, 2048, 3072 and 4096 bit)  
ECC (NIST P256, BN P256, NIST P384)  
SHA1, SHA256, SHA384  
Data Sheet  
www.infineon.com  
Please read the Important Notice and Warnings at the end of this document  
Revision 1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
About this document  
Scope and purpose  
This data sheet describes the OPTIGA™ TPM SLB 9673 FW26.xx Trusted Platform Module together with its  
features, functionality and programming interface.  
Intended audience  
This data sheet is primarily intended for system developers.  
Data Sheet  
2
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Table of contents  
Table of contents  
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
1.1  
1.2  
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
2
Device types and ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
3.1  
Typical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
4
TPM properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
4.1  
TPM register polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
I2C Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
5.1  
5.2  
5.3  
5.4  
5.4.1  
5.5  
6
Package dimensions (UQFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Packing type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Chip marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
6.1  
6.2  
6.3  
Data Sheet  
3
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
List of figures  
List of figures  
Figure 1  
Figure 2  
Figure 3  
Figure 4  
Figure 5  
Figure 6  
Figure 7  
Pinout of the OPTIGA™ TPM SLB 9673 (PG-UQFN-32-1,-2 package, top view) . . . . . . . . . . . . . . . . . . . . 7  
Typical schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Package dimensions PG-UQFN-32-1,-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Tape & reel dimensions PG-UQFN-32-1,-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Recommended footprint PG-UQFN-32-1,-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Chip marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Data Sheet  
4
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
List of tables  
List of tables  
Table 1  
Table 2  
Table 3  
Table 4  
Table 5  
Table 6  
Table 7  
Table 8  
Table 9  
Table 10  
Table 11  
Table 12  
Table 13  
Table 14  
Table 15  
Table 16  
Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Not connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Infineon TPM property values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
DC characteristics of interface pins (SCL, SDA, TEST#, RST#, I2C_PIRQ#) . . . . . . . . . . . . . . . . . . . . . . 12  
DC characteristics of GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
I2C Standard Mode Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
I2C Fast Mode Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
I2C Fast Mode plus Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Data Sheet  
5
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Overview  
1
Overview  
The OPTIGA™ TPM SLB 9673 is a Trusted Platform Module. It is available in PG-UQFN-32-1,-2 package. It supports  
an I2C interface with a transfer rate of up to 1 MHz. The OPTIGA™ TPM SLB 9673 is a TPM based on TCG family 2.0  
specifications (see [1] and [2]).  
This TPM product is targeted to be certified, using the Common Criteria for Information Technology Security  
Evaluation (CC), Version 3.1 Rev.5, in the level EAL4+, AVA_VAN.4 (moderate), ALC_FLR.1 according to the  
Protection Profile PC Client Specific TPM, TPM Library Specification Family "2.0" Level 0 Revision 1.59  
(CERTIFICATE <tbd>1)).  
1.1  
Power management  
In the OPTIGA™ TPM SLB 9673, power management is handled internally; no explicit power-down or standby  
mode is available. The device automatically enters a low-power state after each successful command/response  
transaction. If a transaction is started on the I2C bus from the host platform, the device will wake immediately  
and will return to the low-power mode after the transaction has been finished.  
1.2  
Device address  
The I2C interface uses 7-bit addressing. The default address of the device is 0x2E (also see [2]).  
2
Device types and ordering information  
The OPTIGA™ TPM SLB 9673 product family features devices using an UQFN package. Table 1 shows the available  
versions.  
Table 1  
Device configuration  
Device Name  
Package  
Remarks  
SLB 9673XU2.0 FW26.xx  
SLB 9673AU2.0 FW26.xx  
PG-UQFN-32-1,-2  
PG-UQFN-32-1,-2  
Standard temperature range -40°C - 85°C  
Enhanced temperature range -40°C - 105°C  
1) Exact reference not yet available at document generation time  
Data Sheet  
6
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Pin description  
3
Pin description  
30  
26  
1
VDD  
GND  
NC  
GND  
VDD  
22  
18  
GPIO_00  
GPIO_01  
NCI  
TPM  
SLB 9673AU2.0  
NC  
TEST#  
NC  
NC  
PG-UQFN-32-1,-2  
7
GPIO_02  
NCI/VDD  
I2C_PIRQ#  
RST#  
10  
15  
Figure 1  
Pinout of the OPTIGA™ TPM SLB 9673 (PG-UQFN-32-1,-2 package, top view)  
Table 2  
Buffer types  
Buffer type  
Description  
TS  
ST  
OD  
Tri-state pin  
Schmitt-trigger pin  
Open-drain pin  
Table 3  
I/O Signals  
Pin number  
PG-UQFN-32-1,-2  
30  
Name  
Pin  
type  
Buffer Function  
type  
SCL  
SDA  
I
ST  
TS  
OD  
I2C bus clock signal  
The clock signal of the I2C bus.  
29  
18  
I/O  
I2C bus data signal  
The data signal of the I2C bus.  
I2C_PIRQ# O  
Interrupt signal  
This pin can be connected to the host interrupt controller to  
allow interrupt driven reads of the response data instead of  
polling. As soon as a response is available, the signal is  
asserted (low) and remains active until the complete  
response is read by the host.  
17  
RST#  
I
ST  
Reset  
External reset signal. Asserting this pin unconditionally  
resets the device. The signal is active low.  
This pin has a weak internal pull-up resistor.  
Data Sheet  
7
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Pin description  
Table 3  
I/O Signals (continued)  
Pin number  
PG-UQFN-32-1,-2  
20  
Name  
Pin  
type  
Buffer Function  
type  
TEST#  
I
ST  
TS  
TS  
TS  
Test  
Test signal, must be externally connected to a static high  
level.  
3
4
7
GPIO_00 I/O  
GPIO_01 I/O  
GPIO_02 I/O  
General purpose IO  
This pin may be left unconnected; it has an internal pull-up  
resistor. It can be controlled via TPM NV GPIO functionality.  
General purpose IO  
This pin may be left unconnected; it has an internal pull-up  
resistor. It can be controlled via TPM NV GPIO functionality.  
General purpose IO  
This pin may be left unconnected; it has an internal pull-up  
resistor. It can be controlled via TPM NV GPIO functionality.  
Table 4  
Power supply  
Pin number  
PG-UQFN-32-1,-2  
1, 14, 22  
Name  
Pin  
type  
Buffer  
type  
Function  
VDD  
PWR  
Power supply  
All VDD pins must be connected externally and should be  
bypassed to GND via 100 nF capacitors.  
2, 9, 23, 32  
GND  
GND  
Ground  
All GND pins must be connected externally.  
Table 5  
Not connected  
Name  
Pin number  
Pin  
type  
Buffer  
type  
Function  
PG-UQFN-32-1,-2  
6, 19, 21, 24  
NC  
NU  
No connect  
All pins must not be connected externally (must be left  
floating).  
5, 10 - 13, 15,  
25 - 28, 31  
NCI  
Not connected internally  
All pins are not connected internally (can be connected  
externally).  
8
NCI/VDD  
Not connected internally/VDD  
This pin is not connected internally (can be connected  
externally).  
Note that pin 8 is defined as VDD in the TCG specification  
[2]. To be compliant, VDD can be connected to this pin.  
16  
NCI/GND  
Not connected internally/GND  
This pin is not connected internally (can be connected  
externally).  
Note that pin 16 is defined as GND in the TCG specification  
[2]. To be compliant, GND can be connected to this pins.  
Data Sheet  
8
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Pin description  
3.1  
Typical schematic  
Figure 2 shows the typical schematic for the OPTIGA™ TPM SLB 9673. The power supply pins should be bypassed  
to GND with capacitors located close to the device.  
3.3V (1.8V)  
* Pull-up resistors are  
needed on I2C bus  
RPU  
*
3.3V (1.8V)  
SCL  
SDA  
SCL  
VDD  
SDA  
RST#  
1 μF  
RESET#  
GND  
2x 100 nF (place close to  
device VDD/GND pins)  
I2C_PIRQ#  
I2C_PIRQ#  
TEST#  
GPIO_00  
GPIO_01  
GPIO_02  
NC/NCI  
SLB 9673  
Figure 2  
Typical schematic  
Data Sheet  
9
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
TPM properties  
4
TPM properties  
Properties defined within the TPM can be read with the command TPM2_GetCapability. The values are vendor  
dependent or determined by a platform-specific specification. The following properties are returned by the  
Infineon  
OPTIGA™ TPM SLB 9673  
using  
the  
command  
TPM2_GetCapability  
(capability =  
TPM_CAP_TPM_PROPERTIES):  
Table 6  
Infineon TPM property values  
TPM_PT_MANUFACTURER  
TPM_PT_VENDOR_STRING_1  
TPM_PT_VENDOR_STRING_2  
TPM_PT_VENDOR_STRING_3  
TPM_PT_VENDOR_STRING_4  
TPM_PT_FIRMWARE_VERSION_1  
“IFX”  
“SLB9”  
“673”  
NULL  
NULL  
Major and minor version (for instance, 0x001A000A  
indicates V26.10)1)  
TPM_PT_FIRMWARE_VERSION_2  
Build number and Common Criteria certification state (for  
instance, 0x00413000 or 0x00413002)1)  
Byte 1: reserved for future use (0x00)  
Byte 2 and 3: Build number (for instance, 0x4130)1)  
Byte 4: Common Criteria certification state/mode:  
0x00 = TPM operational mode/TPM is CC certified  
0x02 = TPM operational mode/TPM is not certified  
0x60 = Manually entered TPM firmware recovery mode  
(triggered externally for testing purposes)  
0x61 = TPM firmware recovery mode (triggered by code  
integrity failure detection)  
0x62 = TPM firmware update mode  
TPM_PT_MODES  
Bit 0 (FIPS_140_2) = 1  
Bits 1..31 = 0  
1) The build- and version numbers given here are examples and do not necessarily match the numbers of the device this  
data sheet has been provided for.  
4.1  
TPM register polling  
Processing of accesses to registers creates a load on the TPM.  
If registers are polled in quick succession, the time until the TPM reaches the target state is increased, which  
decreases performance and may even lead to violation of maximum timeout values.  
To prevent this, a minimum delay between register read accesses must be respected when polling:  
Minimum delay between TPM register reads for polling of TPM_STS_x during command execution: 1 ms  
Minimum delay between TPM register reads for polling of TPM_STS_x after device reset before  
commandReady set: 1 ms  
Minimum delay between TPM register reads for all other TPM register polling, including  
TPM_STS_x.commandReady set between command, TPM_STS_x.valid and TPM_STS_x.burstCount: 100 µs  
Data Sheet  
10  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Electrical characteristics  
5
Electrical characteristics  
This chapter lists the maximum and operating ranges for various electrical and timing parameters.  
5.1  
Absolute maximum ratings  
Table 7  
Absolute maximum ratings  
Symbol  
Parameter  
Values  
Min. Typ. Max.  
Unit  
Note or Test Condition  
Supply Voltage  
VDD  
Vmax  
TA  
-0.3  
-0.5  
-40  
4.1  
4.1  
85  
V
Voltage on any pin  
Ambient temperature  
V
°C  
Standard temperature  
SLB 9673XU2.0 devices  
Ambient temperature  
Storage temperature  
TA  
-40  
105  
°C  
Enhanced temperature  
SLB 9673AU2.0 devices  
TS  
-40  
125  
°C  
V
ESD robustness HBM:  
VESD,HBM  
2000  
According to EIA/JESD22-A114-B  
1.5 kΩ, 100 pF  
ESD robustness  
VESD,CDM  
500  
100  
V
According to ESD Association  
Standard STM5.3.1 - 1999  
Latchup immunity  
Ilatch  
mA  
According to EIA/JESD78  
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure  
to absolute maximum rating conditions for extended periods may affect device reliability.  
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible  
damage to the integrated circuit.  
5.2  
Functional operating range  
Table 8  
Functional operating range  
Symbol  
Parameter  
Values  
Min. Typ. Max.  
Unit  
Note or Test Condition  
Supply Voltage  
VDD  
3.0  
3.3  
1.8  
3.6  
1.95  
85  
V
1.65  
-40  
V
Ambient temperature  
Ambient temperature  
TA  
TA  
°C  
Standard temperature  
SLB 9673XU2.0 devices  
-40  
105  
°C  
Enhanced temperature  
SLB 9673AU2.0 devices  
Useful lifetime  
10  
10  
y
Operating lifetime  
Average TA over lifetime  
y
55  
°C  
Data Sheet  
11  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Electrical characteristics  
5.3  
DC characteristics  
TA = 25°C, VDD = 3.3 V ± 0.3 V or VDD = 1.8 V ± 0.15 V unless otherwise noted.  
Table 9  
Current consumption  
Symbol  
Parameter  
Values  
Min. Typ. Max.  
35  
Unit  
Note or Test Condition  
Current Consumption in IVDD_Active  
Active Mode  
mA  
µA  
Current Consumption in IVDD_Sleep  
Sleep Mode  
120  
Pins GPIO, RST# and  
I2C_PIRQ# = VDD, no I2C bus  
activity  
Note:  
Note:  
Current consumption does not include any currents flowing through resistive loads on output pins!  
Device sleep mode will be entered after 50 milliseconds of inactivity after the last TPM command was  
executed.  
Table 10 DC characteristics of interface pins (SCL, SDA, TEST#, RST#, I2C_PIRQ#)  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or Test Condition  
Min.  
0.7 VDD  
-0.5  
Max.  
VDD+0.5  
0.3 VDD  
2
Input voltage high  
Input voltage low  
VIH  
V
VIL  
V
Input leakage current  
Output high voltage  
Output low voltage  
Pad input capacitance  
ILEAK  
VOH  
VOL  
CIN  
-2  
µA  
V
0 V < VIN < VDD  
IOH = -100 µA  
IOL = 1.5 mA  
0.9 VDD  
0.1 VDD  
10  
V
pF  
pF  
Output load capacitance CLOAD  
30  
Table 11 DC characteristics of GPIO pins  
Parameter  
Symbol  
Values  
Unit  
Note or Test Condition  
Min.  
0.7 VDD  
-0.5  
Typ. Max.  
VDD+0.3  
Input voltage high  
Input voltage low  
VIH  
V
Pins GPIO  
VIL  
0.3 VDD  
2
V
Pins GPIO  
Input leakage current  
Output high voltage  
Output low voltage  
Pad input capacitance  
ILEAK  
VOH  
VOL  
CIN  
-2  
µA  
V
0 V < VIN < VDD  
IOH = -1 mA, pins GPIO  
IOL = 1 mA, pins GPIO  
Pins GPIO  
VDD-0.3  
0.3  
10  
V
pF  
Data Sheet  
12  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Electrical characteristics  
5.4  
AC characteristics  
TA = 25°C, VDD = 3.3V ± 0.3V or VDD = 1.8V ± 0.15V unless otherwise noted.  
Table 12 Power supply  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or Test Condition  
Min.  
Max.  
Supply voltage rise time tVDDR  
1.0  
V/ns  
Table 13 Device reset  
Parameter  
Symbol  
Values  
Typ.  
Unit Note or Test Condition  
Min.  
80  
Max.  
Cold (Power-On) Reset  
Warm Reset  
tPOR  
µs  
µs  
tWRST  
2
tPOR  
VDD  
tWRST  
tWRST  
RST#  
RST_Timing.vsdx  
Figure 3  
Reset timing  
5.4.1  
I2C Interface Characteristics  
The electrical characteristics are compliant to the NXP I2C bus specification [1] for “standard-mode”  
(fSCL 100 kHz), “fast-mode” (fSCL 400 kHz) and “fast-mode plus” (fSCL 1000 kHz), with certain deviations  
stated in Table 14, Table 15, and Table 16 below.  
For printed circuit board design the reduced output fall time tOF compared to the NXP I2C bus specification needs  
to be considered!  
TA = 25°C, VDD = 3.3V ± 0.3V or VDD = 1.8V ± 0.15V unless otherwise noted.  
Table 14 I2C Standard Mode Interface Characteristics  
Parameter  
Symbol  
Values  
Typ.  
Unit  
Note or Test Condition  
Min.  
0
Max.  
100  
SCL clock frequency  
Input voltage low  
Input voltage high  
fSCL  
VIL  
kHz  
V
-0.5  
0.7 VDD  
0.3 VDD  
VIH  
VDD+0.5  
or  
V
Maximum = min(VDD+0.5, VDD,max)  
VDD,max  
Output low voltage  
VOL  
0.4  
V
IOL = 2 mA, VDD 2 V  
Data Sheet  
13  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Electrical characteristics  
Table 14 I2C Standard Mode Interface Characteristics (continued)  
Parameter  
Symbol  
Values  
Typ.  
Unit  
Note or Test Condition  
Min.  
Max.  
0.4  
Output low voltage  
VOL  
V
IOL = 3 mA, VDD > 2 V  
Low level output current IOL  
Low level output current IOL  
2
mA  
mA  
ns  
VOL = 0.4 V, VDD < 2.7 V  
VOL = 0.4 V, VDD 2.7 V  
Cb 200 pF, VDD < 2.7 V  
3
Output fall time from  
IHmin to VILmax (at device  
tOF  
250  
V
pin)  
Output fall time from  
VIHmin to VILmax (at device  
pin)  
tOF  
250  
ns  
Cb 400 pF, VDD 2.7 V  
Capacitive load for each Cb  
bus line  
200  
400  
pF  
pF  
VDD < 2.7 V  
VDD 2.7 V  
Capacitive load for each Cb  
bus line  
Table 15 I2C Fast Mode Interface Characteristics  
Parameter  
Symbol  
Values  
Typ.  
Unit  
Note or Test Condition  
Min.  
0
Max.  
400  
SCL clock frequency  
Input voltage low  
Input voltage high  
fSCL  
VIL  
kHz  
V
-0.5  
0.7 VDD  
0.3 VDD  
VIH  
VDD+0.5  
or  
V
Maximum = min(VDD+0.5, VDD,max)  
VDD,max  
Output low voltage  
Output low voltage  
VOL  
VOL  
2
0.4  
0.4  
V
IOL = 2 mA, VDD 2 V  
V
IOL = 3 mA, VDD > 2 V  
Low level output current IOL  
Low level output current IOL  
mA  
mA  
ns  
VOL = 0.4 V, VDD < 2.7 V  
VOL = 0.4 V, VDD 2.7 V  
Cb,min< Cb 200 pF, VDD < 2.7 V  
3
Output fall time from  
IHmin to VILmax (at device  
tOF  
20*VDD/ —  
5.5 V  
250  
V
pin)  
Output fall time from  
tOF  
20*VDD/ —  
5.5 V  
250  
ns  
Cb,min< Cb 400 pF, VDD 2.7 V  
V
IHmin to VILmax (at device  
pin)  
Capacitive load for each Cb  
bus line  
15  
15  
200  
400  
pF  
pF  
VDD < 2.7 V  
VDD 2.7 V  
Capacitive load for each Cb  
bus line  
Data Sheet  
14  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Electrical characteristics  
Table 16 I2C Fast Mode plus Interface Characteristics  
Parameter  
Symbol  
Values  
Typ.  
Unit  
Note or Test Condition  
Min.  
0
Max.  
1000  
SCL clock frequency  
Input voltage low  
Input voltage high  
fSCL  
VIL  
kHz  
V
-0.5  
0.7 VDD  
0.3 VDD  
VIH  
VDD+0.5  
or  
V
Maximum = min(VDD+0.5, VDD,max  
)
VDD,max  
Output low voltage  
Output low voltage  
VOL  
VOL  
2
0.4  
0.4  
V
IOL = 2 mA, VDD 2 V  
IOL = 3 mA, VDD > 2 V  
VOL = 0.4 V, VDD < 2.7 V  
VOL = 0.4 V, VDD 2.7 V  
Cb,min< Cb 150 pF  
V
Low level output current IOL  
Low level output current IOL  
mA  
mA  
ns  
3
Output fall time from  
VIHmin to VILmax (at device  
pin)  
tOF  
20*VDD/ —  
5.5 V  
120  
Capacitive load for each Cb  
15  
150  
pF  
bus line  
5.5  
Timing  
Some pads are disabled after deassertion of the reset signal for up to 500 µs.  
The OPTIGA™ TPM SLB 9673 features security mechanisms which detect and count all resets.  
Data Sheet  
15  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Package dimensions (UQFN)  
6
Package dimensions (UQFN)  
All dimensions are given in millimeters (mm) unless otherwise noted. The packages are “green” and RoHS  
compliant.  
Figure 4  
Package dimensions PG-UQFN-32-1,-2  
6.1  
Packing type  
PG-UQFN-32-1,-2: Tape & Reel (reel diameter 330mm), 5000 pcs. per reel  
8
PIN 1  
INDEX MARKING  
4
0.3  
5.25  
0.8  
ALL DIMENSIONS ARE IN UNITS MM  
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [  
]
Figure 5  
Tape & reel dimensions PG-UQFN-32-1,-2  
Data Sheet  
16  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Package dimensions (UQFN)  
6.2  
Recommended footprint  
Figure 6 shows the recommended footprint for the package. The exposed pad of the package is internally  
connected to GND. It shall be connected to GND externally as well.  
Figure 6  
Recommended footprint PG-UQFN-32-1,-2  
6.3  
Chip marking  
Line 1: SLB9673  
Line 2: XU20 yy or AU20 yy (see Table 1), the <yy> is an internal FW indication (only at manufacturing due to field  
upgrade option)  
Line 3: <Lot number> H <datecode>  
Infineon  
1234567  
AU20 YY  
Softwarecode  
XXH  
Lot Code  
ChipMarking_UQFN.vsd  
Figure 7  
Chip marking  
For details and recommendations regarding assembly of packages on PCBs, please refer to  
http://www.infineon.com/cms/en/product/technology/packages/  
Data Sheet  
17  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
References  
References  
[1] —, “Trusted Platform Module Library (Part 1-4)”, Family 2.0, Level 00, Rev. 01.59, November 8, 2019, TCG  
[2] —, “TCG PC Client Platform TPM Profile (PTP) Specification”, Family 2.0, Level 00, Rev. 01.05 v14,  
September 4, 2020, TCG  
[3] —, “Errata For TCG Trusted Platform Libary, Family 2.0, Level 00, Rev. 01.59, November 8, 2019”, Errata  
Version 1.1, June 18, 2020, TCG  
[4] —, “Errata for PC Client Platform TPM Profile for TPM 2.0 Version 1.05 Revision 14”, Errata Version 1.0,  
September 04, 2020, TCG  
[5] —, “Registry of reserved TPM 2.0 handles and localities”, Version 1.1, Rev. 1.00, February 6, 2019, TCG  
[6] —, “TCG EK Credential Profile”, Version 2.3, Rev. 2, July 23, 2020, TCG  
[7] —, "NIST Special Publication 800-193, Platform Firmware Resiliency Guidelines", May, 2018, NIST  
Data Sheet  
18  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Terminology  
Terminology  
ESW  
HMAC  
I2C  
Embedded Software  
Hashed Message Authentication Code  
Inter Integrated Circuit (bus)  
Information and Communications Technology  
Internet of Things  
ICT  
IoT  
PCR  
PUBEK  
SPI  
Platform Configuration Register  
Public Endorsement Key  
Serial Peripheral Interface (bus)  
Trusted Computing Group  
Trusted Platform Module  
TCG  
TPM  
TSS  
TCG Software Stack  
Data Sheet  
19  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Licenses and notices  
Licenses and notices  
The following license and notice statements are reproduced from [1].  
Licenses and Notices  
1. Copyright Licenses:  
Trusted Computing Group (TCG) grants to the user of the source code in this specification (the "Source Code") a  
worldwide, irrevocable, nonexclusive, royalty free, copyright license to reproduce, create derivative works,  
distribute, display and perform the Source Code and derivative works thereof, and to grant others the rights  
granted herein.The TCG grants to the user of the other parts of the specification (other than the Source Code) the  
rights to reproduce, distribute, display, and perform the specification solely for the purpose of developing  
products based on such documents.  
2. Source Code Distribution Conditions:  
Redistributions of Source Code must retain the above copyright licenses, this list of conditions and the following  
disclaimers.  
Redistributions in binary form must reproduce the above copyright licenses, this list of conditions and the  
following disclaimers in the documentation and/or other materials provided with the distribution.  
3. Disclaimers:  
THE COPYRIGHT LICENSES SET FORTH ABOVE DO NOT REPRESENT ANY FORM OF LICENSE OR WAIVER, EXPRESS  
OR IMPLIED, BY ESTOPPEL OR OTHERWISE, WITH RESPECT TO PATENT RIGHTS HELD BY TCG MEMBERS (OR  
OTHER THIRD PARTIES) THAT MAY BE NECESSARY TO IMPLEMENT THIS SPECIFICATION OR OTHERWISE. Contact  
TCG Administration (admin@trustedcomputinggroup.org) for information on specification licensing rights  
available through TCG membership agreements.  
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO EXPRESS OR IMPLIED WARRANTIES WHATSOEVER,  
INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ACCURACY,  
COMPLETENESS, OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS, OR ANY WARRANTY OTHERWISE  
ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.  
Without limitation, TCG and its members and licensors disclaim all liability, including liability for infringement of  
any proprietary rights, relating to use of information in this specification and to the implementation of this  
specification, and TCG disclaims all liability for cost of procurement of substitute goods or services, lost profits,  
loss of use, loss of data or any incidental, consequential, direct, indirect, or special damages, whether under  
contract, tort, warranty or otherwise, arising in any way out of use or reliance upon this specification or any  
information herein.  
Any marks and brands contained herein are the property of their respective owners.  
Data Sheet  
20  
Revision1.2  
2022-08-24  
OPTIGA™ TPM  
SLB 9673 TPM2.0  
Revision history  
Page or item  
Subjects (major changes since previous revision)  
Revision 1.2, 2022-08-24  
Fixed package designation in Figure 1.  
Revision 1.1, 2022-07-08  
Added Section 4.1  
Revision 1.0, 2022-05-25  
Initial version  
Data Sheet  
21  
Revision1.2  
2022-08-24  
Please read the Important Notice and Warnings at the end of this document  
Trademarks  
All referenced product or service names and trademarks are the property of their respective owners.  
IMPORTANT NOTICE  
The information given in this document shall in no For further information on technology, delivery terms  
Edition 2022-08-24  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest  
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Infineon Technologies Office (www.infineon.com).  
With respect to any examples, hints or any typical  
values stated herein and/or any information regarding  
the application of the product, Infineon Technologies  
hereby disclaims any and all warranties and liabilities  
of any kind, including without limitation warranties of  
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In addition, any information given in this document is  
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