IRFS7437TRL7PP_技术文档

StrongIRFET

IRFS7437-7PPbF

Applications

HEXFET^®Power MOSFET

l Brushed Motor drive applications

l BLDC Motor drive applications

l PWM Inverterized topologies

l Battery powered circuits

l Half-bridge and full-bridge topologies

l Electronic ballast applications

l Synchronous rectifier applications

l Resonant mode power supplies

l OR-ing and redundant power switches

l DC/DC and AC/DC converters

D

V_DSS

40V

R_DS(on)typ.

max.

1.1m

1.4m



G

I_D

295A

(Silicon Limited)

I_D

195A

S

(Package Limited)

D

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

l Fully Characterized Capacitance and Avalanche

S

SOA

S

l Enhanced body diode dV/dt and dI/dt Capability

l Lead-Free

G

D²Pak 7 Pin

l Halogen Free

G

D

S

Gate

Drain

Source

Ordering Information

Base Part Number

Package Type

Standard Pack

Form

Complete Part

Number

Quantity

Tube

Tape and Reel Left

50

800

IRFS7437-7PPbF

IRFS7437TRL7PP

IRFS7437-7PPbF

D2Pak-7PIN

4.0

3.0

2.0

1.0

300

250

200

150

100

50

I

= 100A

Limited By Package

D

T = 125°C

J

T

= 25°C

J

0

4

6

8

10 12 14

16 18 20

25

50

75

100

125

150

175

T

, Case Temperature (°C)

C

V

Gate -to -Source Voltage (V)

GS,

Fig 2. Maximum Drain Current vs. Case Temperature

Fig 1. Typical On-Resistance vs. Gate Voltage

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1

September 6, 2012

IRFS7437-7PPbF

Absolute Maximum Ratings

Symbol

Parameter

Max.

295

Units

I_D@ T_C= 25°C

I_D@ T_C= 100°C

I_D@ T_C= 25°C

I_DM

Continuous Drain Current, V_GS@ 10V (Silicon Limited)

Continuous Drain Current, V_GS@ 10V (Wire Bond Limited)

Pulsed Drain Current

208

A

195

1040

231

P_D@T_C= 25°C

Maximum Power Dissipation

W

1.5

Linear Derating Factor

W/°C

V

± 20

V_GS

Gate-to-Source Voltage

3.5

Peak Diode Recovery

dv/dt

T_J

V/ns

-55 to + 175

Operating Junction and

°C

T_STG

Storage Temperature Range

300

Soldering Temperature, for 10 seconds (1.6mm from case)

Mounting torque, 6-32 or M3 screw

10lbf in (1.1N m)

Avalanche Characteristics

E_{AS (Thermally limited)}

Single Pulse Avalanche Energy

344

508

mJ

E_{AS (tested)}

I_AR

Single Pulse Avalanche Energy Tested Value

Avalanche Current

See Fig. 14, 15, 22a, 22b

A

Repetitive Avalanche Energy

E_AR

mJ

Thermal Resistance

Symbol

Parameter

Typ.

–––

Max.

0.65

40

Units

°C/W

R_

Junction-to-Case

JC

Junction-to-Ambient (PCB Mount)

JA

Static @ T_J= 25°C (unless otherwise specified)

Symbol

Parameter

Min. Typ. Max. Units

Conditions

V_(BR)DSS

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

40

–––

V

V_GS= 0V, I_D= 250μA

V_(BR)DSS/T_J

R_DS(on)

––– 0.035 –––

V/°C Reference to 25°C, I_D= 1.0mA

m V_GS= 10V, I_D= 100A

m V_GS= 6.0V, I_D= 50A

–––

1.1

1.7

1.4

–––

3.9

V_GS(th)

I_DSS

Gate Threshold Voltage

2.2

–––

2.2

V

V_DS= V_GS, I_D= 150μA

Drain-to-Source Leakage Current

1.0

μA V_DS= 40V, V_GS= 0V

150

100

-100

–––

V

_DS= 40V, V_GS= 0V, T_J= 125°C

_GS= 20V

I_GSS

R_G

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Internal Gate Resistance

nA

V_GS= -20V



Notes:

Calculated continuous current based on maximum allowable junction

ꢀ Pulse width  400μs; duty cycle  2%.

C_osseff. (TR) is a fixed capacitance that gives the same charging time

as C_osswhile V_DSis rising from 0 to 80% V_DSS

C_osseff. (ER) is a fixed capacitance that gives the same energy as

C_osswhile V_DSis rising from 0 to 80% V_DSS

When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

R_is measured at T_Japproximately 90°C.

temperature. Bond wire current limit is 195A. Note that current

limitations arising from heating of the device leads may occur with

some lead mounting arrangements. (Refer to AN-1140)

Repetitive rating; pulse width limited by max. junction

temperature.

Limited by T_Jmax, starting T_J= 25°C, L = 0.069mH

R_G= 50, I_AS= 100A, V_GS=10V.

.

This value determined from sample failure population,

I_SD 100A, di/dt  1288A/μs, V_DDV_(BR)DSS, T_J 175°C.

starting T_J= 25°C, L= 0.069mH, R_G= 50, I_AS= 100A, V_GS=10V.

2

www.irf.com

September 6, 2012

IRFS7437-7PPbF

Dynamic @ T_J= 25°C (unless otherwise specified)

Symbol

Parameter

Min. Typ. Max. Units

Conditions

gfs

Q_g

Forward Transconductance

122

–––

150

41

–––

225

–––

S

V_DS= 10V, I_D= 100A

Total Gate Charge

nC I_D= 100A

V_DS= 20V

Q_gs

Q_gd

Gate-to-Source Charge

Gate-to-Drain ("Miller") Charge

Total Gate Charge Sync. (Q_g- Q_gd)

Turn-On Delay Time

51

V_GS= 10V

Q_sync

t_d(on)

t_r

99

I_D= 100A, V_DS=0V, V_GS= 10V

18

ns V_DD= 20V

I_D= 30A

Rise Time

62

t_d(off)

t_f

Turn-Off Delay Time

78

R_G= 2.7

V_GS= 10V

Fall Time

51

C_iss

C_oss

C_rss

Input Capacitance

7437

1097

748

1314

1735

pF V_GS= 0V

Output Capacitance

V

_DS= 25V

ƒ = 1.0 MHz

V_GS= 0V, V_DS= 0V to 32V

Reverse Transfer Capacitance

Effective Output Capacitance (Energy Related)

Effective Output Capacitance (Time Related)

C

_osseff. (ER)

C_osseff. (TR)

V_GS= 0V, V_DS= 0V to 32V

Diode Characteristics

Symbol

Parameter

Min. Typ. Max. Units

Conditions

D

S

I_S

Continuous Source Current

–––

––– 285

A

V

MOSFET symbol

(Body Diode)

Pulsed Source Current

showing the

integral reverse

G

I_SM

–––

1040

(Body Diode)

Diode Forward Voltage

Reverse Recovery Time

p-n junction diode.

T_J= 25°C, I_S= 100A, V_GS= 0V

V_SD

t_rr

–––

1.0

37

38

34

36

1.8

1.3

–––

ns T_J= 25°C

T_J= 125°C

V_R= 34V,

I_F= 100A

di/dt = 100A/μs

Q_rr

Reverse Recovery Charge

nC T_J= 25°C

T_J= 125°C

I_RRM

t_on

Reverse Recovery Current

Forward Turn-On Time

A

T_J= 25°C

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

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3

September 6, 2012

IRFS7437-7PPbF

10000

1000

100

VGS

15V

10V

8.0V

7.0V

6.5V

6.0V

5.5V

5.0V

VGS

15V

TOP

10V

8.0V

7.0V

6.5V

6.0V

5.5V

5.0V

1000

100

BOTTOM

5.0V

10

5.0V

60μs PULSE WIDTH

Tj = 25°C

60μs PULSE WIDTH



Tj = 175°C



1

10

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 3. Typical Output Characteristics

Fig 4. Typical Output Characteristics

10000

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

I

= 100A

= 10V

D

V

GS

1000

100

10

T = 175°C

J

T

V

= 25°C

= 10V

J

DS

60μs PULSE WIDTH

1.0

2

3

4

5

6

7

8

9

-60 -40 -20 0 20 40 60 80 100120140160180

, Junction Temperature (°C)

T

J

V

, Gate-to-Source Voltage (V)

GS

Fig 6. Normalized On-Resistance vs. Temperature

Fig 5. Typical Transfer Characteristics

100000

10000

1000

14.0

V

= 0V,

= C

f = 1 MHZ

GS

I = 100A

D

C

+ C , C

SHORTED

ds

iss

gs

gd

12.0

= C

rss

oss

gd

= C + C

V

= 32V

= 20V

DS

ds

gd

10.0

8.0

6.0

4.0

2.0

0.0

C

iss

C

oss

rss

100

1

10

, Drain-to-Source Voltage (V)

100

0

20 40 60 80 100 120 140 160 180 200

V

DS

Q , Total Gate Charge (nC)

G

Fig 7. Typical Capacitance vs. Drain-to-Source Voltage

Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage

4

www.irf.com

September 6, 2012

IRFS7437-7PPbF

10000

1000

100

10

10000

1000

100

10

OPERATION IN THIS AREA

LIMITED BY R (on)

DS

100μsec

1msec

T

= 175°C

J

10msec

Limited by

package

T

= 25°C

J

DC

1

Tc = 25°C

Tj = 175°C

Single Pulse

V

GS

= 0V

1.0

0.1

1

10

100

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

, Source-to-Drain Voltage (V)

V

, Drain-toSource Voltage (V)

V

DS

SD

Fig 10. Maximum Safe Operating Area

Fig 9. Typical Source-Drain Diode

Forward Voltage

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

-0.1

49

48

47

46

45

44

43

42

41

40

Id = 1.0mA

-5

0

5

10 15 20 25 30 35 40

Drain-to-Source Voltage (V)

-60 -40 -20 0 20 40 60 80 100120140160180

T

, Temperature ( °C )

J

V

DS,

Fig 11. Drain-to-Source Breakdown Voltage

Fig 12. Typical C_OSSStored Energy

10.0

V

= 6.0V

GS

8.0

6.0

4.0

2.0

0.0

= 7.0V

= 8.0V

=10V

GS

V

GS

V

GS

0

200

400

600

800 1000 1200

I , Drain Current (A)

D

Fig 13. Typical On-Resistance vs. Drain Current

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5

September 6, 2012

IRFS7437-7PPbF

1

D = 0.50

0.20

0.1

0.10

0.05

0.02

0.01

SINGLE PULSE

( THERMAL RESPONSE )

0.001

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0.0001

1E-006

1E-005

0.0001

0.001

0.01

0.1

1

t

, Rectangular Pulse Duration (sec)

1

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

100

10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming Tj = 150°C and

Tstart =25°C (Single Pulse)

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming  j = 25°C and

Tstart = 150°C.

1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current vs.Pulsewidth

350

300

250

200

150

100

50

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in

excess of T_jmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P_{D (ave)}= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

6. I_av= Allowable avalanche current.

7. T = Allowable rise in junction temperature, not to exceed T_jmax(assumed as

25°C in Figure 14, 15).

t_{av =}Average time in avalanche.

D = Duty cycle in avalanche = t_av·f

TOP

BOTTOM 1.0% Duty Cycle

= 100A

Single Pulse

I

D

Z_thJC(D, t_av) = Transient thermal resistance, see Figures 13)

0

P_{D (ave)}= 1/2 ( 1.3·BV·I_av) = DT/ Z_thJC

I_av= 2DT/ [1.3·BV·Z_th]

25

50

75

100

125

150

175

Starting T , Junction Temperature (°C)

J

E_{AS (AR)}= P_{D (ave)}·t_av

Fig 16. Maximum Avalanche Energy vs. Temperature

6

www.irf.com

September 6, 2012

IRFS7437-7PPbF

5.0

4.0

3.0

2.0

1.0

12

10

8

I = 60A

F

V

= 34V

R

T = 25°C

J

T = 125°C

J

6

I

= 150μA

= 1.0mA

= 1.0A

D

4

2

0

-75 -50 -25

0

25 50 75 100 125 150 175

0

200

400

600

800

1000

T , Temperature ( °C )

di /dt (A/μs)

J

F

Fig. 18 - Typical Recovery Current vs. di_f/dt

Fig 17. Threshold Voltage vs. Temperature

12

300

I = 100A

F

I = 60A

F

V

= 34V

V

= 34V

R

10

8

R

250

200

150

100

50

T = 25°C

J

T = 125°C

J

T = 125°C

J

6

4

2

0

200

400

600

800

1000

0

200

400

600

800

1000

di /dt (A/μs)

F

Fig. 19 - Typical Recovery Current vs. di_f/dt

Fig. 20 - Typical Stored Charge vs. di_f/dt

300

I = 100A

F

V

= 34V

R

250

200

150

100

50

T = 25°C

J

T = 125°C

J

0

200

400

600

800

1000

di /dt (A/μs)

F

Fig. 21 - Typical Stored Charge vs. di_f/dt

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7

September 6, 2012

IRFS7437-7PPbF

Driver Gate Drive

P.W.

Period

D.U.T

Period

D =

+

-

*

=10V

V

GS

Circuit Layout Considerations

 Low Stray Inductance

Ground Plane

Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

-

+

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

dv/dt controlled by R_G

R_G

+

-

Body Diode

Forward Drop

Driver same type as D.U.T.

I_SDcontrolled by Duty Factor "D"

D.U.T. - Device Under Test

Inductor Current

Inductor Curent

I

SD

Ripple

 5%

* V_GS= 5V for Logic Level Devices

Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

V

(BR)DSS

15V

t

p

DRIVER

+

L

V

DS

D.U.T

AS

R

G

V

DD

-

I

A

2V0_GV_S



0.01

t

p

I

AS

Fig 22b. Unclamped Inductive Waveforms

Fig 22a. Unclamped Inductive Test Circuit

R_D

V_DS

V

DS

90%

V_GS

D.U.T.

R_G

+

V_DD

-

10V

V_GS

10%

Pulse Width µs

Duty Factor 

V

GS

t

r

t

f

d(on)

d(off)

Fig 23a. Switching Time Test Circuit

Fig 23b. Switching Time Waveforms

Id

Current Regulator

Same Type as D.U.T.

Vds

Vgs

50K

.2F

12V

.3F

+

V

DS

D.U.T.

-

Vgs(th)

V

GS

3mA

I

D

G

Qgs1

Qgs2

Qgd

Qgodr

Current Sampling Resistors

Fig 24a. Gate Charge Test Circuit

Fig 24b. Gate Charge Waveform

8

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September 6, 2012

IRFS7437-7PPbF

D²Pak - 7 Pin Package Outline

Dimensions are shown in millimeters (inches)

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

www.irf.com

9

September 6, 2012

IRFS7437-7PPbF

D²Pak - 7 Pin Part Marking Information

D²Pak - 7 Pin Tape and Reel

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

10

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September 6, 2012

IRFS7437-7PPbF

Qualification information

†

Industrial^††

(per JEDEC JESD47F^†††guidelines)

Qualification level

MS L 1

(per JE DE C J-S TD-020D^†††

D²Pak-7PIN

Moisture Sensitivity Level

RoHS compliant

)

Yes

Qualification standards can be found at International Rectifiers web site: http://www.irf.com/product-info/reliability/

Higher qualification ratings may be available should the user have such requirements. Please contact your

International Rectifier sales representative for further information: http:www.irf.com/whoto-call/salesrep/

Applicable version of JEDEC standard at the time of product release.

Data and specifications subject to change without notice.

IR WORLD HEADQUARTERS: 101N Sepulveda., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 04/2012

www.irf.com

11

September 6, 2012


型号：	IRFS7437TRL7PP
厂家：	Infineon
描述：	HEXFETPower MOSFET ?? HEXFET功率MOSFET 晶体晶体管功率场效应晶体管
文件：	总11页 (文件大小：277K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFS7437TRL7PP [INFINEON]

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