IRFS7530-7PPBF [INFINEON]

Power Field-Effect Transistor;


型号：	IRFS7530-7PPBF
厂家：	Infineon
描述：	Power Field-Effect Transistor
文件：	总11页 (文件大小：554K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

StrongIRFET™

IRFS7530-7PPbF

HEXFET^®Power MOSFET

Application

 Brushed Motor drive applications

 BLDC Motor drive applications

 Battery powered circuits

 Half-bridge and full-bridge topologies

 Synchronous rectifier applications

 Resonant mode power supplies

 OR-ing and redundant power switches

V_DSS

R_DS(on)typ.

max

60V

1.15m

1.4m

338A

I_{D (Silicon Limited)}

I_{D (Package Limited)}

240A

Benefits

 Improved Gate, Avalanche and Dynamic dV/dt Ruggedness

 Fully Characterized Capacitance and Avalanche SOA

 Enhanced body diode dV/dt and dI/dt Capability

 Lead-Free, RoHS Compliant

Gate

Drain

Source

Base Part Number

Package Type

Standard Pack

Complete Part Number

Form

Tube

Quantity

IRFS7530-7PPbF

IRFS7530TRL7PP

IRFS7530-7PPbF

D2Pak-7PIN

Tape and Reel Left

800

350

300

250

200

150

100

= 100A

Limited By Package

T = 125°C

T = 25°C

100

125

150

175

, Gate-to-Source Voltage (V)

, Case Temperature (°C)

Fig 2. Maximum Drain Current vs. Case Temperature

Fig 1. Typical On-Resistance vs. Gate Voltage

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November 27, 2013

IRFS7530-7PPbF

Absolute Maximium Rating

Symbol

Parameter

Max.

Units

I_D@ T_C= 25°C

Continuous Drain Current, V_GS@ 10V (Silicon Limited)

338

239

I_D@ T_C= 100°C Continuous Drain Current, V_GS@ 10V (Silicon Limited)

I_D@ T_C= 25°C

I_DM

Continuous Drain Current, V_GS@ 10V (Wire Bond Limited)

Pulsed Drain Current 

240

1450

375

P_D@T_C= 25°C

Maximum Power Dissipation

Linear Derating Factor

W/°C

2.5

V_GS

T_J

Gate-to-Source Voltage

± 20

Operating Junction and

-55 to + 175

300

°C

T_STG

Storage Temperature Range

Soldering Temperature, for 10 seconds (1.6mm from case)

Avalanche Characteristics

E_{AS (Thermally limited)}

526

Single Pulse Avalanche Energy 

E_{AS (tested)}

I_AR

E_AR

1000

Single Pulse Avalanche Energy Tested Value 

Avalanche Current 

Repetitive Avalanche Energy 

See Fig 14, 15, 23a, 23b

Thermal Resistance

Symbol

Parameter

Typ.

Max.

Units

Junction-to-Case 

–––

0.40

R_JC

R_JA

°C/W

Junction-to-Ambient 

–––

Static @ T_J= 25°C (unless otherwise specified)

Symbol

Parameter

Min. Typ. Max. Units

Conditions

V_(BR)DSS

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

––– –––

V_GS= 0V, I_D= 250µA

–––

33 ––– mV/°C Reference to 25°C, I_D= 1mA 

V_(BR)DSS/T_J

R_DS(on)

––– 1.15 1.4

V_GS= 10V, I_D= 100A 

V_GS= 6.0V, I_D= 50A 

V_DS= V_GS, I_D= 250µA

V_DS= 60 V, V_GS= 0V

m

–––

1.4

–––

3.7

1.0

V_GS(th)

I_DSS

Gate Threshold Voltage

2.1 –––

––– –––

Drain-to-Source Leakage Current

µA

––– ––– 150

––– ––– 100

––– ––– -100

_DS= 60V,V_GS= 0V,T_J=125°C

V_GS= 20V

_GS= -20V

I_GSS

R_G

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Gate Resistance

–––

2.2

–––



Notes:

Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A.

Note that current limitations arising from heating of the device leads may occur with some lead mounting

arrangements. (Refer to AN-1140)

Repetitive rating; pulse width limited by max. junction temperature.

 Limited by T_Jmax, starting T_J= 25°C, L = 105µH, R_G= 50, I_AS= 100A, V_GS=10V.

I_SD 100A, di/dt  1575A/µs, V_DD V_(BR)DSS, T_J175°C.

Pulse width  400µs; duty cycle  2%.

 C_osseff. (TR) is a fixed capacitance that gives the same charging time as C_osswhile V_DSis rising from 0 to 80% V_DSS

 C_osseff. (ER) is a fixed capacitance that gives the same energy as C_osswhile V_DSis rising from 0 to 80% V_DSS

 R_is measured at T_Japproximately 90°C.

 This value determined from sample failure population, starting T_J=25°C, L= 105µH, R_G= 50, I_AS=100A,

V_GS=10V.

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IRFS7530-7PPbF

Dynamic Electrical Characteristics @ T_J= 25°C (unless otherwise specified)

Symbol

gfs

Parameter

Forward Transconductance

Total Gate Charge

Min. Typ. Max. Units

Conditions

V_DS= 10V, I_D=100A

I_D= 100A

249 ––– –––

––– 236 354

Q_g

Q_gs

Gate-to-Source Charge

Gate-to-Drain Charge

Total Gate Charge Sync. (Qg - Qgd)

Turn-On Delay Time

–––

V_DS= 30V

Q_gd

V_GS= 10V

Q_sync

t_d(on)

t_r

––– 163 –––

––– 24 –––

V_DD= 30V

I_D= 100A

Rise Time

––– 102 –––

––– 168 –––

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

R_G= 2.7

V_GS= 10V

–––

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

––– 12960 –––

––– 1270 –––

––– 760 –––

V_GS= 0V

V_DS= 25V

ƒ = 1.0MHz

C_{oss eff.(ER)}Effective Output Capacitance (Energy Related) ––– 1248 –––

V_GS= 0V, V_DS= 0V to 48V

V_GS= 0V, V_DS= 0V to 48V

C_{oss eff.(TR)}Output Capacitance (Time Related)

––– 1590 –––

Diode Characteristics

Symbol

I_S

Parameter

Continuous Source Current

(Body Diode)

Pulsed Source Current

(Body Diode)

Min. Typ. Max. Units

Conditions

MOSFET symbol

showing the

integral reverse

p-n junction diode.

––– ––– 338

––– ––– 1450

I_SM

V_SD

Diode Forward Voltage

––– –––

1.2

T_J= 25°C,I_S= 100A,V_GS= 0V 

dv/dt

Peak Diode Recovery dv/dt

–––

8.5

2.5

––– V/ns T_J= 175°C,I_S=100A,V_DS= 60V

–––

T_J= 25°C

V_DD= 51V

I_F= 100A,

t_rr

Reverse Recovery Time

T_J= 125°C

T_J= 25°C di/dt = 100A/µs 

Q_rr

Reverse Recovery Charge

Reverse Recovery Current

T_J= 125°C

I_RRM

T_J= 25°C



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IRFS7530-7PPbF

10000

1000

100

10000

1000

100

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

TOP

BOTTOM

4.5V

60µs PULSE WIDTH



4.5V

60µs PULSE WIDTH



Tj = 25°C

Tj = 175°C

0.1

100

0.1

100

, Drain-to-Source Voltage (V)

Fig 4. Typical Output Characteristics

Fig 3. Typical Output Characteristics

2.5

2.0

1.5

1.0

0.5

10000

= 100A

= 10V

1000

T = 175°C

100

T = 25°C

= 25V

60µs PULSE WIDTH



0.1

2.0

4.0

6.0

8.0

-60 -40 -20

20 40 60 80 100 120 140 160 180

, Gate-to-Source Voltage (V)

T , Junction Temperature (°C)

Fig 6. Normalized On-Resistance vs. Temperature

Fig 5. Typical Transfer Characteristics

1000000

100000

10000

1000

= 0V,

f = 1 MHZ

I = 100A

= 48V

= 30V

12V

= C + C , C SHORTED

iss

= C

rss

oss

+ C

DS=

Ciss

Coss

Crss

100

150

200

250

300

, Drain-to-Source Voltage (V)

100

Total Gate Charge (nC)

Fig 8. Typical Gate Charge vs.

Fig 7. Typical Capacitance vs.

Gate-to-Source Voltage

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IRFS7530-7PPbF

10000

1000

100

10000

1000

100

100µsec

1msec

T = 175°C

imited by

Package

T = 25°C

OPERATION IN THIS AREA

LIMITED BY R (on)

10msec

Tc = 25°C

Tj = 175°C

Single Pulse

= 0V

1.4

0.1

0.2

0.4

0.6

0.8

1.0

1.2

1.6

0.1

100

, Source-to-Drain Voltage (V)

, Drain-toSource Voltage (V)

Fig 10. Maximum Safe Operating Area

Fig 9. Typical Source-Drain Diode Forward Voltage

2.0

Id = 1.0mA

1.5

1.0

0.5

0.0

-60 -40 -20 0 20 40 60 80 100120140160180

Drain-to-Source Voltage (V)

T , Temperature ( °C )

DS,

Fig 12. Typical C_ossStored Energy

Fig 11. Drain-to-Source Breakdown Voltage

2.2

= 5.5V

= 6.0V

= 7.0V

= 8.0V

= 10V

2.0

1.8

1.6

1.4

1.2

1.0

100

150

200

I , Drain Current (A)

Fig 13. Typical On-Resistance vs. Drain Current

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IRFS7530-7PPbF

0.1

D = 0.50

0.20

0.10

0.05

0.01

0.02

0.01

0.001

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0.0001

1E-006

1E-005

0.0001

0.001

0.01

0.1

, Rectangular Pulse Duration (sec)

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

100

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming Tj = 150°C and



Tstart =25°C (Single Pulse)

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming j = 25°C and



Tstart = 150°C. (Single Pulse)

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 15. Avalanche Current vs. Pulse Width

2400

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)

1.Avalanche failures assumption:

TOP

21A

44A

100A

2000

1600

1200

800

400

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T_jmax. This is validated for every

part type.

BOTTOM

2. Safe operation in Avalanche is allowed as long asT_jmaxis not

exceeded.

3. Equation below based on circuit and waveforms shown in Figures

23a, 23b.

4. P_{D (ave)}= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage

increase during avalanche).

6. I_av= Allowable avalanche current.

7. T = Allowable rise in junction temperature, not to exceed T_jmax

(assumed as 25°C in Figure 14, 15).

t_av= Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

100

125

150

175

Z_thJC(D, t_av) = Transient thermal resistance, see Figures 13)

Starting T , Junction Temperature (°C)

PD (ave) = 1/2 ( 1.3·BV·I_av) = T/ Z_thJC

_av= 2T/ [1.3·BV·Z_th]

E_{AS (AR)}= P_{D (ave)· av}

Fig 16. Maximum Avalanche Energy vs. Temperature

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IRFS7530-7PPbF

4.0

3.5

3.0

2.5

2.0

1.5

1.0

= 60A

= 51V

T = 25°C

T = 125°C

= 250µA

= 1.0mA

= 1.0A

-75 -50 -25

25 50 75 100 125 150 175

200

400

600

800

1000

T , Temperature ( °C )

di /dt (A/µs)

Fig 17. Threshold Voltage vs. Temperature

Fig 18. Typical Recovery Current vs. dif/dt

500

400

300

200

100

= 60A

= 51V

= 100A

= 51V

T = 25°C

T = 125°C

200

400

600

800

1000

200

400

600

800

1000

di /dt (A/µs)

Fig 20. Typical Stored Charge vs. dif/dt

Fig 19. Typical Recovery Current vs. dif/dt

500

= 100A

= 51V

400

300

200

100

T = 25°C

T = 125°C

200

400

600

800

1000

di /dt (A/µs)

Fig 21. Typical Stored Charge vs. dif/dt

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IRFS7530-7PPbF

Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET^®Power MOSFETs

(BR)DSS

15V

DRIVER

D.U.T

20V

0.01



Fig 23a. Unclamped Inductive Test Circuit

Fig 23b. Unclamped Inductive Waveforms

Fig 24a. Switching Time Test Circuit

Fig 24b. Switching Time Waveforms

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 25b. Gate Charge Waveform

Fig 25a. Gate Charge Test Circuit

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IRFS7530-7PPbF

D²Pak-7Pin Package Outline (Dimensions are shown in millimeters (inches))

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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IRFS7530-7PPbF

D²Pak-7Pin Part Marking Information

D2Pak-7Pin Tape and Reel

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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IRFS7530-7PPbF

Qualification Information^†

Qualification Level

Industrial

(per JEDEC JESD47F) ^††

D²Pak-7Pin

MSL1

Yes

Moisture Sensitivity Level

RoHS Compliant

†

Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/

†† Applicable version of JEDEC standard at the time of product release.

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/

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IRFS7530-7PPBF [INFINEON]

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