IRFHM8228PBF [INFINEON]

Compatible with Existing Surface Mount Techniques;
IRFHM8228PBF
型号: IRFHM8228PBF
厂家: Infineon    Infineon
描述:

Compatible with Existing Surface Mount Techniques

文件: 总10页 (文件大小:672K)
中文:  中文翻译
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IRFHM8228PbF  
HEXFET® Power MOSFET  
VDSS  
25  
V
V
VGS max  
±20  
RDS(on) max  
(@ VGS = 10V)  
5.2  
G
m  
S
S
S
(@ VGS = 4.5V)  
8.7  
D
Qg (typical)  
9.0  
nC  
A
D
D
D
D
ID  
25  
(@TC (Bottom) = 25°C)  
Applications  
Control or synchronous MOSFET for synchronous buck converter  
Features  
Benefits  
Low Thermal Resistance to PCB (<3.7°C/W)  
Low Profile (<1.05 mm)  
Enable better thermal dissipation  
Increased Power Density  
Multi-Vendor Compatibility  
Easier Manufacturing  
Industry-Standard Pinout  
results in  
Compatible with Existing Surface Mount Techniques  
RoHS Compliant, Halogen-Free  
MSL1, Consumer Qualification  
  
Environmentally Friendlier  
Increased Reliability  
Base part number  
Package Type  
Standard Pack  
Orderable Part Number  
Form  
Quantity  
IRFHM8228PbF  
PQFN 3.3 mm x 3.3 mm  
Tape and Reel  
4000  
IRFHM8228TRPbF  
Absolute Maximum Ratings  
Parameter  
Gate-to-Source Voltage  
Max.  
± 20  
19  
Units  
VGS  
V
ID @ TA = 25°C  
ID @ TA = 70°C  
ID @ TC(Bottom) = 25°C  
ID @ TC(Bottom) = 100°C  
ID @ TC = 25°C  
Continuous Drain Current, VGS @ 10V  
Continuous Drain Current, VGS @ 10V  
Continuous Drain Current, VGS @ 10V  
Continuous Drain Current, VGS @ 10V  
15  
65  
41  
A
Continuous Drain Current, VGS @ 10V  
(Source Bonding Technology Limited)  
25  
IDM  
Pulsed Drain Current   
Power Dissipation   
260  
2.8  
PD @TA = 25°C  
PD @TC(Bottom) = 25°C  
W
Power Dissipation   
34  
Linear Derating Factor   
Operating Junction and  
Storage Temperature Range  
0.023  
W/°C  
TJ  
-55 to + 150  
°C  
TSTG  
Notes through are on page 10  
1
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June 30, 2014  
IRFHM8228PbF  
Static @ TJ = 25°C (unless otherwise specified)  
Parameter  
Min.  
25  
Typ.  
–––  
18  
Max. Units  
–––  
––– mV/°C Reference to 25°C, ID = 1mA  
Conditions  
VGS = 0V, ID = 250µA  
BVDSS  
BVDSS/TJ  
RDS(on)  
Drain-to-Source Breakdown Voltage  
Breakdown Voltage Temp. Coefficient  
Static Drain-to-Source On-Resistance  
V
–––  
–––  
–––  
1.35  
–––  
–––  
–––  
–––  
–––  
63  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
4.2  
6.7  
1.8  
-6.6  
–––  
–––  
–––  
–––  
–––  
18  
9.0  
2.7  
1.0  
3.1  
2.2  
4.1  
9.7  
1.7  
11  
5.2  
8.7  
VGS = 10V, ID = 20A   
GS = 4.5V, ID = 16A   
m  
V
VGS(th)  
VGS(th)  
IDSS  
Gate Threshold Voltage  
Gate Threshold Voltage Coefficient  
Drain-to-Source Leakage Current  
2.35  
V
VDS = VGS, ID = 25µA  
––– mV/°C  
1.0  
150  
100  
-100  
–––  
–––  
14  
µA VDS = 20V, VGS = 0V  
VDS = 20V, VGS = 0V, TJ = 125°C  
nA VGS = 20V  
IGSS  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Forward Transconductance  
Total Gate Charge  
V
GS = -20V  
VDS = 10V, ID = 20A  
nC VGS = 10V, VDS = 13V, ID = 20A  
gfs  
Qg  
S
Qg  
Total Gate Charge  
V
V
DS = 13V  
GS = 4.5V  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Qsw  
Qoss  
RG  
Pre-Vth Gate-to-Source Charge  
Post-Vth Gate-to-Source Charge  
Gate-to-Drain Charge  
Gate Charge Overdrive  
Switch Charge (Qgs2 + Qgd)  
Output Charge  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
nC  
ID = 20A  
nC VDS = 16V, VGS = 0V  
VDD = 13V, VGS = 4.5V  
ns ID = 20A  
RG=1.8  
Gate Resistance  
td(on)  
tr  
td(off)  
tf  
Turn-On Delay Time  
Rise Time  
Turn-Off Delay Time  
Fall Time  
22  
13  
6.2  
1667  
456  
195  
Ciss  
Coss  
Crss  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
VGS = 0V  
VDS = 10V  
pF  
ƒ = 1.0MHz  
Avalanche Characteristics  
Parameter  
Single Pulse Avalanche Energy   
Typ.  
–––  
Max.  
50  
Units  
mJ  
EAS  
Diode Characteristics  
Parameter  
Min. Typ. Max. Units  
Conditions  
MOSFET symbol  
showing the  
D
IS  
Continuous Source Current  
(Body Diode)  
––– ––– 25  
A
––– ––– 260  
G
ISM  
Pulsed Source Current  
(Body Diode)   
integral reverse  
S
p-n junction diode.  
VSD  
trr  
Qrr  
Diode Forward Voltage  
Reverse Recovery Time  
Reverse Recovery Charge  
––– ––– 1.0  
V
ns  
TJ = 25°C, IS = 20A, VGS = 0V   
TJ = 25°C, IF = 20A, VDD = 13V  
––– 14  
––– 10  
21  
15  
nC di/dt = 260A/µs   
Thermal Resistance  
Parameter  
Typ.  
–––  
–––  
Max.  
3.7  
Units  
Junction-to-Case   
RJC (Bottom)  
RJC (Top)  
°C/W  
Junction-to-Case   
41  
Junction-to-Ambient   
Junction-to-Ambient   
–––  
–––  
44  
29  
RJA  
RJA (<10s)  
2
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June 30, 2014  
IRFHM8228PbF  
1000  
100  
10  
1000  
100  
10  
VGS  
10V  
VGS  
10V  
TOP  
TOP  
7.0V  
4.5V  
4.0V  
3.5V  
3.0V  
2.75V  
2.5V  
7.0V  
4.5V  
4.0V  
3.5V  
3.0V  
2.75V  
2.5V  
BOTTOM  
BOTTOM  
1
0.1  
0.01  
2.5V  
60µs PULSE WIDTH  
Tj = 25°C  
2.5V  
60µs PULSE WIDTH  
Tj = 150°C  
1
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
V
, Drain-to-Source Voltage (V)  
DS  
DS  
Fig 1. Typical Output Characteristics  
Fig 2. Typical Output Characteristics  
1000  
100  
10  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
I
= 20A  
D
V
= 10V  
GS  
T
= 150°C  
J
T
= 25°C  
J
1
V
= 10V  
DS  
60µs PULSE WIDTH  
0.1  
0
2
4
6
8
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
T
J
, Junction Temperature (°C)  
V
, Gate-to-Source Voltage (V)  
GS  
Fig 4. Normalized On-Resistance vs. Temperature  
Fig 3. Typical Transfer Characteristics  
14.0  
10000  
1000  
100  
V
= 0V,  
= C  
f = 1 MHZ  
GS  
I = 20A  
D
C
C
C
+ C , C  
SHORTED  
iss  
gs  
gd  
ds  
12.0  
10.0  
8.0  
V
V
V
= 20V  
= 13V  
= 5.0V  
= C  
DS  
DS  
DS  
rss  
oss  
gd  
= C + C  
ds  
gd  
C
iss  
6.0  
C
C
oss  
rss  
4.0  
2.0  
0.0  
0
5
10  
15  
20  
25  
1
10  
, Drain-to-Source Voltage (V)  
100  
Q , Total Gate Charge (nC)  
V
G
DS  
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage  
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage  
3
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IRFHM8228PbF  
1000  
100  
10  
1000  
100  
10  
OPERATION IN THIS AREA  
LIMITED BY R  
(on)  
DS  
T
= 150°C  
J
100µsec  
1msec  
Limited by source bonding  
technology  
1
T
= 25°C  
J
1
10msec  
DC  
0.1  
0.01  
Tc = 25°C  
Tj = 150°C  
Single Pulse  
V
= 0V  
GS  
0.1  
0.1  
1
10  
100  
0.0  
0.4  
0.8  
1.2  
1.6  
2.0  
V
, Drain-to-Source Voltage (V)  
DS  
V
, Source-to-Drain Voltage (V)  
SD  
Fig 8. Maximum Safe Operating Area  
Fig 7. Typical Source-Drain Diode Forward Voltage  
3.0  
70  
Limited by source  
60  
bonding technology  
2.5  
2.0  
50  
40  
30  
20  
10  
0
I
I
I
I
= 25µA  
= 250µA  
= 1.0mA  
= 1.0A  
D
D
D
D
1.5  
1.0  
0.5  
-75 -50 -25  
0
25 50 75 100 125 150  
25  
50  
T
75  
100  
125  
150  
T
, Temperature ( °C )  
, Case Temperature (°C)  
J
C
Fig 10. Drain-to–Source Breakdown Voltage  
Fig 9. Maximum Drain Current vs. Case Temperature  
10  
D = 0.50  
1
0.20  
0.10  
0.05  
0.1  
0.01  
0.02  
0.01  
SINGLE PULSE  
( THERMAL RESPONSE )  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
0.001  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
1
t
, Rectangular Pulse Duration (sec)  
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case  
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4
June 30, 2014  
IRFHM8228PbF  
18  
14  
10  
6
200  
160  
120  
80  
I
= 20A  
I
D
D
TOP  
4.4A  
9.2A  
BOTTOM 20A  
T
= 125°C  
J
40  
T
= 25°C  
J
2
0
2
4
6
8
10 12 14 16 18 20  
25  
50  
75  
100  
125  
150  
Starting T , Junction Temperature (°C)  
J
V
Gate -to -Source Voltage (V)  
GS,  
Fig 13. Maximum Avalanche Energy vs. Drain Current  
Fig 12. On-Resistance vs. Gate Voltage  
100  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming Tj = 125°C and  
Tstart =25°C (Single Pulse)  
10  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming j = 25°C and  
Tstart = 125°C.  
1
0.1  
1.0E-06  
1.0E-05  
1.0E-04  
tav (sec)  
1.0E-03  
1.0E-02  
Fig 14. Single Avalanche Event: Pulse Current vs. Pulse Width  
5
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IRFHM8228PbF  
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs  
V
(BR)DSS  
t
p
15V  
DRIVER  
+
L
V
DS  
D.U.T  
AS  
R
G
V
DD  
-
I
A
20V  
I
0.01  
t
p
AS  
Fig 16a. Unclamped Inductive Test Circuit  
Fig 16b. Unclamped Inductive Waveforms  
Fig 17a. Switching Time Test Circuit  
Fig 17b. Switching Time Waveforms  
Id  
Vds  
Vgs  
VDD  
Vgs(th)  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Fig 18a. Gate Charge Test Circuit  
Fig 18b. Gate Charge Waveform  
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6
www.irf.com © 2014 International Rectifier  
IRFHM8228PbF  
Placement and Layout Guidelines  
The typical application topology for this product is the synchronous buck converter. These converters operate at high  
frequencies (typically around 400 kHz). During turn-on and turn-off switching cycles, the high di/dt currents circulating in  
the parasitic elements of the circuit induce high voltage ringing which may exceed the device rating and lead to  
undesirable effects. One of the major contributors to the increase in parasitics is the PCB power circuit inductance.  
This section introduces a simple guideline that mitigates the effect of these parasitics on the performance of the circuit  
and provides reliable operation of the devices.  
To reduce high frequency switching noise and the effects of Electromagnetic Interference (EMI) when the control  
MOSFET (Q1) is turned on, the layout shown in Figure 19 is recommended. The input bypass capacitors, control  
MOSFET and output capacitors are placed in a tight loop to minimize parasitic inductance which in turn lowers the  
amplitude of the switch node ringing, and minimizes exposure of the MOSFETs to repetitive avalanche conditions.  
Fig 19. Placement and Layout Guidelines  
7
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June 30, 2014  
IRFHM8228PbF  
PQFN 3.3mm x 3.3mm Outline Package Details  
For more information on board mounting, including footprint and stencil recommendation, please refer to application note  
AN-1136: http://www.irf.com/technical-info/appnotes/an-1136.pdf  
For more information on package inspection techniques, please refer to application note AN-1154:  
http://www.irf.com/technical-info/appnotes/an-1154.pdf  
PQFN 3.3mm x 3.3mm Outline Part Marking  
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/  
8
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June 30, 2014  
IRFHM8228PbF  
PQFN 3.3mm x 3.3mm Outline Tape and Reel  
REEL DIMENSIONS  
TAPE DIMENSIONS  
DIMENSION (MM)  
DIMENSION (INCH)  
CODE  
Ao  
MIN  
3.50  
3.50  
1.10  
7.90  
11.80  
12.30  
MAX  
3.70  
MIN  
.138  
.138  
.043  
.311  
.465  
.484  
MAX  
.146  
.146  
.051  
.319  
.480  
.492  
3.70  
Bo  
1.30  
Ko  
8.10  
P
1
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
12.20  
12.50  
W
W
1
Qty  
4000  
13 Inches  
Reel Diameter  
CODE  
DESCRIPTION  
Ao  
Bo  
Ko  
W
Dimension design to accommodate the component width  
Dimension design to accommodate the component lenght  
Dimension design to accommodate the component thickness  
Overall width of the carrier tape  
P
1
Pitch between successive cavity centers  
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/  
9
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June 30, 2014  
IRFHM8228PbF  
Qualification Information†  
Qualification Level  
Consumer††  
(per JEDEC JESD47F††† guidelines)  
MSL1  
PQFN 3.3mm x 3.3mm  
Moisture Sensitivity Level  
RoHS Compliant  
(per JEDEC J-STD-020D††)  
Yes  
Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability  
†† Higher qualification ratings may be available should the user have such requirements. Please contact your  
International Rectifier representative for further information: http://www.irf.com/whoto-call/salesrep/  
††† Applicable version of JEDEC standard at the time of product release.  
Notes:  
Repetitive rating; pulse width limited by max. junction temperature.  
Starting TJ = 25°C, L = 0.25mH, RG = 50, IAS = 20A.  
Pulse width 400µs; duty cycle 2%.  
Ris measured at TJ of approximately 90°C.  
When mounted on 1 inch square 2 oz copper pad on 1.5x1.5 in. board of FR-4 material. Please refer to AN-994  
for more details: http://www.irf.com/technical-info/appnotes/an-994.pdf  
Calculated continuous current based on maximum allowable junction temperature.  
Current is limited to 25A by source bonding technology.  
Revision History  
Date  
Comments  
 Updated schematic on page 1.  
 Updated part marking on page 8.  
 Updated tape and reel on page 9.  
6/5/14  
6/30/14  
 Remove “SAWN” package outline on page 8.  
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA  
To contact International Rectifier, please visit http://www.irf.com/whoto-call/  
10  
www.irf.com © 2014 International Rectifier  
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June 30, 2014  

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