IRFH7084PBF_15_技术文档

StrongIRFET™

IRFH7084PbF

HEXFET^®Power MOSFET

Application

 Half-bridge and full-bridge topologies

 Synchronous rectifier applications

 Resonant mode power supplies

 DC/DC converters

V_DSS

40V

R_{DS(on) typ.}

0.95m

1.25m

265A

 DC/AC Inverters

max

I_{D (Silicon Limited)}

I_{D (Package Limited)}

100A

Benefits

 Improved Gate, Avalanche and Dynamic dV/dt Ruggedness

 Fully Characterized Capacitance and Avalanche SOA

 Enhanced body diode dV/dt and dI/dt Capability

 Lead-Free, RoHS Compliant

PQFN 5X6 mm

Base part number

Package Type

Standard Pack

Orderable Part Number

Form

Tape and Reel

Quantity

4000

IRFH7084TRPbF

IRFH7084PbF

PQFN 5mm x 6mm

6

5

4

3

2

1

300

240

180

120

60

I

= 100A

D

Limited by package

T = 125°C

J

T = 25°C

J

0

4

0

8

12

16

20

25

50

75

100

125

150

V

, Gate-to-Source Voltage (V)

GS

T

, Case Temperature (°C)

C

Fig 2. Maximum Drain Current vs. Case Temperature

Fig 1. Typical On-Resistance vs. Gate Voltage

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IRFH7084PbF

Absolute Maximium Rating

Symbol

Parameter

Max.

Units

I_D@ T_A= 25°C

Continuous Drain Current, V_GS@ 10V

40

I_D@ T_C(Bottom)= 25°C

265

170

100

400

A

I_D@ T_C(Bottom)= 100°C Continuous Drain Current, V_GS@ 10V

I_D@ T_C= 25°C

I_DM

Continuous Drain Current, V_GS@ 10V (Package Limited)

Pulsed Drain Current 

Linear Derating Factor

Max Power Dissipation

Gate-to-Source Voltage

A

1.25

156

W/°C

P_D@T_C= 25°C

V_GS

± 20

V

T_J

T_STG

Operating Junction and

Storage Temperature Range

-55 to + 150

°C

Avalanche Characteristics

E_{AS (Thermally limited)}

I_AR

E_AR

185

431

Single Pulse Avalanche Energy 

Single Pulse Avalanche Energy 

Avalanche Current 

mJ

A

mJ

See Fig 14, 15, 23a,

Repetitive Avalanche Energy 

Thermal Resistance

Parameter

Junction-to-Case 

Typ.

0.5

Max.

0.8

21

Units

R_JC(Bottom)

R_JC(Top)

R_JA

Junction-to-Case

–––

°C/W

Junction-to-Ambient 

35

R_JA(<10s)

20

Static @ T_J= 25°C (unless otherwise specified)

Symbol

V_(BR)DSS

Parameter

Min. Typ. Max. Units

40 ––– –––

––– 0.034 ––– V/°C Reference to 25°C, I_D= 1mA

Conditions

V_GS= 0V, I_D= 250µA

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

Gate Threshold Voltage

V

V_(BR)DSS/T_J

R_DS(on)

V_GS(th)

––– 0.95 1.25

V_GS= 10V, I_D= 100A 

m

2.2 –––

––– –––

––– ––– 150

––– ––– 100

––– ––– -100

3.9

1.0

V

V_DS= V_GS, I_D= 150µA

V

_DS=40 V, V_GS= 0V

_DS=40V,V_GS= 0V,T_J=125°C

_GS= 20V

I_DSS

Drain-to-Source Leakage Current

µA

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Gate Resistance

I_GSS

R_G

nA

_GS= -20V

–––

1.4

–––



Notes:

Repetitive rating; pulse width limited by max. junction temperature.

 Limited by T_Jmax, starting T_J= 25°C, L = 0.037mH, R_G= 50, I_AS= 100A, V_GS=10V.

I_SD 100A, di/dt  994A/µs, V_DD V_(BR)DSS, T_J150°C.

Pulse width  400µs; duty cycle  2%.

 C_osseff. (TR) is a fixed capacitance that gives the same charging time as C_osswhile V_DSis rising from 0 to 80% V_DSS

.

 C_osseff. (ER) is a fixed capacitance that gives the same energy as C_osswhile V_DSis rising from 0 to 80% V_DSS

.

 R_is measured at T_Japproximately 90°C.

 Limited by T_Jmax, starting T_J= 25°C, L = 1mH, R_G= 50, I_AS= 29A, V_GS=10V.

 When mounted on 1 inch square PCB (FR-4). Please refer to AN-994 for more details:

http://www.irf.com/technical-info/appnotes/an-994.pdf

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IRFH7084PbF

Dynamic Electrical Characteristics @ T_J= 25°C (unless otherwise specified)

Symbol

gfs

Parameter

Forward Transconductance

Total Gate Charge

Min. Typ. Max. Units

Conditions

120 ––– –––

––– 127 190

S

V_DS= 10V, I_D=100A

Q_g

I_D= 100A

V_DS= 20V

V_GS= 10V

Q_gs

Gate-to-Source Charge

Gate-to-Drain Charge

Total Gate Charge Sync. (Qg– Qgd)

Turn-On Delay Time

–––

35

41

–––

nC

Q_gd

Q_sync

t_d(on)

t_r

––– 195 –––

–––

16

31

64

34

–––

V_DD= 20V

I_D= 30A

Rise Time

ns

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

R_G= 2.7

V

_GS= 10V

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

––– 6560 –––

––– 940 –––

––– 650 –––

V_GS= 0V

V_DS= 25V

ƒ = 1.0MHz, See Fig.5

pF

V_GS= 0V, VDS = 0V to 32V

C_{oss eff.(ER)}Effective Output Capacitance (Energy Related) ––– 1120 –––

See Fig.11

C_{oss eff.(TR)}Output Capacitance (Time Related)

––– 1300 –––

V_GS= 0V, VDS = 0V to 32V

Diode Characteristics

Symbol

I_S

Parameter

Continuous Source Current

(Body Diode)

Pulsed Source Current

(Body Diode)

Min. Typ. Max. Units

Conditions

D

MOSFET symbol

showing the

––– ––– 100

A

––– ––– 400

G

integral reverse

p-n junction diode.

I_SM

S

V_SD

Diode Forward Voltage

––– –––

1.3

V

T_J= 25°C,I_S= 100A,V_GS= 0V 

dv/dt

Peak Diode Recovery dv/dt

–––

4.5

36

37

38

40

1.7

––– V/ns T_J= 150°C,I_S=100A,V_DS= 40V

–––

T_J= 25°C

V_DD= 34V

I_F= 100A,

t_rr

Reverse Recovery Time

ns

T_J= 125°C

T_J= 25°C di/dt = 100A/µs 

Q_rr

Reverse Recovery Charge

Reverse Recovery Current

nC

A

T_J= 125°C

I_RRM

T_J= 25°C



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IRFH7084PbF

10000

1000

100

10

10000

1000

100

10

VGS

15V

10V

7.0V

6.0V

5.0V

4.5V

4.3V

4.0V

VGS

15V

10V

7.0V

6.0V

5.0V

4.5V

4.3V

4.0V

TOP

BOTTOM

4.0V

1

 60µs PULSE WIDTH

Tj = 150°C

4.0V

 60µs PULSE WIDTH

Tj = 25°C

1

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 4. Typical Output Characteristics

Fig 3. Typical Output Characteristics

1.8

1.6

1.4

1.2

1.0

0.8

0.6

10000

I

= 100A

= 10V

D

V

GS

1000

100

T

= 150°C

J

10

1

T

= 25°C

J

V

= 10V

DS

 60µs PULSE WIDTH

0.1

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

-60 -40 -20

T

0

20 40 60 80 100 120 140 160

V

, Gate-to-Source Voltage (V)

GS

, Junction Temperature (°C)

J

Fig 6. Normalized On-Resistance vs. Temperature

Fig 5. Typical Transfer Characteristics

14

100000

V

= 0V,

f = 1 MHZ

GS

I = 100A

D

C

= C + C , C SHORTED

iss

gs gd ds

12

V

= 32V

= 20V

= C

DS

rss

oss

gd

= C + C

ds

gd

10

8

10000

1000

100

Ciss

6

Coss

Crss

4

2

0

40

80

120

160

1

10

, Drain-to-Source Voltage (V)

100

Q

Total Gate Charge (nC)

G

V

DS

Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage

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Fig 7. Typical Capacitance vs. Drain-to-Source Voltage

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IRFH7084PbF

10000

1000

100

10

1000

100

10

100µsec

1msec

T

= 150°C

J

imited by

Package

L

T

= 25°C

J

10msec

OPERATION IN THIS AREA

LIMITED BY R (on)

DS

1

Tc = 25°C

Tj = 150°C

Single Pulse

DC

10

V

= 0V

GS

1.6

0.1

0.0

0.4

0.8

1.2

2.0

0.1

1

V

, Source-to-Drain Voltage (V)

V

, Drain-toSource Voltage (V)

SD

DS

Fig 10. Maximum Safe Operating Area

Fig 9. Typical Source-Drain Diode Forward Voltage

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

49

Id = 1.0mA

48

47

46

45

44

43

42

41

40

0

10

20

30

40

-60 -40 -20

0

T

20 40 60 80 100 120 140 160

, Temperature ( °C )

V

Drain-to-Source Voltage (V)

DS,

J

Fig 12. Typical C_ossStored Energy

Fig 11. Drain-to–Source Breakdown Voltage

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

VGS = 6.0V

VGS = 7.0V

VGS = 10V

VGS = 15V

0

40

80

120

160

200

I , Drain Current (A)

D

Fig 13. Typical On-Resistance vs. Drain Current

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IRFH7084PbF

1

D = 0.50

0.20

0.10

0.1

0.05

0.02

0.01

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE

( THERMAL RESPONSE )

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

t

, Rectangular Pulse Duration (sec)

1

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

100

10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming Tj = 125°C and

Tstart =25°C (Single Pulse)

1

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming j = 25°C and

Tstart = 125°C.

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current vs. Pulse width

200

180

160

140

120

100

80

TOP

Single Pulse

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)

1.Avalanche failures assumption:

BOTTOM 1.0% Duty Cycle

I

= 100A

D

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T_jmax. This is validated for every

part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis not

exceeded.

3. Equation below based on circuit and waveforms shown in Figures

22a, 22b.

4. P_{D (ave)}= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage

increase during avalanche).

60

40

6. I_av= Allowable avalanche current.

7. T = Allowable rise in junction temperature, not to exceed T_jmax

(assumed as 25°C in Figure 14, 15).

20

t_av= Average time in avalanche.

0

D = Duty cycle in avalanche = tav ·f

Z_thJC(D, t_av) = Transient thermal resistance, see Figures 13)

25

50

75

100

125

150

Starting T , Junction Temperature (°C)

J

PD (ave) = 1/2 ( 1.3·BV·I_av) = T/ Z_thJC

I

_av= 2T/ [1.3·BV·Z_th]

E_{AS (AR)}= P_{D (ave)· av}

t

Fig 16. Maximum Avalanche Energy vs. Temperature

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IRFH7084PbF

4.5

4.0

3.5

3.0

2.5

2.0

1.5

12

10

8

I

= 60A

= 34V

F

V

R

T = 25°C

J

T = 125°C

J

6

I

= 150µA

= 1.0mA

= 1.0A

D

4

2

0

-75 -50 -25

0

25

50

75 100 125 150

0

200

400

600

800

1000

T

, Temperature ( °C )

J

di /dt (A/µs)

F

Fig 17. Threshold Voltage vs. Temperature

Fig 18. Typical Recovery Current vs. dif/dt

240

12

I

= 60A

= 34V

R

I

= 100A

= 34V

F

V

200

160

120

80

V

10

8

R

T = 25°C

J

T = 125°C

J

T = 125°C

J

6

4

40

2

0

200

400

600

800

1000

0

200

400

600

800

1000

di /dt (A/µs)

F

Fig 20. Typical Stored Charge vs. dif/dt

Fig 19. Typical Recovery Current vs. dif/dt

240

I

= 100A

= 34V

F

V

200

160

120

80

R

T = 25°C

J

T = 125°C

J

40

0

200

400

600

800

1000

di /dt (A/µs)

F

Fig 21. Typical Stored Charge vs. dif/dt

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IRFH7084PbF

Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET^®Power MOSFETs

V

(BR)DSS

t

p

15V

DRIVER

+

L

V

DS

D.U.T

AS

R

G

V

DD

-

I

A

20V

I

0.01



t

p

AS

Fig 23a. Unclamped Inductive Test Circuit

Fig 23b. Unclamped Inductive Waveforms

Fig 24a. Switching Time Test Circuit

Fig 24b. Switching Time Waveforms

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 25b. Gate Charge Waveform

Fig 25a. Gate Charge Test Circuit

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IRFH7084PbF

PQFN 5x6 Outline "B" Package Details

For more information on board mounting, including footprint and stencil recommendation, please refer to application note

AN-1136: http://www.irf.com/technical-info/appnotes/an-1136.pdf

For more information on package inspection techniques, please refer to application note AN-1154:

http://www.irf.com/technical-info/appnotes/an-1154.pdf

PQFN 5x6 Part Marking

INTERNATIONAL

RECTIFIER LOGO

DATE CODE

PART NUMBER

XXXX

(“4 or 5 digits”)

ASSEMBLY

SITE CODE

(Per SCOP 200-002)

MARKING CODE

XYWWX

XXXXX

(Per Marking Spec)

PIN 1

IDENTIFIER

LOT CODE

(Eng Mode - Min last 4 digits of EATI#)

(Prod Mode - 4 digits of SPN code)

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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IRFH7084PbF

PQFN 5x6 Tape and Reel

REEL DIMENSIONS

TAPE DIMENSIONS

CODE

Ao

DESCRIPTION

Dimension design to accommodate the component width

Dimension design to accommodate the component lenght

Dimension design to accommodate the component thickness

Overall width of the carrier tape

Bo

Ko

W

P

1

Pitch between successive cavity centers

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Note: All dimension are nominal

Package

Type

Reel

Diameter

(Inch)

QTY

Reel

Width

W1

Ao

Bo

Ko

P1

W

Pin 1

(mm)

Quadrant

(mm)

5 X 6 PQFN

13

4000

12.4

6.300

5.300

1.20

8.00

12

Q1

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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IRFH7084PbF

Qualification information^†

Industrial^††

(per JEDEC JESD47F ^††guidelines )

MSL1

(per JEDEC J-STD-020D^††)

Qualification level

Moisture Sensitivity Level

RoHS compliant

PQFN 5mmx 6mm

Yes

† Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/

†† Applicable version of JEDEC standard at the time of product release.

Revision History

Date

Comments

10/16/2014

 Add Pd at tc=25C on Absolute Max Rating table on page 2

Updated E_{AS (L =1mH)}= 431mJ on page 2

Updated note 8 “Limited by T_Jmax, starting T_J= 25°C, L = 1mH, R_G= 50, I_AS= 29A, V_GS=10V” on page 2

03/05/2015

3/19/2015

 Updated package outline on page 9.

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/

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型号：	IRFH7084PBF_15
厂家：	Infineon
描述：	Half-bridge and full-bridge topologies
文件：	总11页 (文件大小：715K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFH7084PBF_15 [INFINEON]

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