IRF8010 [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRF8010 |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总8页 (文件大小：495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 94497
SMPS MOSFET
IRF8010
Applications
HEXFET® Power MOSFET
ꢂ High frequency DC-DC converters
ꢂ UPS and Motor Control
VDSS
RDS(on) max
ID
80A
Benefits
ꢁ
100V
15mΩ
ꢂ Low Gate-to-Drain Charge to Reduce
Switching Losses
ꢂ Fully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
ꢂ Fully Characterized Avalanche Voltage
and Current
ꢂ Typical RDS(on) = 12mΩ
TO-220AB
Absolute Maximum Ratings
Parameter
Max.
Units
A
ꢁ
Continuous Drain Current, VGS @ 10V
80
I
I
I
@ T = 25°C
C
D
D
Continuous Drain Current, VGS @ 10V
@ T = 100°C
C
57
ꢀ
Pulsed Drain Current
Power Dissipation
320
260
DM
P
@T = 25°C
C
W
D
Linear Derating Factor
Gate-to-Source Voltage
1.8
20
W/°C
V
V
GS
ꢃ
dv/dt
T
J
Peak Diode Recovery dv/dt
Operating Junction and
16
V/ns
-55 to + 175
T
Storage Temperature Range
°C
STG
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
300 (1.6mm from case )
1.1(10)
N•m (lbf•in)
Thermal Resistance
Parameter
Typ.
–––
Max.
0.57
–––
62
Units
RθJC
RθCS
RθJA
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.50
–––
°C/W
Notes ꢀ through ꢁ are on page 8
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1
08/23/02
IRF8010
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
100
–––
0.11
12
–––
V
VGS = 0V, ID = 250µA
∆
V
∆
(BR)DSS/ TJ
Breakdown Voltage Temp. Coefficient –––
––– V/°C Reference to 25°C, ID = 1mA
mΩ
RDS(on)
VGS(th)
IDSS
ꢅ
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
2.0
15
4.0
VGS = 10V, ID = 45A
VDS = VGS, ID = 250µA
µA VDS = 100V, VGS = 0V
–––
–––
–––
–––
–––
V
Drain-to-Source Leakage Current
–––
–––
–––
–––
20
250
200
-200
VDS = 100V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA VGS = 20V
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 25V, ID = 45A
gfs
82
–––
–––
120
–––
–––
–––
–––
–––
–––
V
Qg
–––
–––
–––
–––
–––
–––
–––
81
ID = 80A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
22
nC
VDS = 80V
ꢅ
26
VGS = 10V
DD = 50V
ID = 80A
15
V
130
61
td(off)
tf
Ω
Turn-Off Delay Time
Fall Time
ns
R
G = 39
VGS = 10V
GS = 0V
VDS = 25V
pF ƒ = 1.0MHz
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
ꢅ
120
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
––– 3830 –––
V
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
480
59
–––
–––
––– 3830 –––
–––
–––
280
530
–––
–––
V
GS = 0V, VDS = 80V, ƒ = 1.0MHz
ꢃ
VGS = 0V, VDS = 0V to 80V
Avalanche Characteristics
Parameter
Typ.
–––
–––
–––
Max.
310
45
Units
mJ
A
ꢄꢁ
Single Pulse Avalanche Energy
EAS
IAR
ꢀ
Avalanche Current
ꢀ
Repetitive Avalanche Energy
EAR
26
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
I
I
Continuous Source Current
–––
–––
80
MOSFET symbol
S
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
–––
–––
320
SM
S
ꢀꢁ
(Body Diode)
p-n junction diode.
V
t
ꢅ
T = 25°C, I = 80A, V = 0V
J S GS
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
–––
–––
–––
–––
99
1.3
150
700
V
SD
ns T = 150°C, I = 80A, VDD = 50V
rr
J
F
ꢅ
di/dt = 100A/µs
Q
t
460
nC
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
2
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IRF8010
1000
100
10
10000
1000
100
10
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
6.0V
5.5V
5.0V
4.5V
4.0V
6.0V
5.5V
5.0V
4.5V
BOTTOM
BOTTOM 4.0V
4.0V
4.0V
1
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
1
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.5
1000
80A
=
I
D
T
= 175°C
3.0
2.5
2.0
1.5
1.0
0.5
0.0
J
100
10
1
T
= 25°C
J
V
= 50V
DS
20µs PULSE WIDTH
V
= 10V
GS
2.0
4.0
V
6.0
8.0
10.0
12.0
14.0
16.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
°
T , Junction Temperature
( C)
, Gate-to-Source Voltage (V)
J
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRF8010
100000
12
10
8
V
C
= 0V,
f = 1 MHZ
I = 80A
GS
D
= C + C , C SHORTED
iss
gs gd ds
V
V
V
= 80V
= 50V
= 20V
DS
DS
DS
C
= C
gd
rss
C
= C + C
oss
ds gd
10000
1000
100
C
iss
6
C
oss
4
2
C
rss
0
10
0
20
40
60
80
100
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
°
T = 175
J
C
100µsec
1msec
°
T = 25
J
C
1
1
Tc = 25°C
10msec
Tj = 175°C
Single Pulse
V
= 0 V
GS
0.1
0.1
0.0
0.5
1.0
1.5
2.0
1
10
100
1000
V
,Source-to-Drain Voltage (V)
SD
V
, Drain-to-Source Voltage (V)
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF8010
RD
80
60
40
20
0
VDS
LIMITED BY PACKAGE
VGS
10V
D.U.T.
RG
+VDD
-
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
°
, Case Temperature ( C)
T
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
1
D = 0.50
0.20
P
DM
0.1
t
1
0.10
0.05
t
2
SINGLE PULSE
0.02
Notes:
(THERMAL RESPONSE)
0.01
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF8010
600
500
400
300
200
100
0
15V
I
D
TOP
18A
32A
45A
DRIVER
+
L
BOTTOM
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
°
( C)
150
175
Starting Tj, Junction Temperature
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
Q
G
50KΩ
.2µF
12V
10 V
.3µF
Q
Q
GD
GS
+
V
DS
D.U.T.
-
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRF8010
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
ꢃ
-
+
ꢄ
-
ꢅ
-
+
ꢀ
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRF8010
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
- B -
3.78 (.149)
3.54 (.139)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
1.32 (.052)
1.22 (.048)
- A -
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
1.15 (.045)
MIN
LEAD ASSIGNMENTS
1 - GATE
1
2
3
2 - DRAIN
3 - SOURCE
4 - DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE : THIS IS AN IRF1010
WITH ASSEMBLY
A
INTERNATIONAL
RECTIFIER
PART NUMBER
LOT CODE 9B1M
IRF1010
9246
LOGO
9B 1M
DATE CODE
(YYWW)
ASSEMBLY
LOT CODE
YY = YEAR
WW = WEEK
Notes:
ꢀRepetitive rating; pulse width limited by
max. junction temperature.
ꢄStarting TJ = 25°C, L = 0.31mH, RG = 25Ω,
IAS = 45A.
ꢅPulse width ≤ 300µs; duty cycle ≤ 2%.
ꢆCoss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
.
ꢁCalculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.
ꢃISD ≤ 45A, di/dt ≤ 110A/µs, VDD ≤ V(BR)DSS
,
TJ ≤ 175°C.
TO-220 package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/02
8
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相关型号：
IRF8010STRLPBF
Power Field-Effect Transistor, 75A I(D), 100V, 0.015ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE, PLASTIC, D2PAK-3
INFINEON
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