IR11682SPBF_技术文档

Datasheet No – 97476

July 1, 2011

IR11682S

DUAL SmartRectifier^TMDRIVER IC

Product Summary

Features

•

Secondary-side

high

speed

controller

for

Topology

LLC Half-bridge

200V

synchronous rectification in resonant half bridge

topologies

VD

•

200V proprietary IC technology

Max 400KHz switching frequency

Anti-bounce logic and UVLO protection

4A peak turn off drive current

Micropower start-up & ultra low quiescent current

10.7V gate drive clamp

80ns turn-off propagation delay

Wide Vcc operating range

Direct sensing for both Synchronous Rectifiers

Cycle by Cycle MOT Check Circuit prevents multiple

false trigger GATE pulses

V_OUT

10.7V Clamped

+1A & -4A

I_o+& I _o-(typical)

Turn on Propagation Delay

100ns (typical)

Turn off Propagation Delay 80ns (typical)

Package Options

•

Minimal component count

Simple design

Lead-free

Typical Applications

•

LCD & PDP TV, Telecom SMPS, AC-DC adapters

8-Lead SOIC

Typical Connection Diagram

Vin

SR1

Cdc

C1

M1

Rg1

Lr

1

2

1

2

3

4

8

7

6

5

GATE1 GATE2

VCC

VS1

VD1

GND

VS2

VD2

LOAD

Cout

IR1168

IR11682

C2

M2

Rg2

Rtn

SR2

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IR11682S

Table of Contents

Description

Page

3

Qualification Information

Absolute Maximum Ratings

Electrical Characteristics

Functional Block Diagram

Input/Output Pin Equivalent Circuit Diagram

Lead Definitions

4

5

6

8

9

10

12

19

20

21

22

Lead Assignments

Application Information and Additional Details

Package Details

Tape and Reel Details

Part Marking Information

Ordering Information

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2

IR11682S

Description

IR11682 is a dual smart secondary-side rectifier driver IC designed to drive two N-Channel power MOSFETs

used as synchronous rectifiers in resonant converter applications. The IC can control one or more paralleled N

MOSFETs to emulate the behavior of Schottky diode rectifiers. The drain to source for each rectifier MOSFET

voltage is sensed differentially to determine the level of the current and the power switch is turned ON and

OFF in close proximity of the zero current transition. The anti shoot-through logic prevents both channels from

turning on the power switches at the same time. The cycle-by-cycle MOT protection circuit can automatically

detect no load condition and turn off gate driver output to avoid negative current flowing through the

MOSFETs. Ruggedness and noise immunity are accomplished using an advanced blanking scheme and

double-pulse suppression that allows reliable operation in fixed and variable frequency applications.

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3

IR11682S

Qualification Information^†

Industrial^††

Comments: This family of ICs has passed JEDEC’s

Industrial qualification. IR’s Consumer qualification level is

granted by extension of the higher Industrial level.

Qualification Level

MSL2^†††260°C

SOIC8N

Moisture Sensitivity Level

(per IPC/JEDEC J-STD-020)

Class B

Machine Model

Human Body Model

(per JEDEC standard JESD22-A115)

ESD

Class 2

(per EIA/JEDEC standard EIA/JESD22-A114)

Class 1, Level A

(per JESD78)

Yes

IC Latch-Up Test

RoHS Compliant

†

††

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

Higher qualification ratings may be available should the user have such requirements. Please contact

your International Rectifier sales representative for further information.

†††

Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

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4

IR11682S

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The

thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.

Parameters

Supply Voltage

Cont. Drain Sense Voltage

Pulse Drain Sense Voltage

Source Sense Voltage

Gate Voltage

Operating Junction Temperature

Storage Temperature

Thermal Resistance

Package Power Dissipation

Switching Frequency

Symbol

V_CC

V_D

V_S

V_GATE

T_J

T_S

Min.

-0.3

-1

-5

-3

-0.3

-40

-55

Max.

20

200

20

Units

V

°C

Remarks

20

V_CC=20V, Gate off

150

128

970

400

R_θJA

P_D

fsw

°C/W

mW

kHz

SOIC-8

SOIC-8, T_AMB=25°C

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions.

Symbol

V_CC

V_D1,V_D2

T_J

Definition

Min.

8.6

-3 ^†

-25

---

Max.

18

200

125

400

Units

Supply voltage

Drain Sense Voltage

V

Junction Temperature

Switching Frequency

°C

kHz

Fsw

-3V negative spike width 100ns

† V_D1,V_D2

≤

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5

IR11682S

Electrical Characteristics

VCC=15V and T_A= 25°C unless otherwise specified. The output volt age and current (V_Oand I_O) parameters

are referenced to GND (pin7).

Supply Section

Parameters

Supply Voltage Operating

Range

Symbol Min.

Typ.

Max.

Units

Remarks

V_CC

8.6

7.5

18

V

GBD

V_CCTurn On Threshold

V_CCTurn Off Threshold

(Under Voltage Lock Out)

V_{CC ON}

8.1

7.6

8.5

V_{CC UVLO}

7

8

V

V_CCTurn On/Off Hysteresis V_{CC HYST}

0.5

14

V

C_LOAD=1nF, f_SW= 400kHz

C_LOAD=4.7nF, f_SW= 400kHz

18

60

mA

Operating Current

I_CC

48

Quiescent Current

Start-up Current

I_QCC

2.6

4.3

140

I_{CC START}

µA V_CC=V_{CC ON}- 0.1V

Comparator Section

Parameters

Turn-off Threshold

Turn-on Threshold

Hysteresis

Symbol Min.

Typ.

-6

Max.

0

Units

mV

µA

Remarks

V_TH1

V_TH2

-12

-220

-140

141

1

-80

V_HYST

I_IBIAS1

I_IBIAS2

V_OFFSET

V_D= -50mV

V_D= 200V

GBD

Input Bias Current

10

50

2

Input Bias Current

10

µA

Comparator Input Offset

mV

One-Shot Section

Parameters

Blanking pulse duration

Symbol Min.

t_BLANK

Typ.

17

Max.

25

Units

µs

Remarks

8

2.5

5.4

40

V

V_CC=10V – GBD

V_CC=20V – GBD

Reset Threshold

Hysteresis

V_TH3

mV V_CC=10V – GBD

V_HYST3

Minimum On Time Section

Parameters

Minimum on time

Symbol Min.

T_Onmin

Typ.

Max.

Units

Remarks

600

850

1100

ns

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6

IR11682S

Electrical Characteristics

VCC=15V and T_A= 25°C unless otherwise specified. The output volt age and current (V_Oand I_O) parameters

are referenced to GND (pin7).

Gate Driver Section

Parameters

Gate Low Voltage

Gate High Voltage

Rise Time

Symbol Min.

V_GLO

Typ.

0.3

10.7

10

80

5

25

100

80

5

1.2

Max.

0.5

13.5

Units

V

ns

Ω

Remarks

I_GATE= 200mA

V_CC=12V-18V (internally clamped)

C_LOAD= 1nF

C_LOAD= 4.7nF

C_LOAD= 1nF

V_GTH

t_r1

8.5

t_r2

t_f1

t_f2

t_Don

t_Doff

r_up

Fall Time

C_LOAD= 4.7nF

Turn on Propagation Delay

Turn off Propagation Delay

Pull up Resistance

Pull down Resistance

Output Peak Current

(source)

200

120

V_DSto V_GATE-100mV overdrive

I_GATE= 15mA – GBD

I_GATE= -200mA – GBD

r_down

Ω

I_{O source}

I_{O sink}

1

4

A

C_LOAD= 1nF – GBD

Output Peak Current (sink)

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7

IR11682S

Functional Block Diagram

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8

IR11682S

I/O Pin Equivalent Circuit Diagram

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9

IR11682S

Lead Definitions

PIN#

Symbol

GATE1

VCC

Description

Gate Drive Output 1

Supply Voltage

Sync FET 1 Source Voltage Sense

Sync FET 1 Drain Voltage Sense

Sync FET 2 Drain Voltage Sense

Sync FET 2 Source Voltage Sense

Analog and Power Ground

Gate Drive Output 2

1

2

3

4

5

6

7

8

VS1

VD1

VD2

VS2

GND

GATE2

Lead Assignments

1

2

3

4

GATE1

VCC

VS1

8

7

6

5

GATE2

GND

VS2

VD2

VD1

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10

IR11682S

Detailed Pin Description

VCC: Power Supply

This is the supply voltage pin of the IC and it is monitored by the under voltage lockout circuit. It is possible to

turn off the IC by pulling this pin below the minimum turn off threshold voltage, without damage to the IC.

To prevent noise problems, a bypass ceramic capacitor connected to Vcc and COM should be placed as

close as possible to the IR11682. This pin is not internally clamped.

GND: Ground

This is ground potential pin of the integrated control circuit. The internal devices and gate driver are

referenced to this point.

VD1 and VD2: Drain Voltage Sense

These are the two high-voltage pins used to sense the drain voltage of the two SR power MOSFETs. Routing

between the drain of the MOSFET and the IC pin must be particularly optimized.

Additional RC filter in not necessary but could be added to VD1 and VD2 pins to increase noise immunity.

For applications which VD voltage exceeds 100V, a 1Kohm to 2Kohm VD resistor is recommended to be

added between the drain of SR MOSFET and VD pin. The VD resistor helps to limit the switching loss of VD

pins.

VS1 and VS2: Source Voltage Sense

These are the two differential sense pins for the two source pins of the two SR power MOSFETs. This pin

must not be connected directly to the GND pin (pin 7) but must be used to create a Kelvin contact as close as

possible to the power MOSFET source pin.

GATE1 and GATE2: Gate Drive Outputs

These are the two gate drive outputs of the IC. The gate voltage is internally clamped and has a +1A/-4A

peak drive capability. Although this pin can be directly connected to the synchronous rectifier (SR) MOSFET

gate, the use of gate resistor is recommended (specifically when putting multiple MOSFETs in parallel). Care

must be taken in order to keep the gate loop as short and as small as possible in order to achieve optimal

switching performance.

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11

IR11682S

Application Information and Additional Details

State Diagram

POWER ON

GateꢀInactive

UVLOꢀMODE

VCCꢀ<ꢀVCCon

GateꢀInactive

I_CC=ꢀI_CCꢀSTART

VCC > VCCon

& V_DS>V_TH3

VCC < VCCuvlo

NORMAL

GateꢀActive

GateꢀPWꢀ≥ MOT

CycleꢀbyꢀCycleꢀMOTꢀCheckꢀEnabled

V_DS>V_TH1@ MOT

V_DS<V_TH1@ MOT

MOT PROTECTION

MODE

GateꢀOutputꢀDisabled

UVLO Mode:

The IC is in the UVLO mode when the VCC pin voltage is below VCCUVLO. The UVLO mode is accessible

from any other state of operation. In the UVLO state, most of the internal circuitry is unbiased and the IC

draws a quiescent current of ICCSTART.

The IC remains in the UVLO condition until the voltage on the VCC pin exceeds the VCC turn on threshold

voltage, VCC ON.

Normal Mode:

Once Vcc exceeds the UVLO voltage, the IC is ready to go into Normal mode. The GATE outputs are

activated when the VDS sensed on the MOSFET crosses VTH3. This function will prevent the GATE to turn-

on towards the end of a switching cycle and prevent reverse current in MOT time. In Normal mode the gate

drivers are operating and the IC will draw a maximum of ICC from the supply voltage source.

MOT Protection Mode

If the secondary current conduction time is shorter than the MOT (Minimum On Time) time, the next driver

output is disabled. This function can avoid reverse current that occurs when the system works at very light/no

load conditions and reduce system standby power consumption by disabling GATE outputs. The IC

automatically goes back to normal operation mode once the load increases to a level and the secondary

current conduction time is longer than MOT.

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12

IR11682S

General Description

The IR11682 Dual Smart Rectifier controller IC is the industry first dedicated high-voltage controller IC for

synchronous rectification in resonant converter applications. The IC can emulate the operation of the two

secondary rectifier diodes by correctly driving the synchronous rectifier (SR) MOSFETs in the two secondary

legs.

The core of this device are two high-voltage, high speed comparators which sense the drain to source voltage

of the MOSFETs differentially. The device current is sensed using the R_DSONas a shunt resistance and the

GATE pin of the MOSFET is driven accordingly. Dedicated internal logic then manages to turn the power

device on and off in close proximity of the zero current transition.

IR11682 further simplifies synchronous rectifier control by offering the following power management features:

-Wide VCC operating range allows the IC to be directly powered from the converter output

-Shoot through protection logic that prevents both the GATE outputs from the IC to be high at the same time

-Device turn ON and OFF in close proximity of the zero current transition with low turn-on and turn-off

propagation delays; eliminates reactive power flow between the output capacitors and power transformer

-Internally clamped gate driver outputs that significantly reduce gate losses.

The SmartRectifier™ control technique is based on sensing the voltage across the MOSFET and comparing it

with two negative thresholds to determine the turn on and off transitions for the device. The rectifier current is

sensed by the input comparators using the power MOSFET R_DSONas a shunt resistance and its GATE is

driven depending on the level of the sensed voltage vs. the 3 thresholds shown below.

V_Gate

V_DS

V_TH2

V_TH1

V_TH3

Figure 1: Input comparator thresholds

Turn-on phase

When the conduction phase of the SR FET is initiated, current will start flowing through its body diode,

generating a negative V_DSvoltage across it. The body diode has generally a much higher voltage drop than the

one caused by the MOSFET on resistance and therefore will trigger the turn-on threshold V_TH2

.

When V_TH2is triggered, IR11682 will drive the gate of MOSFET on which will in turn cause the conduction

voltage VDS to drop down to I_D*R_DSON. This drop is usually accompanied by some amount of ringing, that

could trigger the input comparator to turn off; hence, a fixed Minimum On Time (MOT) blanking period is used

that will maintain the power MOSFET on for a minimum amount of time.

The fixed MOT limits the minimum conduction time of the secondary rectifiers and hence, the maximum

switching frequency of the converter.

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13

IR11682S

Turn-off phase

Once the SR MOSFET has been turned on, it will remain on until the rectified current will decay to the level

where V_DSwill cross the turn-off threshold V_TH1

.

Since the device currents are sinusoidal here, the device VDS will cross the V_TH1threshold with a relatively low

dV/dt. Once the threshold is crossed, the current will start flowing again through the body diode, causing the

VDS voltage to jump negative. Depending on the amount of residual current, VDS may once again trigger the

turn-on threshold; hence, VTH2 is blanked for a time duration t_BLANKafter VTH1 is triggered. When the device

VDS crosses the positive reset threshold VTH3, t_BLANKis terminated and the IC is ready for next conduction

cycle as shown below.

V_TH3

I_DS

V_DS

T1

T2

V_TH1

V_TH2

GateꢀDrive

Blanking

MOT

t_BLANK

time

Figure 2: Secondary currents and voltages

MOT protection

At very light load or no load condition, the current in SR FET will become discontinuous and could be shorter

than MOT time in some system. If this happens, the SR FET current will flow from drain to source at the end

of MOT. The reverse current discharges output capacitor; stores the energy in transformer and causes

resonant on VDS voltage once the SR FET turns off. The resonant could turn on the gate of IR11682, caused

more reverse current and thus subsequent multi false triggering as shown below in Figure 3.

Figure 3: Waveform without MOT protection

The cycle-by-cycle MOT protection circuit can detect the reverse current situation and disable the next output

gate pulse to avoid this issue. The internal comparator and MOT pulse generator still work under the

protection mode. So the circuit can continuously monitor the load current and come back to normal working

mode once the load current conduction time increased to longer than MOT. This circuit helps to reduce

standby power losses. It also can prevent voltage spike that caused by false triggering at light load.

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14

IR11682S

Figure 4: Waveform under MOT protection mode

General Timing Waveform

VCC

VCC ON

VCC UVLO

t

UVLO

NORMAL

UVLO

Figure 5: Vcc UVLO

V_TH1

V_DS

V_TH2

t_Don

t_Doff

V_Gate

90%

50%

10%

t_rise

t_fall

Figure 6: Timing waveform

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15

IR11682S

9.0 V

8.5 V

8.0 V

7.5 V

7.0 V

10

1

0.1

0.01

VCC ON

VCC UVLO

5.0 V 7.5 V 10.0 V 12.5 V 15.0 V 17.5 V

-50 °C

0 °C

50 °C

Temperature

100 °C

150 °C

Supply voltage

Figure 7: Supply Current vs. Supply Voltage

Figure 8: Undervoltage Lockout vs. Temperature

Icc @400KHz, C_LOAD=1nF

13.8

I_QCC

2.7

13.7

13.6

13.5

13.4

13.3

2.6

2.5

2.4

2.3

2.2

-50 °C

0 °C

50 °C

100 °C

150 °C

-50 °C

0 °C

50 °C

100 °C

150 °C

Temperature

Figure 9: Icc Quiescent Currrent vs. Temperature

Figure 10: Icc Supply Currrent @1nF Load vs.

Temperature

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16

IR11682S

-3.4

-3.6

-3.8

-4.0

-4.2

-4.4

-4.6

-4.8

-138.0

-139.0

-140.0

-141.0

-142.0

-143.0

-144.0

-145.0

Ch2

Ch1

Ch2

Ch1

-50 °C

0 °C

50 °C

100 °C

150 °C

-50 °C

0 °C

50 °C

Temperature

100 °C

150 °C

Temperature

Figure 12: V_TH2vs. Temperature

Figure 11: V_TH1vs. Temperature

900 ns

-134.0

890 ns

880 ns

870 ns

860 ns

850 ns

840 ns

830 ns

820 ns

-135.0

-136.0

-137.0

-138.0

-139.0

-140.0

-141.0

Ch2

Ch1

MOT_Ch1

MOT_Ch2

-50 °C

0 °C

50 °C

100 °C

150 °C

-50 °C

0 °C

50 °C

100 °C

150 °C

Temperature

Figure 13: Comparator Hysteresis vs.

Temperature

Figure 14: MOT vs Temperature

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17

IR11682S

125 ns

120 ns

115 ns

110 ns

105 ns

100 ns

95 ns

90 ns

85 ns

80 ns

75 ns

70 ns

Ch1 Turn-off Propagation Delay

Ch2 Turn-off Propagation Delay

Ch1 Turn-on Propagation Delay

Ch2 Turn-on Propagation Delay

90 ns

-50 °C

0 °C

50 °C

100 °C

150 °C

-50 °C

0 °C

50 °C

100 °C

150 °C

Temperature

Figure 15: Turn-on Propagation Delay vs.

Temperature

Figure 16: Turn-off Propagation Delay vs.

Temperature

11.5 V

10 ns

9 ns

8 ns

Ch1 VGH@Vcc=12V

Ch2 VGH@Vcc=12V

Ch1 VGH@Vcc=18V

Ch2 VGH@Vcc=18V

11.0 V

Tr_Ch1

Tf_Ch1

Tr_Ch2

Tf_Ch2

8 ns

7 ns

6 ns

5 ns

10.5 V

10.0 V

-50 °C

0 °C

50 °C

100 °C

150 °C

-50 °C

0 °C

50 °C

100 °C

150 °C

Temperature

Figure 18: Gate Output Tr and Tf time @ 1nF

Load vs. Temperature

Figure 17: Gate Clamping Voltage vs.

Temperature

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18

IR11682S

Package Details: SOIC8N

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19

IR11682S

Tape and Reel Details: SOIC8N

LOADED TAPE FEED DIRECTION

A

B

H

D

F

C

NOTE : CONTROLLING

DIMENSION IN MM

E

G

CARRIER TAPE DIMENSION FOR 8SOICN

Metric

Imperial

Min

0.311

0.153

0.46

Code

A

B

C

D

E

F

G

H

Min

7.90

3.90

11.70

5.45

6.30

5.10

1.50

Max

8.10

4.10

12.30

5.55

6.50

5.30

n/a

Max

0.318

0.161

0.484

0.218

0.255

0.208

n/a

0.214

0.248

0.200

0.059

1.60

0.062

F

D

B

C

A

E

G

H

REEL DIMENSIONS FOR 8SOICN

Metric

Imperial

Code

A

B

C

D

E

F

G

H

Min

329.60

20.95

12.80

1.95

98.00

n/a

14.50

12.40

Max

330.25

21.45

13.20

2.45

102.00

18.40

17.10

14.40

Min

12.976

0.824

0.503

0.767

3.858

n/a

Max

13.001

0.844

0.519

0.096

4.015

0.724

0.673

0.566

0.570

0.488

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20

IR11682S

Part Marking Information

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21

IR11682S

Ordering Information

Standard Pack

Base Part Number

Package Type

Complete Part Number

Form

Quantity

Tube/Bulk

95

IR11682SPBF

SOIC8N

IR11682

Tape and Reel

2500

IR11682STRPBF

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no

responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any

infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by

implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are

subject to change without notice. This document supersedes and replaces all information previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

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22


型号：	IR11682SPBF
厂家：	Infineon
描述：	DUAL SmartRectifier DRIVER IC 200V proprietary IC technology 双智能整流驱动IC专有200V IC技术驱动
文件：	总22页 (文件大小：381K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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