IPD70N04S307ATMA1 [INFINEON]

Power Field-Effect Transistor, 82A I(D), 40V, 0.006ohm, 1-Element, N-Channel, Silicon, Metal-Oxide Semiconductor FET, TO-252, GREEN, PLASTIC PACKAGE-3;
IPD70N04S307ATMA1
型号: IPD70N04S307ATMA1
厂家: Infineon    Infineon
描述:

Power Field-Effect Transistor, 82A I(D), 40V, 0.006ohm, 1-Element, N-Channel, Silicon, Metal-Oxide Semiconductor FET, TO-252, GREEN, PLASTIC PACKAGE-3

脉冲 晶体管
文件: 总9页 (文件大小:182K)
中文:  中文翻译
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IPD70N04S3-07  
OptiMOS®-T Power-Transistor  
Product Summary  
VDS  
40  
6.0  
82  
V
R DS(on),max  
I D  
m  
A
Features  
• N-channel - Enhancement mode  
PG-TO252-3-11  
• Automotive AEC Q101 qualified  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
• Green package (RoHS compliant)  
• 100% Avalanche tested  
Type  
Package  
Marking  
IPD70N04S3-07  
PG-TO252-3-11 QN0407  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
I D  
T C=25 °C, VGS=10 V  
T C=100 °C,  
Continuous drain current  
82  
A
58  
V
GS=10 V1)  
Pulsed drain current1)  
I D,pulse  
EAS  
T C=25 °C  
I D=50 A  
280  
145  
Avalanche energy, single pulse  
Gate source voltage  
mJ  
V
VGS  
±20  
Ptot  
T C=25 °C  
Power dissipation  
79  
W
°C  
T j, T stg  
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-55 ... +175  
55/175/56  
Rev. 1.0  
page 1  
2007-05-03  
IPD70N04S3-07  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics1)  
R thJC  
R thJA  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
1.9  
62  
40  
K/W  
minimal footprint  
6 cm2 cooling area2)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS  
VGS(th)  
V
V
GS=0 V, I D= 1 mA  
DS=VGS, I D=50 µA  
Drain-source breakdown voltage  
Gate threshold voltage  
40  
-
-
V
2.1  
3.0  
4.0  
V
DS=40 V, VGS=0 V,  
I DSS  
Zero gate voltage drain current  
-
-
-
-
1
µA  
T j=25 °C  
V
DS=40 V, VGS=0 V,  
100  
T j=125 °C2)  
I GSS  
V
V
GS=20 V, VDS=0 V  
GS=10 V, I D=70 A  
Gate-source leakage current  
-
-
-
100 nA  
RDS(on)  
Drain-source on-state resistance  
4.9  
6.0  
m  
Rev. 1.0  
page 2  
2007-05-03  
IPD70N04S3-07  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics1)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
2050  
610  
90  
13  
8
2700 pF  
800  
V
GS=0 V, VDS=25 V,  
f =1 MHz  
130  
-
-
-
-
ns  
V
DD=20 V, VGS=10 V,  
I D=70 A, R G=3.5 Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
17  
7
Gate Charge Characteristics1)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
12  
8
16  
14  
40  
-
nC  
Q gd  
V
V
DD=32 V, I D=70 A,  
GS=0 to 10 V  
Q g  
30  
6.0  
Vplateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current1)  
Diode pulse current1)  
I S  
-
-
-
-
70  
T C=25 °C  
I S,pulse  
280  
V
GS=0 V, I F=70 A,  
VSD  
Diode forward voltage  
-
1
1.3  
V
T j=25 °C  
Reverse recovery time1)  
Reverse recovery charge1)  
t rr  
-
-
34  
36  
-
-
ns  
VR=20 V, I F=I S,  
diF/dt =100 A/µs  
Q rr  
nC  
1) Defined by design. Not subject to production test.  
2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.0  
page 3  
2007-05-03  
IPD70N04S3-07  
1 Power dissipation  
2 Drain current  
P
tot = f(T C); VGS 6 V  
I D = f(T C); VGS 6 V  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
80  
60  
40  
20  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
C [°C]  
T
C [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
Z
parameter: D =t p/T  
101  
1000  
100  
10  
1 µs  
0.5  
100  
10 µs  
100 µs  
0.1  
0.05  
10-1  
1 ms  
0.01  
10-2  
single pulse  
10-3  
1
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
t p [s]  
V
DS [V]  
Rev. 1.0  
page 4  
2007-05-03  
IPD70N04S3-07  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
DS(on) = f(I D); T j = 25 °C  
R
parameter: VGS  
200  
20  
6 V  
5.5 V  
6.5 V  
10 V  
18  
16  
14  
12  
10  
8
160  
120  
80  
40  
0
7 V  
6.5 V  
6 V  
7 V  
6
5.5 V  
5 V  
10 V  
4
2
0
20  
40  
60  
D [A]  
80  
100  
120  
0
2
4
6
8
I
V
DS [V]  
7 Typ. transfer characteristics  
I D = f(VGS); VDS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R
DS(on) = f(T j); I D = 70 A; VGS = 10 V  
320  
280  
240  
200  
160  
120  
80  
9
8
7
6
5
4
3
2
-55 °C  
25 °C  
175 °C  
40  
0
2
3
4
5
6
7
8
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
V
GS [V]  
Rev. 1.0  
page 5  
2007-05-03  
IPD70N04S3-07  
9 Typ. gate threshold voltage  
GS(th) = f(T j); VGS = VDS  
10 Typ. capacitances  
V
C = f(VDS); VGS = 0 V; f = 1 MHz  
parameter: I D  
4
104  
103  
102  
101  
3.5  
3
Ciss  
500 µA  
Coss  
50 µA  
2.5  
2
Crss  
1.5  
1
0
5
10  
15  
20  
25  
30  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
V
DS [V]  
11 Typical forward diode characteristicis  
12 Typ. avalanche characteristics  
A S= f(t AV  
IF = f(VSD)  
I
)
parameter: T j  
parameter: Tj(start)  
103  
100  
25 °C  
100 °C  
150 °C  
102  
10  
25 °C  
175 °C  
101  
100  
1
1
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
10  
100  
1000  
V
SD [V]  
t AV [µs]  
Rev. 1.0  
page 6  
2007-05-03  
IPD70N04S3-07  
13 Typical avalanche energy  
AS = f(T j)  
14 Typ. drain-source breakdown voltage  
E
V
BR(DSS) = f(T j); I D = 1 mA  
parameter: I D  
55  
700  
600  
50  
45  
40  
35  
30  
12.5 A  
500  
400  
300  
25 A  
200  
50 A  
100  
0
-60  
-20  
20  
60  
100  
140  
180  
25  
75  
125  
175  
T j [°C]  
T j [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
V
GS = f(Q gate); I D = 70 A pulsed  
parameter: VDD  
12  
V GS  
32 V  
8 V  
Q g  
10  
8
6
V gs(th)  
4
2
Q g(th)  
Q sw  
Q gd  
Q gate  
Q gs  
0
0
10  
20  
30  
40  
Q
gate [nC]  
Rev. 1.0  
page 7  
2007-05-03  
IPD70N04S3-07  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2007  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein,  
any typical values stated herein and/or any information regarding the application of the device,  
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including  
without limitation warranties of noninfringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices please  
contact your nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information  
on the types in question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably  
be expected to cause the failure of that life-support device or system, or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be  
implanted in the human body, or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be  
endangered.  
Rev. 1.0  
page 8  
2007-05-03  
IPD70N04S3-07  
Revision History  
Version  
Date  
Changes  
Rev. 1.0  
page 9  
2007-05-03  

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