ESD5V5U5ULC [INFINEON]
Ultra-low Capacitance ESD / Transient / Surge Protection Array;
| 型号： | ESD5V5U5ULC |
| 厂家： | 
Infineon |
| 描述： | Ultra-low Capacitance ESD / Transient / Surge Protection Array |
| 文件： | 总16页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVS Diodes
Transient Voltage Suppressor Diodes
ESD5V5U5ULC
Ultra-low Capacitance ESD / Transient / Surge Protection Array
ESD5V5U5ULC
Data Sheet
Revision 1.3, 2015-07-16
Final
Power Management & Multimarket
Edition 2015-07-16
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD5V5U5ULC
Revision History: Rev. 1.2, 2013-02-07
Page or Item
Subjects (major changes since previous revision)
Revision 1.3, 2015-07-16
14
Marking drawing updated
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Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2010-06-09
Final Data Sheet
3
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Ultra-low Capacitance ESD / Transient / Surge Protection Array
1
Ultra-low Capacitance ESD / Transient / Surge Protection Array
1.1
Features
•
ESD / Transient protection of high speed data lines exceeding
– IEC61000-4-2 (ESD): ±25 kV (air / contact)
– IEC61000-4-4 (EFT): ±2.5 kV / ±50 A (5/50 ns)
– IEC61000-4-5 (surge): ±6 A (8/20 μs)
•
•
•
•
•
•
Maximum working voltage: VRWM = 5.5 V
Extremely low capacitance CL = 0.45 pF I/O to GND (typical)
Very low dynamic resistance: RDYN I/O to GND = 0.2 Ω (typical)
Very low reverse clamping voltage: VCL = 9 V (typical) at IPP = 16 A
Protection of VBUS with one line freely selectable
Pb-free (RoHS compliant) package
1.2
Application Examples
•
•
•
Protection of all I/O and VBUS lines in dual USB2.0 ports
10/100/100 Ethernet
DVI, HDM, FireWire
1.3
Product Description
Pin 4
Pin 1
Pin 3
Pin 5
Pin 6
Pin 6
Pin 5
Pin 4
SC74
GND
Pin 2
Pin 1
Pin 2
Pin 3
b) Schematic diagram
a) Pin configuration
ESD5V5U5ULC_PinConf_and_SchematicDiag.vsd
Figure 1
Pin Configuration and Schematic Diagram
Ordering Information
Table 1
Type
Package
Configuration
Marking code
ESD5V5U5ULC
SC74
5 lines, uni-directional
20
Final Data Sheet
4
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Characteristics
2
Characteristics
Table 2
Maximum Rating at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Unit
Min.
-25
-6
Typ.
Max.
25
ESD contact discharge1)
Peak pulse current (tp = 8/20 μs)2) IPP
VESD
–
–
–
–
kV
A
6
Operating temperature range
Storage temperature
TOP
Tstg
-40
-65
125
150
°C
°C
1)
VESD according to IEC61000-4-2
2) IPP according to IEC61000-4-5
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
2.1
Electrical Characteristics at TA = 25 °C, unless otherwise specified
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ꢀꢁꢋ
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ꢂ
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ꢀ
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ꢑꢑꢑ !ꢂꢒꢊꢊꢋꢂꢆꢇꢁꢈꢉꢄꢊꢋ
ꢃꢄꢅ
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ꢆꢇ
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ꢑꢑꢑ ꢌꢋꢇꢋꢂꢍꢋꢆꢎꢈꢄꢝꢖꢒꢐꢊꢆꢇꢁꢈꢉꢄꢊꢋ
ꢑꢑꢑ !#$ꢆꢇꢁꢈꢉꢄꢊꢋ
ꢑꢑꢑ ꢌꢋꢇꢋꢂꢍꢋꢆꢃꢁꢂꢘꢒꢐꢊꢆꢎꢏꢂꢂꢋꢐꢉꢆꢝꢄ"ꢛ
ꢑꢑꢑ $ꢋꢄꢘꢆꢖꢏꢈꢍꢋꢆꢎꢏꢂꢂꢋꢐꢉ
ꢑꢑꢑ !#$ꢆꢎꢏꢂꢂꢋꢐꢉ
ꢆꢀ
ꢆꢇ
ꢂꢋ
ꢂꢃꢄꢅ
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Figure 2
Definitions of Electrical Characteristics[1]
Final Data Sheet
5
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Characteristics
Table 3
DC Characteristics at TA = 25 °C, unless otherwise specified
Symbol Values
Typ.
Parameter
Unit
Note /
Test Condition
Min.
Max.
5.5
Reverse working voltage VRWM
Reverse current IR
–
–
–
V
I/O to GND
<1
100
nA
VR = 5.5 V,
I/O to GND
Table 4
RF Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Typ.
Unit
Note /
Test Condition
Min.
Max.
Line capacitance
Line capacitance
CL
–
0.45
0.23
0.25
1
pF
pF
pF
VR = 0 V, f = 1 MHz,
I/O to GND
–
–
0.5
–
VR = 0 V, f = 1 MHz,
I/O to I/O
CL
VR = 0 V,
f = 825 MHz,
I/O to GND
–
0.13
–
pF
VR = 0 V,
f = 825 MHz,
I/O to I/O
Capacitance variation
between I/O and GND
∆Ci/o-GND
∆Ci/o-i/o
–
–
0.02
0.01
–
–
pF
pF
VR = 0 V, f = 1 MHz,
I/O to GND
Capacitance variation
between I/O
VR = 0 V, f = 1 MHz,
I/O to I/O
Final Data Sheet
6
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Characteristics
Table 5
ESD Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Typ.
Unit
Note /
Test Condition
Min.
Max.
Reverse clamping
voltage1)
VCL
–
9
–
V
V
V
I
PP = 1 A, tp = 8/20 μs,
I/O pin to GND
PP = 3 A, tp = 8/20 μs,
I/O pin to GND
PP = 16 A,
–
–
12
8.9
–
–
I
Reverse clamping
voltage2)[2]
VCL
I
tp = 100 ns,
I/O pin to GND
–
11.5
–
V
I
PP = 30 A,
tp = 100 ns,
I/O pin to GND
Forward clamping
voltage1)
VFC
–
–
–
1.75
2.5
–
–
–
V
V
V
I
PP = 1 A, tp = 8/20 μs,
GND pin to I/O
I
PP = 3 A,tp = 8/20 μs,
GND pin to I/O
IPP = 16 A,
Forward clamping
voltage2)[2]
VFC
5.4
tp = 100 ns,
GND pin to I/O
–
9.2
–
V
I
PP = 30 A,
tp = 100 ns,
GND pin to I/O
Dynamic resistance
RDYN, I/O
–
–
0.2
0.3
–
–
Ω
Ω
I/O to GND2)[2]
to GND
Dynamic resistance
GND to I/O2)[2]
RDYN,
GND to I/O
1) IPP according to IEC61000-4-5
2) Please refer to Application Note AN210[2]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns
to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between IPP1 = 10 A and
I
PP2 = 40 A.
Final Data Sheet
7
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Characteristics
2.2
Typical Characteristics at TA = 25 °C, unless otherwise specified
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VR [V]
Figure 3
Line capacitance CL = f(VR) at f = 825 MHz
0.6
0.5
0.4
I/O to GND
0.3
0.2
0.1
0
I/O to I/O
106
107
108
109
1010
f [Hz]
Figure 4
Line capacitance CL = f(f), VR = 0 V
Final Data Sheet
8
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Characteristics
0
-5
-10
-15
-20
105
106
107
108
109
1010
f [Hz]
Figure 5
Insertion loss IL = f(f), VR = 0 V
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
0
0.5
V [V]
1
F
Figure 6
Forward characteristic, IF = f(VF), current forced
Final Data Sheet
9
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Characteristics
10-7
10-8
10-9
10-10
10-11
10-12
-50
-25
0
25
50
75
100
125
150
TA [°C]
Figure 7
Reverse current IR = f(TA), VR = 5.5 V (typical)
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
0
5
10
VR [V]
Figure 8
Reverse characteristic, IR = (VR), voltage forced
Final Data Sheet
10
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Characteristics
60
50
40
30
20
10
0
30
25
20
15
10
5
ESD5V5U5ULC
RDYN
RDYN=0.2Ω
0
5
10
15
20
25
VTLP [V]
Figure 9
TLP characteristic I/O to GND Note: [2]
60
30
25
20
15
10
5
ESD5V5U5ULC
RDYN
50
40
30
20
10
0
RDYN=0.3Ω
0
5
10
15
20
25
VTLP [V]
Figure 10 TLP characteristic GND to I/O Note: [2]
Note:TLP parameter: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of
dynamic resistance using least squares fit of TLP charactertistic between IPP1 = 10 A and IPP2 = 40 A. The
equivalent stress level VIEC according IEC 61000-4-2 (R = 330 Ω , C = 150 pF) is calculated at the broad
peak of the IEC waveform at t = 30 ns with 2 A / kV
Final Data Sheet
11
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Application Information
3
Application Information
ESD5V5U5ULC_Ethernet_application .vsd
Gigabit Ethernet
Transceiver (PHY)
HOST
RJ45
Quad Transformer
Ethernet connector
RX1
primary
ESD current
1 : 1
TX1
secondary
Secondary ESD/surge ESD current
protection
75 Ohm Res
common 2nF cap
Res
Gigabit Ethernet
Transceiver (PHY)
Device
RJ45
Quad Transformer
Ethernet connector
RX1
primary
ESD current
1 : 1
TX1
secondary
Secondary ESD/surge
75 Ohm Res
common 2nF cap
ESD current
Res
protection
Figure 11 Ethernet
ESD5V5U5ULC_USB20_application .vsd
Device
controller
Host
controller
TVS ESD
diodes array
D+
D-
D+
D1+
D1+
Data #1
IN / OUT
Data #1
IN / OUT
D1-
D1-
Vcc
D-
USB2.0 Host1
LS/FS/HS
USB2.0 Device1
LS/FS/HS
GND
USB2.0 cable#1
Vcc
Vcc
USBConnectors
USB2.0 Host2
LS/FS/HS
USB2.0 Device2
LS/FS/HS
USB2.0 cable#2
GND
Vcc
D+
D-
D+
D-
Data #2
IN / OUT
D2+
D2-
D2+
D2-
Data #2
IN / OUT
TVS ESD
diodes array
Figure 12 USB2.0
Final Data Sheet
12
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Ordering Information Scheme (Examples)
4
Ordering Information Scheme (Examples)
ESD 0P1 RF - XX YY
Package
XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins)
YY = Package family:
LS = TSSLP
LRH = TSLP
For Radio Frequency Applications
Line Capacitance CL in pF: (i.e.: 0P1 = 0.1pF)
ESD 5V3 U n U - XX YY
Package or Application
XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins)
YY = Package family:
LS = TSSLP
LRH = TSLP
S = SOT363
U = SC74
XX = Application family:
LC = Low Clamp
HDMI
Uni- / Bi-directional or Rail to Rail protection
Number of protected lines(i.e.: 1 = 1 line; 4 = 4 lines)
Capacitance: Standard (>10pF), Low (<10pF), Ultra-low (<1pF)
Maximum working voltage VRWM in V: (i.e.: 5V3 = 5.3V)
Figure 13 Ordering information scheme
Final Data Sheet
13
Revision 1.3, 2015-07-16
ESD5V5U5ULC
Package Information
5
Package Information
5.1
PG-SC74 (mm)
0.2
2.9
B
1.1 MAX.
(2.25)
+0.1
0.15
(0.35)
-0.06
6
1
5
2
4
3
+0.1
A
0.35
-0.05
M
0.2
B 6x
Pin 1
marking
0.1 MAX.
0.95
M
0.2
A
1.9
SC74-PO V04
Figure 14 PG-SC74: Package overview
0.5
0.95
4
SC74-FPR V04
Figure 15 PG-SC74: Footprint
0.2
3.15
1.15
Pin 1
marking
SC74-TP
Figure 16 PG-SC74: Packing
Manufacturer
2005, June
Date code (YM)
Pin 1 marking
Laser marking
BCW66H
Type code
SC74-MK V04
Figure 17 PG-SC74: Marking (example)
Final Data Sheet
14
Revision 1.3, 2015-07-16
ESD5V5U5ULC
References
References
[1] On-chip ESD protection for integrated circuits, Albert Z. H. Wang, ISBN:0-7923-7647-1
[2] Infineon Technologie AG - Application Note AN210: Effective ESD Protection Design at System Level
Using VF-TLP Characterization Methodology
Final Data Sheet
15
Revision 1.3, 2015-07-16
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
相关型号：
ESD5Z12
Trans Voltage Suppressor Diode, 240W, 12V V(RWM), Unidirectional, 1 Element, Silicon,
DIOTEC
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