AUIRLS3036-7TRL [INFINEON]
HEXFETPower MOSFET; ?? HEXFET功率MOSFET
| 型号： | AUIRLS3036-7TRL |
| 厂家： | 
Infineon |
| 描述： | HEXFETPower MOSFET |
| 文件： | 总12页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97719A
AUTOMOTIVE GRADE
AUIRLS3036-7P
HEXFET® Power MOSFET
Features
●
●
●
●
●
●
●
●
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
D
VDSS
RDS(on) typ.
60V
1.5m
max.
ID (Silicon Limited)
ID (Package Limited)
1.9m
300A
G
240A
S
Description
SpecificallydesignedforAutomotiveapplications,thisHEXFET®
Power MOSFET utilizes the latest processing techniques to
achieveextremelylowon-resistancepersiliconarea. Additional
features of this design are a 175°C junction operating
temperature, fast switching speed and improved repetitive
avalanche rating . These features combine to make this design
an extremely efficient and reliable device for use in Automotive
D
S
S
S
S
S
applications and a wide variety of other applications.
G
D2Pak 7 Pin
AUIRLS3036-7P
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; and
functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified.
Symbol
ID @ TC = 25°C
Parameter
Max.
300
210
240
1000
380
2.5
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
ID @ TC = 100°C
ID @ TC = 25°C
IDM
A
PD @TC = 25°C
W
Maximum Power Dissipation
Linear Derating Factor
W/°C
V
VGS
EAS
IAR
± 16
300
Gate-to-Source Voltage
mJ
A
Single Pulse Avalanche Energy (Thermally Limited)
Avalanche Current
See Fig. 14, 15, 22a, 22b
Repetitive Avalanche Energy
EAR
mJ
8.1
-55 to + 175
300
Peak Diode Recovery
dv/dt
TJ
V/ns
Operating Junction and
TSTG
°C
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.40
40
Units
°C/W
R
Junction-to-Case
JC
RJA
–––
Junction-to-Ambient (PCB Mount, steady state)
HEXFET® is a registered trademark of International Rectifier.
*Qualification standards can be found at http://www.irf.com/
www.irf.com
1
11/29/11
AUIRLS3036-7P
Static Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
60 ––– –––
––– 0.059 ––– V/°C Reference to 25°C, ID = 5mA
Conditions
VGS = 0V, ID = 250μA
V
V
/ T
(BR)DSS
Breakdown Voltage Temp. Coefficient
J
–––
–––
1.0
1.5
1.7
–––
1.9
2.2
2.5
VGS = 10V, ID = 180A
RDS(on)
Static Drain-to-Source On-Resistance
m
V
GS = 4.5V, ID = 150A
VGS(th)
Gate Threshold Voltage
V
S
VDS = VGS, ID = 250μA
gfs
Forward Transconductance
390 ––– –––
VDS = 10V, ID = 180A
RG(int)
IDSS
Internal Gate Resistance
Drain-to-Source Leakage Current
–––
1.9
–––
20
––– –––
VDS = 60V, VGS = 0V
μA
––– ––– 250
––– ––– 100
––– ––– -100
VDS = 60V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
VGS = 16V
nA
VGS = -16V
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
––– 110 160
Conditions
Qg
Total Gate Charge
ID = 180A
VDS = 30V
VGS = 4.5V
Qgs
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
–––
–––
–––
–––
33
53
57
81
–––
–––
–––
–––
nC
ns
Qgd
Qsync
ID = 180A, VDS =0V, VGS = 4.5V
VDD = 39V
td(on)
tr
––– 540 –––
––– 89 –––
ID = 180A
td(off)
Turn-Off Delay Time
Fall Time
R = 2.1
G
VGS = 4.5V
tf
––– 170 –––
––– 11270 –––
––– 1025 –––
––– 520 –––
––– 1460 –––
––– 1630 –––
Ciss
Input Capacitance
VGS = 0V
Coss
Output Capacitance
Reverse Transfer Capacitance
VDS = 50V
Crss
ƒ = 1.0MHz
pF
Coss eff. (ER)
Coss eff. (TR)
VGS = 0V, VDS = 0V to 48V
VGS = 0V, VDS = 0V to 48V
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
D
S
IS
Continuous Source Current
––– –––
MOSFET symbol
300
(Body Diode)
Pulsed Source Current
(Body Diode)
showing the
integral reverse
A
––– –––
G
ISM
1000
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
V
TJ = 25°C, IS = 180A, VGS = 0V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 51V,
IF = 180A
di/dt = 100A/μs
–––
–––
57
60
ns
Qrr
Reverse Recovery Charge
––– 140 –––
––– 160 –––
nC
A
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
4.6
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
ꢀ Pulse width 400μs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 195A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniquea refer to applocation
note # AN- 994 echniques refer to application note #AN-994.
R is measured at TJ approximately 90°C.
.
.
Limited by TJmax, starting TJ = 25°C, L = 0.018mH
RG = 25, IAS = 180A, VGS =10V. Part not recommended for use
above this value .
RJC value shown is at time zero.
ISD 180A, di/dt 1070A/μs, VDD V(BR)DSS, TJ 175°C.
2
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AUIRLS3036-7P
Qualification Information†
Automotive
††
(per AEC-Q101)
Qualification Level
Comments: This part number(s) passed Automotive
qualification. IR’s Industrial and Consumer qualification level
is granted by extension of the higher Automotive level.
D2Pak 7 Pin
MSL1
Moisture Sensitivity Level
Class M4 (+/- 800V)†††
Machine Model
AEC-Q101-002
Class H3A (+/- 6000V)†††
AEC-Q101-001
Human Body Model
ESD
Class C5 (+/- 2000V)†††
AEC-Q101-005
Charged Device Model
Yes
RoHS Compliant
Qualification standards can be found at International Rectifiers web site: http//www.irf.com/
Exceptions (if any) to AEC-Q101 requirements are noted in the qualification report.
Highest passing voltage.
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3
AUIRLS3036-7P
1000
1000
100
10
VGS
15V
VGS
15V
10V
TOP
TOP
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
100
10
1
BOTTOM
BOTTOM
2.7V
2.7V
60μs PULSE WIDTH
60μs PULSE WIDTH
Tj = 175°C
Tj = 25°C
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 180A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
J
V
= 25V
DS
60μs PULSE WIDTH
1
2.0
3.0
4.0
5.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
5
20000
15000
10000
5000
0
V
C
= 0V,
f = 100 kHz
GS
V
V
= 48V
= 30V
I = 180A
D
DS
DS
= C + C , C SHORTED
iss
gs
gd ds
C
C
= C
rss
oss
gd
4
3
2
1
0
= C + C
ds
gd
Ciss
Coss
Crss
0
20
Q
40
60
80
100 120 140
1
10
100
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
4
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AUIRLS3036-7P
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100μsec
T
= 25°C
J
1msec
LIMITED BY PACKAGE
10msec
DC
1
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
1.4
GS
0.1
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.6
0.1
1
10
100
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
300
250
200
150
100
50
80
70
60
50
LIMITED BY PACKAGE
I
= 5mA
D
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T
, Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
1200
4.0
3.0
2.0
1.0
0.0
I
D
TOP
22A
1000
800
600
400
200
0
37A
180A
BOTTOM
0
10
20
30
40
50
60
70
25
50
75
100
125
150
175
V
Drain-to-Source Voltage (V)
Starting T , Junction Temperature (°C)
J
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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5
AUIRLS3036-7P
1
D = 0.50
0.1
0.01
0.20
0.10
R1
R1
R2
R2
R3
R3
(sec)
0.05
0.02
0.01
Ri (°C/W)
J J
C
0.103731 0.000184
0.196542 0.001587
0.098271 0.006721
1 1
2 2
3 3
Ci= iRi
Ci= iRi
SINGLE PULSE
0.001
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
300
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 1% Duty Cycle
= 180A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
6
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AUIRLS3036-7P
3.0
2.5
2.0
1.5
1.0
24
18
12
6
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250μA
I
= 120A
F
V
= 51V
R
T
= 125°C
= 25°C
J
J
T
0
-75 -50 -25
0
J
25 50 75 100 125 150 175
, Temperature ( °C )
100 200 300 400 500 600 700 800 900
T
di / dt - (A / μs)
f
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
1000
24
800
600
400
200
0
18
12
I
= 120A
= 51V
I
= 180A
= 51V
F
F
6
0
V
T
V
R
R
= 125°C
= 25°C
T
= 125°C
= 25°C
J
J
T
T
J
J
100 200 300 400 500 600 700 800 900
100 200 300 400 500 600 700 800 900
di / dt - (A / μs)
di / dt - (A / μs)
f
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
1000
I
= 180A
F
V
= 51V
R
T
= 125°C
= 25°C
800
600
400
200
0
J
T
J
100 200 300 400 500 600 700 800 900
di / dt - (A / μs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
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7
AUIRLS3036-7P
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width µs
Duty Factor
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50K
.2F
12V
.3F
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
8
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AUIRLS3036-7P
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
AUIRLS3036-7P
D2Pak - 7 Pin Part Marking Information
Part Number
AULS3036-7P
Date Code
Y= Year
WW= Work Week
A= Automotive, Lead Free
IR Logo
YWWA
XX or XX
Lot Code
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
10
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AUIRLS3036-7P
Ordering Information
Base part number
Package Type
Standard Pack
Form
Complete Part Number
Quantity
AUIRLS3036-7P
D2Pak 7 Pin
Tube
50
800
800
AUIRLS3036-7P
AUIRLS3036-7TRL
AUIRLS3036-7TRR
Tape and Reel Left
Tape and Reel Right
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11
AUIRLS3036-7P
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corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or
services without notice. Part numbers designated with the “AU” prefix follow automotive industry and / or customer specific requirements with regards
to product discontinuance and process change notification. All products are sold subject to IR’s terms and conditions of sale supplied at the time of order
acknowledgment.
IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with IR’s standard warranty. Testing
and other quality control techniques are used to the extent IR deems necessary to support this warranty. Except where mandated by government
requirements, testing of all parameters of each product is not necessarily performed.
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