AUIRLS3034-7P [INFINEON]

Power Field-Effect Transistor, 240A I(D), 40V, 0.0014ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263CB, ROHS COMPLIANT, PLASTIC, D2PAK-7;
AUIRLS3034-7P
型号: AUIRLS3034-7P
厂家: Infineon    Infineon
描述:

Power Field-Effect Transistor, 240A I(D), 40V, 0.0014ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263CB, ROHS COMPLIANT, PLASTIC, D2PAK-7

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AUTOMOTIVE GRADE  
AUIRLS3034-7P  
HEXFET® Power MOSFET  
Features  
Advanced Process Technology  
Ultra Low On-Resistance  
Logic Level Gate Drive  
Dynamic dv/dt Rating  
175°C Operating Temperature  
Fast Switching  
Repetitive Avalanche Allowed up to Tjmax  
Lead-Free, RoHS Compliant  
Automotive Qualified *  
VDSS  
40V  
RDS(on) typ.  
1.0m  
max.  
ID (Silicon Limited)  
ID (Package Limited)  
1.4m  
380A  
240A  
Description  
Specifically designed for Automotive applications, this HEXFET®  
Power MOSFET utilizes the latest processing techniques to achieve  
extremely low on-resistance per silicon area. Additional features of  
this design are a 175°C junction operating temperature, fast  
switching speed and improved repetitive avalanche rating . These  
features combine to make this design an extremely efficient and  
reliable device for use in Automotive applications and a wide variety  
of other applications.  
D2Pak 7 Pin  
AUIRLS3034-7P  
G
D
S
Gate  
Drain  
Source  
Standard Pack  
Base Part Number  
Package Type  
Orderable Part Number  
Form  
Tube  
Quantity  
50  
AUIRLS3034-7P  
AUIRLS3034-7P  
D2Pak 7 Pin  
AUIRLS3034-7TRL  
Tape and Reel Left  
800  
Absolute Maximum Ratings  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress  
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance  
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless  
otherwise specified.  
Symbol  
ID @ TC = 25°C  
Parameter  
Max.  
380  
Units  
A
Continuous Drain Current, VGS @ 10V (Silicon Limited)  
ID @ TC = 100°C  
ID @ TC = 25°C  
Continuous Drain Current, VGS @ 10V (Silicon Limited)  
Continuous Drain Current, VGS @ 10V (Package Limited)  
270  
240  
IDM  
Pulsed Drain Current   
Maximum Power Dissipation  
Linear Derating Factor  
1540  
380  
2.5  
PD @TC = 25°C  
W
W/°C  
V
mJ  
A
VGS  
EAS  
Gate-to-Source Voltage  
Single Pulse Avalanche Energy (Thermally Limited)   
± 20  
250  
IAR  
Avalanche Current   
See Fig.14,15, 22a, 22b  
EAR  
dv/dt  
TJ  
Repetitive Avalanche Energy   
Peak Diode Recovery   
mJ  
V/ns  
1.3  
Operating Junction and  
-55 to + 175  
TSTG  
Storage Temperature Range  
Soldering Temperature, for 10 seconds (1.6mm from case)  
°C  
300  
Thermal Resistance  
Symbol  
Parameter  
Typ.  
Max.  
Units  
Junction-to-Case   
–––  
0.40  
RJC  
RJA  
°C/W  
Junction-to-Ambient   
–––  
40  
HEXFET® is a registered trademark of Infineon.  
*Qualification standards can be found at www.infineon.com  
1
2015-11-4  
AUIRLS3034-7P  
Static @ TJ = 25°C (unless otherwise specified)  
Parameter  
Min. Typ. Max. Units  
40 ––– –––  
––– 0.035 ––– V/°C Reference to 25°C, ID = 5mA  
Conditions  
V(BR)DSS  
Drain-to-Source Breakdown Voltage  
Breakdown Voltage Temp. Coefficient  
V
VGS = 0V, ID = 250µA  
V(BR)DSS/TJ  
–––  
–––  
1.0  
1.0  
1.2  
–––  
1.4  
1.7  
2.5  
V
GS = 10V, ID = 200A   
GS = 4.5V, ID = 180A   
RDS(on)  
Static Drain-to-Source On-Resistance  
m  
V
VGS(th)  
gfs  
Gate Threshold Voltage  
Forward Trans conductance  
Gate Resistance  
V
VDS = VGS, ID = 250µA  
VDS = 10V, ID = 220A  
370 ––– –––  
S
RG  
–––  
––– –––  
––– ––– 250  
––– ––– 100  
––– ––– -100  
1.9  
–––  
20  
  
VDS = 40V, VGS = 0V  
IDSS  
IGSS  
Drain-to-Source Leakage Current  
µA  
VDS = 40V,VGS = 0V,TJ =125°C  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
V
GS = 20V  
GS = -20V  
nA  
V
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)  
Qg  
Total Gate Charge  
Gate-to-Source Charge  
Gate-to-Drain Charge  
Total Gate Charge Sync. (Qg - Qgd)  
Turn-On Delay Time  
Rise Time  
Turn-Off Delay Time  
Fall Time  
Input Capacitance  
Output Capacitance  
––– 120 180  
ID = 170A  
VDS = 20V  
VGS = 4.5V  
Qgs  
Qgd  
Qsync  
td(on)  
tr  
td(off)  
tf  
Ciss  
Coss  
–––  
–––  
–––  
–––  
32  
71  
49  
71  
–––  
–––  
–––  
–––  
nC  
ns  
VDD = 26V  
ID = 220A  
RG= 2.7  
VGS = 4.5V  
VGS = 0V  
––– 590 –––  
––– 94 –––  
––– 200 –––  
––– 10990 –––  
––– 2030 –––  
VDS = 40V  
Crss  
Reverse Transfer Capacitance  
––– 1100 –––  
ƒ = 1.0MHz  
pF  
Coss eff.(ER)  
Coss eff.(TR)  
Diode Characteristics  
Parameter  
Effective Output Capacitance (Energy Related) ––– 2520 –––  
VGS = 0V, VDS = 0V to 32V  
VGS = 0V, VDS = 0V to 32V  
Effective Output Capacitance (Time Related) ––– 3060 –––  
Min. Typ. Max. Units  
Conditions  
MOSFET symbol  
showing the  
integral reverse  
p-n junction diode.  
TJ = 25°C,IS = 200A,VGS = 0V   
Continuous Source Current  
(Body Diode)  
IS  
––– ––– 380  
A
––– ––– 1540  
Pulsed Source Current  
(Body Diode)  
Diode Forward Voltage  
ISM  
VSD  
trr  
––– –––  
1.3  
–––  
–––  
V
–––  
–––  
46  
49  
TJ = 25°C  
TJ = 125°C  
VDD = 34V  
IF = 220A,  
Reverse Recovery Time  
Reverse Recovery Charge  
ns  
––– 100 –––  
––– 110 –––  
TJ = 25°C di/dt = 100A/µs   
TJ = 125°C  
Qrr  
nC  
A
IRRM  
ton  
Reverse Recovery Current  
Forward Turn-On Time  
–––  
3.7  
–––  
TJ = 25°C  
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)  
Notes:  
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A. Note that  
current limitations arising from heating of the device leads may occur with some lead mounting arrangements.  
Repetitive rating; pulse width limited by max. junction temperature.  
Limited by TJmax, starting TJ = 25°C, L = 0.010mH, RG = 25, IAS = 220A, VGS =10V. Part not recommended for use above this value.  
ISD 220A, di/dt 1240A/µs, VDD V(BR)DSS, TJ 175°C.  
Pulse width 400µs; duty cycle 2%.  
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS  
.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS  
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to  
application note #AN-994  
Ris measured at TJ approximately 90°C.  
RJC value shown is at time zero  
2
2015-11-4  
AUIRLS3034-7P  
10000  
1000  
100  
100000  
10000  
1000  
100  
VGS  
10V  
60µs PULSE WIDTH  
Tj = 175°C  
VGS  
10V  
TOP  
60µs PULSE WIDTH  
Tj = 25°C  
TOP  
5.0V  
4.5V  
4.0V  
3.5V  
3.0V  
2.8V  
2.5V  
5.0V  
4.5V  
4.0V  
3.5V  
3.0V  
2.8V  
2.5V  
BOTTOM  
BOTTOM  
2.5V  
10  
2.5V  
10  
1
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
DS  
V
, Drain-to-Source Voltage (V)  
DS  
Fig. 1 Typical Output Characteristics  
Fig. 2 Typical Output Characteristics  
1000  
2.0  
1.5  
1.0  
0.5  
I
= 200A  
= 10V  
D
V
GS  
100  
10  
1
T
= 175°C  
J
T
= 25°C  
J
V
= 25V  
DS  
60µs PULSE WIDTH  
0.1  
1
2
3
4
5
-60 -40 -20 0 20 40 60 80 100120140160180  
, Junction Temperature (°C)  
T
V
, Gate-to-Source Voltage (V)  
J
GS  
Fig. 4 Normalized On-Resistance vs. Temperature  
Fig. 3 Typical Transfer Characteristics  
100000  
10000  
1000  
V
= 0V,  
= C  
f = 1 MHZ  
5.0  
GS  
C
C
C
+ C , C  
SHORTED  
I = 170A  
D
iss  
gs  
gd  
ds  
V
V
= 32V  
= 20V  
DS  
DS  
= C  
rss  
oss  
gd  
= C + C  
4.0  
3.0  
2.0  
1.0  
0.0  
ds  
gd  
C
iss  
C
oss  
C
rss  
0.1  
1
10  
100  
0
25  
50  
75  
100  
125  
150  
V
, Drain-to-Source Voltage (V)  
DS  
Q , Total Gate Charge (nC)  
G
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage  
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage  
3
2015-11-4  
AUIRLS3034-7P  
10000  
1000  
100  
10  
1000  
100  
10  
OPERATION IN THIS AREA  
LIMITED BY R  
(on)  
DS  
T
= 175°C  
J
100µsec  
1msec  
Limited by package  
T
= 25°C  
J
10msec  
DC  
Tc = 25°C  
Tj = 175°C  
Single Pulse  
V
= 0V  
3.0  
GS  
1
1.0  
0
1
10  
100  
0.0  
0.5  
V
1.0  
1.5  
2.0  
2.5  
3.5  
V
, Drain-to-Source Voltage (V)  
, Source-to-Drain Voltage (V)  
DS  
SD  
Fig 8. Maximum Safe Operating Area  
Fig. 7 Typical Source-to-Drain Diode  
50  
48  
46  
44  
42  
40  
400  
300  
200  
100  
0
Id = 5mA  
Limited By Package  
-60 -40 -20  
0
20 40 60 80 100120140160180  
, Temperature ( °C )  
25  
50  
75  
100  
125  
150  
175  
T
J
T
, Case Temperature (°C)  
C
Fig 9. Maximum Drain Current vs. Case Temperature  
Fig 10. Drain-to-Source Breakdown Voltage  
2.5  
1200  
I
D
TOP  
47A  
94A  
1000  
800  
600  
400  
200  
0
2.0  
1.5  
1.0  
0.5  
0.0  
BOTTOM 220A  
-5  
0
5
10 15 20 25 30 35 40 45  
25  
50  
75  
100  
125  
150  
175  
Starting T , Junction Temperature (°C)  
V
Drain-to-Source Voltage (V)  
J
DS,  
Fig 12. Maximum Avalanche Energy vs. Drain Current  
Fig 11. Typical COSS Stored Energy  
4
2015-11-4  
AUIRLS3034-7P  
1
D = 0.50  
0.1  
0.20  
0.10  
0.05  
Ri (°C/W)  
I (sec)  
0.00741  
0.05041  
0.18384  
0.15864  
0.000005  
0.000038  
0.001161  
0.008809  
0.02  
0.01  
0.01  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
SINGLE PULSE  
( THERMAL RESPONSE )  
0.001  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
t
, Rectangular Pulse Duration (sec)  
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case  
1000  
100  
10  
Duty Cycle = Single Pulse  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming Tj = 150°C and  
Tstart =25°C (Single Pulse)  
0.01  
0.05  
0.10  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming  j = 25°C and  
Tstart = 150°C.  
1
1.0E-06  
1.0E-05  
1.0E-04  
1.0E-03  
1.0E-02  
1.0E-01  
tav (sec)  
Fig 14. Avalanche Current vs. Pulse width  
300  
250  
200  
150  
100  
50  
Notes on Repetitive Avalanche Curves , Figures 14, 15:  
(For further info, see AN-1005 at www.infineon.com)  
1. Avalanche failures assumption:  
TOP  
BOTTOM 1.0% Duty Cycle  
= 220A  
Single Pulse  
I
D
Purely a thermal phenomenon and failure occurs at a temperature far in  
excess of Tjmax. This is validated for every part type.  
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.  
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.  
4. PD (ave) = Average power dissipation per single avalanche pulse.  
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase  
during avalanche).  
6. Iav = Allowable avalanche current.  
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as  
25°C in Figure 13, 14).  
tav = Average time in avalanche.  
D = Duty cycle in avalanche = tav ·f  
0
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)  
25  
50  
75  
100  
125  
150  
175  
Starting T , Junction Temperature (°C)  
P
D (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC  
Iav = 2T/ [1.3·BV·Zth]  
J
E
AS (AR) = PD (ave)·tav  
Fig 15. Maximum Avalanche Energy vs. Temperature  
5
2015-11-4  
AUIRLS3034-7P  
16  
14  
12  
10  
8
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
I
= 89A  
= 34V  
F
V
R
T = 25°C  
J
T = 125°C  
J
I
I
I
= 250µA  
= 1.0mA  
= 1.0A  
D
D
D
6
4
2
0
100 200 300 400 500 600 700  
-75 -50 -25  
0
25 50 75 100 125 150 175  
di /dt (A/µs)  
F
T
, Temperature ( °C )  
J
Fig 16. Threshold Voltage vs. Temperature  
Fig. 17 - Typical Recovery Current vs. dif/dt  
900  
16  
I = 134A  
F
I
= 89A  
= 34V  
F
800  
700  
600  
500  
400  
300  
200  
100  
0
V
14  
12  
10  
8
V
= 34V  
R
R
T = 25°C  
T = 25°C  
J
T = 125°C  
J
J
T = 125°C  
J
6
4
2
0
100 200 300 400 500 600 700 800  
0
100 200 300 400 500 600 700  
di /dt (A/µs)  
di /dt (A/µs)  
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt  
Fig. 19 - Typical Stored Charge vs. dif/dt  
800  
700  
600  
500  
400  
300  
200  
100  
0
I
= 134A  
= 34V  
F
V
R
T = 25°C  
J
T = 125°C  
J
0
100 200 300 400 500 600 700 800  
di /dt (A/µs)  
F
Fig. 20 - Typical Stored Charge vs. dif/dt  
6
2015-11-4  
AUIRLS3034-7P  
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs  
15V  
V
(BR)DSS  
t
p
DRIVER  
+
L
V
DS  
D.U.T  
AS  
R
G
V
DD  
-
I
A
20V  
0.01  
t
p
I
AS  
Fig 22b. Unclamped Inductive Waveforms  
Fig 22a. Unclamped Inductive Test Circuit  
Fig 23b. Switching Time Waveforms  
Fig 23a. Switching Time Test Circuit  
Id  
Vds  
Vgs  
Vgs(th)  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Fig 24a. Gate Charge Test Circuit  
Fig 24b. Gate Charge Waveform  
7
2015-11-4  
AUIRLS3034-7P  
D2Pak - 7 Pin Package Outline (Dimensions are shown in millimeters (inches))  
D2Pak - 7 Pin Part Marking Information  
Part Number  
AULS3034-7P  
Date Code  
IR Logo  
Y= Year  
WW= Work Week  
Lot Code  
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/  
8
2015-11-4  
AUIRLS3034-7P  
D2Pak - 7 Pin Tape and Reel  
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/  
9
2015-11-4  
AUIRLS3034-7P  
Qualification Information  
Qualification Level  
Automotive  
(per AEC-Q101)  
Comments: This part number(s) passed Automotive qualification. Infineon’s  
Industrial and Consumer qualification level is granted by extension of the higher  
Automotive level.  
Moisture Sensitivity Level  
D2-Pak 7 Pin  
MSL1  
Class M4 (+/- 800V)†  
AEC-Q101-002  
Class H3A (+/- 6000V)†  
AEC-Q101-001  
Class C5 (+/- 2000V)†  
AEC-Q101-005  
Yes  
Machine Model  
Human Body Model  
ESD  
Charged Device Model  
RoHS Compliant  
† Highest passing voltage.  
Revision History  
Date  
Comments  
 Added "Logic Level Gate Drive" bullet in the features section on page 1  
 Updated part marking on page 8  
 Updated typo on the fig.19 and fig.20, unit of y-axis from "A" to "nC" on page 6.  
 Updated data sheet with new IR corporate template  
 Updated datasheet with corporate template  
4/2/2014  
11/4/2015  
 Corrected ordering table on page 1.  
Published by  
Infineon Technologies AG  
81726 München, Germany  
© Infineon Technologies AG 2015  
All Rights Reserved.  
IMPORTANT NOTICE  
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics  
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any  
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and  
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third  
party.  
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this  
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of  
the product of Infineon Technologies in customer’s applications.  
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of  
customer’s technical departments to evaluate the suitability of the product for the intended application and the  
completeness of the product information given in this document with respect to such application.  
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest  
Infineon Technologies office (www.infineon.com).  
WARNINGS  
Due to technical requirements products may contain dangerous substances. For information on the types in question  
please contact your nearest Infineon Technologies office.  
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized  
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a  
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.  
10  
2015-11-4  

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