IDT72T51543L7-5BB [IDT]

FIFO, 64KX18, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256;


型号：	IDT72T51543L7-5BB
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FIFO, 64KX18, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 先进先出芯片
文件：	总12页 (文件大小：205K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

2.5V MULTI-QUEUE FIFO (32 QUEUES)

18 BIT WIDE CONFIGURATION

1,179,648 bits

ADVANCE INFORMATION

IDT72T51543

IDT72T51553

2,359,296 bits

•

Shows PAE and PAF status of 8 Queues

Direct or polled operation of flag status bus

Global Bus Matching - (All Queues have same Input Bus Width

and Output Bus Width)

User Selectable Bus Matching Options:

- x18in to x18out

- x9in to x18out

FEATURES:

•

Choose from among the following memory density options:

IDT72T51543

IDT72T51553

Total Available Memory = 1,179,648 bits

Total Available Memory = 2,359,296 bits

•

Configurable from 1 to 32 Queues

Queues may be configured at master reset from the pool of

Total Available Memory in blocks of 512 x 18 or 1,024 x 9

Independent Read and Write access per queue

User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL

User programmable via serial port

- x18in to x9out

- x9in to x9out

•

FWFT mode of operation on read port

Partial Reset, clears data in single Queue

Expansion of up to 8 Multi-Queue devices in parallel is available

Power Down Input provides additional power savings in HSTL

and eHSTL modes.

JTAG Functionality (Boundary Scan)

Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm

HIGH Performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

Default Multi-Queueueue device configurations

-IDT72T51543: 2,048 x 18 x 32Q

-IDT72T51553: 4,096 x 18 x 32Q

•

100% Bus Utilization, Read and Write on every clock cycle

200 MHz High speed operation (5ns cycle time)

3.6ns access time

Echo Read Enable & Echo Read Clock Outputs

Individual, Active queue flags (OV, FF, PAE, PAF, PR)

8 bit parallel flag status on both read and write ports

•

DATA PATH FLOW DIAGRAM

MULTI-QUEUE FIFO

RADEN

ESTR

WADEN

FSTR

RDADD

WRADD

REN

RCLK

EREN

WEN

WCLK

ERCLK

out

x9, x18

DATA IN

DATA OUT

PAF

PAE

Qmax

PAFn

PAEn

5999 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc

OCTOBER 2, 2001

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-5999/-

IDT72T51543/72T515532.5V,MULTI-QUEUEFIFO(32QUEUES)

18BITWIDECONFIGURATION1,179,648and2,359,296bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IftheuserdoesnotwishtoprogramtheMulti-Queuedevice,adefaultoptionis

availablethatconfiguresthedeviceinapredeterminedmanner.

BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster

Reset latches in all configuration setup pins and must be performed before

programmingofthedevicecantakeplace.APartialResetwillresetthereadand

writepointersofanindividualFIFOqueue,providedthatthequeueisselected

onboththe write portandreadportatthe time ofpartialreset.

Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are

provided.TheseareoutputsfromthereadportoftheFIFOthatarerequiredfor

highspeeddatacommunication,toprovidetightersynchronizationbetweenthe

databeingtransmittedfromtheQnoutputsandthedatabeingreceivedbythe

input device. Data read from the read port is available on the output bus with

respecttoERENandERCLK,thisisveryusefulwhendataisbeingreadathigh

speed.

The Multi-Queue FIFO has the capability of operating its IO in either 2.5V

LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected via the

IOSELinput.Thecoresupplyvoltage(VCC)totheMulti-Queueisalways2.5V,

howevertheoutputlevelscanbesetindependentlyviaaseparatesupply,VDDQ.

ThedevicesalsoprovideadditionalpowersavingsviaaPowerDownInput.

This input disables the write port data inputs when no write operations are

required.

DESCRIPTION:

The IDT72T51543/72T51553 Multi-Queue FIFO device is a single chip

withinwhichanywherebetween1and32discreteFIFOqueuescanbesetup.

Allqueueswithinthedevicehaveacommondatainputbus,(writeport)and

acommondataoutputbus,(readport).Datawrittenintothewriteportisdirected

toa respective queue via aninternalde-multiplexoperation, addressedby

theuser.Datareadfromthereadportisaccessedfromarespectivequeue

via aninternalmultiplexoperation, addressedbythe user. Data writes and

readscanbeperformedathighspeedsupto200MHz,withaccesstimesof

3.6ns.Datawriteandreadoperationsaretotallyindependentofeachother,

aqueuemaybeselectedonthewriteportandadifferentqueueontheread

portorbothportsmayselectthesamequeuesimultaneously.

The device provides Full flag and Output Valid flag status for the queue

selected for write and read operations respectively. Also a Programmable

AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.

Two8bitprogrammableflagbussesareavailable,providingstatusofqueues

notselectedforwriteorreadoperations.When8orlessqueuesareconfigured

in the device these flag busses provide an individual flag per queue, when

morethan8queuesareused,eitheraPolledorDirectmodeofbusoperation

providestheflagbusseswithallqueuesstatus.

BusMatchingisavailableonthisdevice,eitherportcanbe9bitsor18bits

wide.WhenBusMatchingisusedthedeviceensuresthelogicaltransferof

datathroughputinaLittleEndianmanner.

Theuserhasfullflexibilityconfiguringqueueswithinthedevice,beingable

toprogramthetotalnumberofqueuesbetween1and32,theindividualqueue

depthsbeingindependentofeachother.Theprogrammableflagpositionsare

alsouserprogrammable.Allprogrammingisdoneviaadedicatedserialport.

AJTAGtestportisprovided,heretheMulti-QueueFIFOhasafullyfunctional

BoundaryScanfeature,compliantwithIEEE1449.1StandardTestAccessPort

andBoundaryScanArchitecture.

SeeFigure1,Multi-QueueFIFOBlockDiagramforanoutlineofthefunctional

blockswithinthedevice.

IDT72T51543/72T515532.5V,MULTI-QUEUEFIFO(32QUEUES)

18BITWIDECONFIGURATION1,179,648and2,359,296bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

x9, x18

- D

WCLK

WEN

INPUT

DEMUX

TMS

TDI

WRADD

WADEN

Write Control

Logic

JTAG

Logic

TDO

TCK

TRST

Write Pointers

PAF

General Flag

Monitor

FSTR

PAFn

FSYNC

Upto 32

FIFO

Queues

FXO

FXI

Active Q

Flags

PAE

2.3 Mbit

Dual Port

Memory

Active Q

Flags

PAF

PAE

SCLK

General Flag

Monitor

PAEn

ESTR

ESYNC

EXI

Serial

Multi-Queue

Programming

SENI

SENO

EXO

Read Pointers

Reset

Logic

RDADD

Read Control

Logic

RADEN

NULL-Q

MAST

REN

RCLK

ID0

ID1

ID2

Device ID

3 Bit

OUTPUT

MUX

PAE/ PAF

Offset

DFM

OUTPUT

EREN

PRS

MRS

ERCLK

5999 drw02

IOSEL

Vref

IO Level Control

Power Down

- Q

x9, x18

out

Figure 1. Multi-Queue Block Diagram

IDT72T51543/72T515532.5V,MULTI-QUEUEFIFO(32QUEUES)

18BITWIDECONFIGURATION1,179,648and2,359,296bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINCONFIGURATION

A1 BALL PAD CORNER

D14

D15

D17

D13

D16

GND

D12

D11

GND

D10

TCK

TMS

TDO

TDI

ID1

ID0

Q12

Q11

Q14

Q13

Q15

DNC

TRST

IOSEL

VDD

ID2

Q10

Q16

DNC

Q17

DNC

VDDQ

VDD

VDDQ

GND

VDDQ VDDQ

VDD

GND

VDD

VDDQ

VDD

GND

VDDQ

VDD

VDDQ

VDD

GND

VDDQ

VDD

GND

VDD

DNC

GND

DNC

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

Null Q

GND

VDD

VREF

GND MASTER

GND

DFM

VDD

SENO

SENI

VDDQ

RDADD0 RDADD1

PRELIMINARY

WRADD1 WRADD0

SCLK

VDDQ

VDDQ VDDQ

VDD

PAF7

PAF4

WCLK

VDD

VDDQ

PAE7

EREN

REN

VDDQ

PAE6

PAE5

PAE4

VDDQ RDADD2 RDADD3 RDADD4

WRADD4 WRADD3 WRADD2 WADEN

RDADD5 RDADD6 RDADD7

PAE

PAF3

PAF2

PAF1

PAF6

PAF5

WEN

PAE3

WRADD6 WRADD5 FSYNC

FSTR

PAF0

ESTR

EXO

ESYNC

EXI

PAF

ERCLK

PAE2

PAE1

RADEN

WRADD7

FXI

FXO

RCLK

PAE0

PRS

MRS

5999 drw03

PBGA (BB256-1, order code: BB)

TOP VIEW

NOTE:

1. DNC - Do Not Connect.

IDT72T51543/72T515532.5V,MULTI-QUEUEFIFO(32QUEUES)

18BITWIDECONFIGURATION1,179,648and2,359,296bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice

providesauserprogrammablealmostfullflagforall32FIFOqueuesandwhen

arespectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus

for that queue. Conversely, the read port has an output valid flag, providing

statusofthedatabeingreadfromthequeueselectedonthereadport.Aswell

astheoutputvalidflagthedeviceprovidesadedicatedalmostemptyflag.This

almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.

Thedeviceprovides auserprogrammablealmostemptyflagforall32FIFO

queuesandwhenarespectivequeueisselectedonthereadport,thealmost

emptyflagprovidesstatusforthatqueue.

DETAILEDDESCRIPTION

MULTI-QUEUE STRUCTURE

TheIDTMulti-QueueFIFOhasasingledatainputportandsingledataoutput

portwithupto32FIFOqueuesinparallelbufferingbetweenthetwoports.The

user can setup between 1 and 32 FIFO Queues within the device. These

queuescanbeconfiguredtoutilizethetotalavailablememory,providingtheuser

with full flexibility and ability to configure the queues to be various depths,

independentofoneanother.

MEMORYORGANIZATION/ALLOCATION

PROGRAMMABLE FLAG BUSSES

Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing

512x18or1,024x9bits.Whentheuserisconfiguringthenumberofqueues

andindividualqueue sizes the usermustallocate the memorytorespective

queues,inunitsofblocks,thatis,asinglequeuecanbemadeupfrom0tom

blocks,wheremisthetotalnumberofblocksavailablewithinadevice.Alsothe

total size ofanygiven queue mustbe inincrements of512x18or 1,024x 9.

Forthe IDT72T51543andIDT72T51553the TotalAvailable Memoryis 128

and256blocks respectively(a blockbeing512x18or1,024x9). Ifanyport

is configured for x18 bus width, a block size is 512 x 18. If both the write and

readports are configuredforx9bus width, a blocksize is 1,024x9. Queues

canbebuiltfromtheseblockstomakeanysizequeuedesiredandanynumber

ofqueuesdesired.

Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput

valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost

fullflagstatusbusisprovided,thisbusis8bitswide.Also,analmostemptyflag

statusbusisprovided,againthisbusis8bitswide.Thepurposeoftheseflag

bussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels

within FIFO queues that may not be selected on the write or read port. As

mentioned,thedeviceprovidesalmostfullandalmostemptyregisters(program-

mable by the user) for each of the 32 FIFO queues in the device.

IntheIDT72T51543/72T51553Multi-QueueFIFOdevicetheuserhasthe

optionofutilizinganywhere between1and32FIFOqueues, therefore the 8

bitflagstatusbussesaremultiplexedbetweenthe32queues,aflagbuscanonly

provide status for 8 of the 32 queues at any moment, this is referred to as a

“Quadrant”,suchthatwhenthebusisprovidingstatusofqueues1through8,

thisisquadrant1,whenitisqueues9through16,thisisquadrant2andsoon

uptoquadrant4.Iflessthan32queuesaresetupinthedevice,therearestill

4quadrants,suchthatin“Polled”modeofoperationtheflagbuswillstillcycle

through4quadrants.Ifforexampleonly22 queuesaresetup,quadrants1and

2 will reflect status of queues 1 through 8 and 9 through 16 respectively.

Quadrant3willreflectthestatusofqueues17through22ontheleastsignificant

6bits,themostsignificant2bitsoftheflagbusaredon’tcareandthe4thquadrant

outputswillbedon’tcarealso.

BUS WIDTHS

TheinputportiscommontoallFIFOqueueswithinthedevice,asistheoutput

port.ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinput

portandoutputportcanbe eitherx9orx18bits wide, the readandwrite port

widthsbeingsetindependentlyofoneanother.Becausetheportsarecommon

toallqueuesthewidthofthequeuesisnotindividuallyset,sothattheinputwidth

of all queues are equal and the output width of all queues are equal.

WRITING TO & READING FROM THE MULTI-QUEUE

The flag busses are available in two user selectable modes of operation,

“Polled”or“Direct”.Whenoperatinginpolledmodeaflagbusprovidesstatus

ofeachquadrantsequentially,thatis,oneachrisingedgeofaclocktheflagbus

isupdatedtoshowthestatusofeachquadrantinorder.Therisingedgeofthe

writeclockwillupdatethealmostfullbusandarisingedgeonthereadclockwill

updatethealmostemptybus.Themodeofoperationisalwaysthesameforboth

thealmostfullandalmostemptyflagbusses.Whenoperatingindirectmode,the

quadrantontheflagbusisselectedbytheuser.Sotheusercanactuallyaddress

thequadranttobeplacedontheflagstatusbusses,theseflagbussesoperate

independentlyofoneanother.Addressingofthealmostfullflagbusisdonevia

thewriteportandaddressingofthealmostemptyflagbusisdoneviathereadport.

Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete

FIFOqueueviathewritequeueselectaddressinputs.Conversely,databeing

readfromthedevicereadportisreadfromaqueueselectedviathereadqueue

selectaddressinputs.Datacanbesimultaneouslywrittenintoandreadfromthe

sameFIFOqueueordifferentFIFOqueues.Onceaqueueisselectedfordata

writes or reads, the writing and reading operation is performed in the same

manner as a conventional IDT synchronous FIFO’s, utilizing clocks and

enables,thereisasingleclockandenableperport.Whenaspecificqueueis

addressedonthewriteport,dataplacedonthedatainputsiswrittentothatqueue

sequentiallybasedontherisingedgeofawriteclockprovidedsetupandhold

timesaremet.Conversely,dataisreadontotheoutputportafteranaccesstime

from a rising edge on a read clock.

EXPANSION

Theoperationofthewriteportiscomparabletothefunctionofaconventional

FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon

thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput

provides status of the selected queue. The operation of the read port is

comparabletothefunctionofaconventionalFIFOoperatinginFWFTmode.

WhenaFIFOqueueisselectedontheoutputport,thenextwordinthatqueue

willautomaticallyfallthroughtotheoutputregister.Allsubsequentwordsfrom

thatqueuerequireanenabledreadcycle.Datacannotbereadfromaselected

queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating

whendata readoutis valid. Ifthe userswitches toa queue thatis empty, the

lastwordfromtheprevious queuewillremainontheoutputregister.

Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected

queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost

ExpansionofMulti-Queuedevicesisalsopossible,upto8devicescanbe

connectedinaparallelfashionprovidingthepossibilityofbothdepthexpansion

or queue expansion. Depth Expansion means expanding the depths of

individual queues. Queue expansion means increasing the total number of

queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore

memoryblockswithinaMulti-Queuedevicecanbeallocatedtoincreasethe

depth of a queue. For example, depth expansion of 8 devices provides the

possibilityof8queuesof64Kx18deepwithintheIDT72T51543,and128kx

18deepwithintheIDT72T51553,eachqueuebeingsetupwithinasingledevice

utilizing all memory blocks available to produce a single queue. This is the

deepestFIFOqueuethatcansetupwithinadevice.

IDT72T51543/72T515532.5V,MULTI-QUEUEFIFO(32QUEUES)

18BITWIDECONFIGURATION1,179,648and2,359,296bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Forqueue expansiona maximumnumberof256(8x32)queues maybe connectingMulti-Queuedevicesinexpansionmodeallrespectiveinputpins

setup,eachqueuebeing4Kx18or8Kx9deep,iflessqueuesaresetup,then (data&control)andoutputpins(data& flags),shouldbe“connected”together

morememoryblockswillbeavailabletoincreasequeuedepthsifdesired.When betweenindividualdevices.

IDT72T51543/72T515532.5V,MULTI-QUEUEFIFO(32QUEUES)

18BITWIDECONFIGURATION1,179,648and2,359,296bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS

Symbol

Name

I/OTYPE

Description

D[17:0]

Din

DataInputBus

LVTTL

INPUT

These are the 18data inputpins. Data is writtenintothe device via these inputpins onthe risingedge

ofWCLKprovidedthatWENisLOW.Duetobusmatchingnotallinputsmaybeused,anyunusedinputs

shouldbetiedLOW.

DF⁽¹⁾

DefaultFlag

DefaultMode

RCLK Echo

REN Echo

LVTTL

INPUT

IftheuserrequiresdefaultprogrammingoftheMulti-Queuedevice,thispinmustbesetupbeforeMaster

Resetandmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines

the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.

(1)

DFM

LVTTL

INPUT

TheMulti-Queuedevicerequiresprogrammingaftermasterreset.Theusercandothisseriallyviathe

serialport,ortheusercanusethedefaultmethod.IfDFMisLOWatmasterresetthenserialmodewillbe

selected,ifHIGHthendefaultmodeisselected.

ERCLK

HSTL-LVTTL ReadClockEchooutput,thisoutputgeneratesaclockbasedonthereadclockinput,thisisusedfor

OUTPUT SourceSynchronousclockingwherethereceivingdevicesutilizestheERCLKtoclockdataoutputfrom

theFIFO.

EREN

HSTL-LVTTL ReadEnableEchooutput,canbeusedinconjunctionwiththeERCLKoutputtoloaddataoutputfromthe

OUTPUT FIFOintothe receivingdevice.

ESTR

PAEn Flag Bus

Strobe

LVTTL

INPUT

IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK

andtheRDADDbustoselectaquadrantofqueuestobeplacedontothe PAEnbusoutputs.Aquadrant

addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If

Polledoperationshasbeenselected,ESTRshouldbetiedinactive,LOW.

ESYNC

PAEnBus Sync

LVTTL

ESYNCisanoutputfromtheMulti-QueuedevicethatprovidesasynchronizingpulseforthePAEnbus

OUTPUT duringPolledoperationofthePAEnbus.DuringPolledoperationeachquadrantofqueuestatusflagsis

loadedontothe PAEnbus outputs sequentiallybasedonRCLK. The firstRCLKrisingedge loads

quadrant1ontoPAEn,thesecondRCLKrisingedgeloadsquadrant2andsoon.ThefifthRCLKrising

edge will again load quadrant 1. During the RCLK cycle that quadrant 1 of a selected device is placed

ontothePAEnbus,theESYNCoutputwillbeHIGH.Forallotherquadrantsofthatdevice,theESYNC

outputwillbeLOW.

EXI

PAEnBus

ExpansionIn

LVTTL

INPUT

The EXIinputis usedwhenMulti-Queue devices are connectedinexpansionmode andPolledPAEn

bus operationhas beenselected. EXIofdevice ‘N’connects directlytoEXOofdevice ‘N-1’. The EXI

receivesatokenfromthepreviousdeviceinachain.InsingledevicemodetheEXIinputshouldbetied

LOWifthePAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheEXIinput

shouldbeconnectedtotheEXOoutputofthesamedevice.InexpansionmodetheEXIofthefirstdevice

shouldbetiedLOW,whendirectmodeisselected.

EXO

PAEnBus

ExpansionOut

LVTTL

EXOisanoutputthatisusedwhenMulti-QueuedevicesareconnectedinexpansionmodeandPolled

OUTPUT PAEnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.This

pinpulses whendevice Nhas placedits final(4th)quadrantontothePAEnbus withrespecttoRCLK.

This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising

edgethefirstquadrantofdeviceN+1willbeloadedontothePAEnbus.Thiscontinuesthroughthechain

andEXOofthelastdeviceisthenloopedbacktoEXIofthefirstdevice.TheESYNCoutputofeachdevice

inthechainprovides synchronizationtotheuserofthis loopingevent.

Full Flag

LVTTL

This pinprovides thefullflagoutputfortheactiveFIFOqueue,thatis,thequeueselectedontheinput

OUTPUT portforwrite operations, (selectedvia WCLK, WRADDbus andWADEN). Onthe WCLKcycle aftera

queueselection,thisflagwillshowthestatusofthenewlyselectedqueue.Datacanbewrittentothisqueue

onthenextcycleprovidedFFisHIGH.ThisflaghasHigh-Impedancecapability,thisisimportantduring

expansionofdevices,whentheFFflagoutputofupto8devicesmaybeconnectedtogetheronacommon

line.ThedevicewithaqueueselectedtakescontroloftheFFbus,allotherdevicesplacetheirFFoutput

intoHigh-Impedance.Whenaqueueselectionismadeonthewriteportthisoutputwillswitchfrom

High-ImpedancecontrolonthenextWCLKcycle.ThisflagissynchronizedtoWCLK.

(1)

Flag Mode

LVTTL

INPUT

Thispinissetupbeforeamasterresetandmustnottoggleduringanydeviceoperation.Thestateofthe

FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbussesoperateineitherPolled

orDirectmode.Ifthis pinis HIGHthemodeis Polled,ifLOWthenitwillbeDirect.

FSTR

PAFn Flag Bus

Strobe

LVTTL

INPUT

IfdirectoperationofthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK

andtheWRADDbustoselectaquadrantofqueuestobeplacedontothePAFnbusoutputs.Aquadrant

IDT72T51543/72T515532.5V,MULTI-QUEUEFIFO(32QUEUES)

18BITWIDECONFIGURATION1,179,648and2,359,296bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/OTYPE

Description

FSTR

(Conitnued) Strobe

PAFn Flag Bus

LVTTL

INPUT

addressedviatheWRADDbus is selectedontherisingedgeofWCLKprovidedthatFSTRis HIGH.If

Polledoperationshasbeenselected,FSTRshouldbetiedinactive,LOW.

FSYNC

PAFn Bus Sync

LVTTL

FSYNCisanoutputfromtheMulti-QueuedevicethatprovidesasynchronizingpulseforthePAFnbus

OUTPUT duringPolledoperationofthePAFnbus.DuringPolledoperationeachquadrantofqueuestatusflags

is loadedontothePAFnbus outputs sequentiallybasedonWCLK.ThefirstWCLKrisingedgeloads

quadrant1ontoPAFn,thesecondWCLKrisingedgeloadsquadrant2andsoon.ThefifthWCLKrising

edgewillagainloadquadrant1.DuringtheWCLKcyclethatquadrant1ofaselecteddeviceis placed

ontothePAFnbus,theFSYNCoutputwillbeHIGH.Forallotherquadrantsofthatdevice,theFSYNC

outputwillbeLOW.

FXI

PAFnBus

ExpansionIn

LVTTL

INPUT

The FXIinputis usedwhenMulti-Queue devices are connectedinexpansionmode andPolled PAFn

bus operation has been selected. FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI

receivesatokenfromthepreviousdeviceinachain.InsingledevicemodetheFXIinputshouldbetied

LOWifthePAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheFXIinput

shouldbeconnectedtotheFXOoutputofthesamedevice.InexpansionmodetheFXIofthefirstdevice

shouldbetiedLOW,whendirectmodeisselected.

FXO

PAFnBus

ExpansionOut

LVTTL

FXOisanoutputthatisusedwhenMulti-QueuedevicesareconnectedinexpansionmodeandPolled

OUTPUT PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This

pinpulseswhendeviceNhasplaceditsfinal(4th)quadrantontothePAFnbuswithrespecttoWCLK.

This pulse (token)is thenpassedontothe nextdevice inthe chain‘N+1’andonthe nextWCLKrising

edgethefirstquadrantofdeviceN+1willbeloadedontothePAFnbus.Thiscontinuesthroughthechain

andFXOofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdevice

inthechainprovides synchronizationtotheuserofthis loopingevent.

(1)

ID[2:0]

Device ID Pins

LVTTL

INPUT

Forthe32QMulti-QueuedevicetheWRADDandRDADDaddressbussesare8bitswide.Whenaqueue

selectiontakesplacethe3MSB’softhis8bitaddressbusareusedtoaddressthespecificdevice(the

5LSB’s are usedtoaddress the queue withinthatdevice). Duringwrite/readoperations the 3MSB’s

oftheaddressarecomparedtothedeviceIDpins.ThefirstdeviceinachainofMulti-Queue’s(connected

in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which

is‘111’,howevertheIDdoesnothavetomatchthedeviceorder.Insingledevicemodethesepinsshould

besetupas‘000’andthe3MSB’softheWRADDandRDADDaddressbussesshouldbetiedLOW.The

ID[2:0]inputs setupa respective devices IDduring masterreset.TheseIDpinsmustnottoggleduring

any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.

IOSEL

IOSelect

LVTTL

INPUT

This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are

required then IOSEL should be tied LOW. If LVTTL I/O are required then it should be tied HIGH.

(1)

InputWidth

MasterDevice

LVTTL

INPUT

IWselectsthebuswidthforthedatainputbus.IfIWisLOWduringaMasterResetthenthebuswidth

is x18, if HIGH then it is x9.

(1)

MAST

LVTTL

INPUT

ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe

MasterdeviceoraSlave.IfthispinisHIGH,thedeviceisthemasterifitisLOWthenitisaSlave.Themaster

deviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgotoHigh-Impedance,

preventingbuscontention.IfaMulti-Queuedeviceisbeingusedinsingledevicemode,thispinmust

be setHIGH.

MRS

MasterReset

LVTTL

INPUT

AmasterresetisperformedbytakingMRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired

aftermasterreset.

NULL-Q

NullQueueSelect HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD

INPUT

address bus toaddress the Null-Q.

OutputEnable

LVTTL

INPUT

TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontroloftheMulti-Queue

dataoutputbus,Qout.Ifadevicehasbeenconfiguredasa“Master”device,theQoutdataoutputswillbe

inaLowImpedanceconditioniftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbein

HighImpedance.Ifadeviceisconfigureda“Slave”device,thentheQoutdataoutputswillalwaysbein

HighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpointOEprovidesthree-

stateofthatrespectivedevice.

OutputValidFlag

LVTTL ThisoutputflagprovidesoutputvalidstatusforthedatawordpresentontheMulti-QueueFIFOdataoutput

OUTPUT port,Qout.Thisflagistherefore,2-stagedelayedtomatchthedataoutputpathdelay.Thatis,thereis

IDT72T51543/72T515532.5V,MULTI-QUEUEFIFO(32QUEUES)

18BITWIDECONFIGURATION1,179,648and2,359,296bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/OTYPE

Description

OutputValidFlag

LVTTL a2RCLKcycledelayfromthetimeagivenqueueisselectedforreads,tothetimetheOVflagrepresents

OUTPUT thedatainthatrespectivequeue.Whenaselectedqueueonthereadportisreadtoempty,theOVflag

willgoHIGH,indicatingthatdataontheoutputbus is notvalid.The OVflagalsohas High-Impedance

capability,requiredwhenmultipledevices areusedandtheOVflags aretiedtogether.

(Continued)

(1)

OutputWidth

LVTTL OWselectsthebuswidthforthedataoutputbus.IfOWisLOWduringaMasterResetthenthebuswidth

INPUT is x18, if HIGH then it is x9.

PAE

Programmable

Almost-EmptyFlag

LVTTL ThispinprovidestheAlmost-EmptyflagstatusfortheFIFOqueuethathasbeenselectedontheoutput

OUTPUT portforreadoperations,(selectedviaRCLK,RDADDandRADEN).ThispinisLOWwhentheselected

FIFOqueuealmost-empty.This flagoutputmaybeduplicatedononeofthe PAEnbus lines.This flag

is synchronizedtoRCLK.

PAEn

Programmable

LVTTL Onthe 32Qdevice thePAEnbus is 8bits wide.Atanyonetimethis outputbus provides PAEstatus of

Almost-EmptyFlagBus OUTPUT 8queues (1quadrant),withinaselecteddevice,havingatotalof4quadrants.DuringFIFOread/write

operationstheseoutputsprovideprogrammableemptyflagstatus,ineitherdirectorpolledmode.The

modeofflagoperationisdeterminedduringmasterresetviathestateoftheFMinput.Thisflagbusiscapable

ofHigh-Impedancestate,thisisimportantduringexpansionofMulti-Queuedevices.Duringdirect

operationthePAEnbusisupdatedtoshowthePAEstatusofaquadrantofqueueswithinaselecteddevice.

SelectionismadeusingRCLK,ESTRandRDADD.DuringPolledoperationthePAEnbusisloadedwith

thePAEstatusofMulti-QueueFIFOquadrantssequentiallybasedontherisingedgeofRCLK.

PAF

Programmable

Almost-FullFlag

LVTTL ThispinprovidestheAlmost-FullflagstatusfortheFIFOqueuethathasbeenselectedontheinput

OUTPUT portforwriteoperations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselected

FIFOqueueisalmost-full.Thisflagoutputmaybeduplicatedononeofthe PAFnbuslines.Thisflagis

synchronizedtoWCLK.

PAFn

Programmable

Almost-FullFlagBus

LVTTL Onthe 32Qdevice the PAFnbus is 8bits wide. Atanyone time this outputbus provides PAF status of

OUTPUT 8queues (1quadrant),withinaselecteddevice,havingatotalof4quadrants.DuringFIFOread/write

operationstheseoutputsprovideprogrammablefullflagstatus,ineitherdirectorpolledmode.Themode

offlagoperationisdeterminedduringmasterresetviathestateoftheFMinput.Thisflagbusiscapable

ofHigh-Impedancestate,thisisimportantduringexpansionofMulti-Queuedevices.Duringdirect

operationthePAFnbusisupdatedtoshowthePAFstatusofaquadrantofqueueswithinaselecteddevice.

SelectionismadeusingWCLK,FSTR,WRADDandWADEN.DuringPolledoperationthePAFnbusis

loadedwiththePAFstatusofMulti-QueueFIFOquadrantssequentiallybasedontherisingedgeofWCLK.

Power Down

PartialReset

HSTL This inputis usedtoprovide additionalpowersavings. Whenthe device I/Ois setupforHSTL/eHSTL

INPUT modeaHIGHonthePDinputdisablesthedatainputsonthewriteportonly,providingsignificantpower

savings. In LVTTL mode this pin has no operation

PRS

LVTTL APartialResetcanbeperformedonasinglequeueselectedwithintheMulti-Queuedevice.BeforeaPartial

INPUT Resetcanbe performedona queue, thatqueue mustbe selectedonboththe write portandreadport

2clockcycles beforetheresetis performed.APartialResetis thenperformedbytakingPRS LOWfor

one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to

thefirstmemorylocation,noneofthedevicesconfigurationwillbechanged.

Q[17:0]

Qout

DataOutputBus

LVTTL Thesearethe18dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge

OUTPUT ofRCLKprovidedthatRENis LOW,OEis LOWandtheFIFOqueueis selected.Duetobus matching

notalloutputs maybeused,anyunusedoutputs shouldnotbeconnected.

RADEN

RCLK

ReadAddress Enable LVTTL The RADENinputis usedinconjunctionwithRCLKandthe RDADDaddress bus toselecta queue to

INPUT be read from. A FIFO queue addressed via the RDADD bus is selected on the rising edge of RCLK

provided that RADEN is HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR.

ReadClock

LVTTL WhenenabledbyREN,therisingedgeofRCLKreadsdatafromtheselectedFIFOqueueviatheoutput

INPUT busQout.TheFIFOqueuetobereadisselectedviatheRDADDaddressbusandarisingedgeofRCLK

whileRADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthe

PAEnflagquadranttobeplacedonthePAEnbusduringdirectflagoperation.Duringpolledflagoperation

thePAEnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronizedtoRCLK.ThePAE

andOV outputs are allsynchronizedtoRCLK. Duringdevice expansionthe EXOandEXIsignals are

basedonRCLK. RCLKmustbe continuous andfree-running.

IDT72T51543/72T515532.5V,MULTI-QUEUEFIFO(32QUEUES)

18BITWIDECONFIGURATION1,179,648and2,359,296bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/OTYPE

Description

RDADD

[7:0]

Read Address Bus

LVTTL For the 32Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The

INPUT firstfunctionofRDADDistoselectaFIFOqueuetobereadfrom.Theleastsignificant5bitsofthebus,

RDADD[4:0]areusedtoaddress1of32possiblequeueswithinaMulti-Queuedevice.Themostsignificant

3bits, RDADD[7:5]are usedtoselect1of8possible Multi-Queue devices thatmaybe connectedin

expansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent

ontheRDADDbuswillbeselectedonarisingedgeofRCLKprovidedthatRADENisHIGH,(note,that

datacanbeplacedontotheQoutbus,readfromthepreviouslyselectedFIFOqueueonthisRCLKedge).

On the next rising RCLK edge after a read queue select, a data word from the previous queue will be

placedontotheoutputs,Qout,regardlessoftheRENinput.TwoRCLKrisingedgesafterreadqueueselect,

datawillbeplacedontotheQoutoutputsfromthenewlyselectedqueue,regardlessofRENduetothe

firstwordfallthrougheffect.

ThesecondfunctionoftheRDADDbusistoselectthequadrantofFIFOqueuestobeloadedontothe

PAEnbusduringstrobedflagmode.Theleastsignificant2bits,RDADD[1:0]areusedtoselectthe

quadrantofadevicetobeplacedonthePAEnbus.Themostsignificant3bits,RDADD[7:5]areagain

usedtoselect1of8possibleMulti-Queuedevicesthatmaybeconnectedinexpansionmode.Address

bitsRDADD[4:2]aredon’tcareduringquadrantselection.ThequadrantaddresspresentontheRDADD

buswillbeselectedontherisingedgeofRCLKprovidedthatESTRisHIGH,(note,thatdatacanbeplaced

ontotheQoutbus,readfromthepreviouslyselectedFIFOQonthisRCLKedge).PleaserefertoTable2

for details on RDADD bus.

REN

ReadEnable

LVTTL The RENinputenables readoperations fromaselectedFIFOqueuebasedonarisingedgeofRCLK.

INPUT Aqueue tobe readfromcanbe selectedvia RCLK, RADENandthe RDADDaddress bus regardless

ofthestateofREN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond

RCLKcycle afterqueue selectionregardless ofREN due tothe FWFToperation. Areadenable is not

required to cycle the PAEn bus (in polled mode) or to select the PAEn quadrant , (in direct mode).

SCLK

SerialClock

LVTTL IfserialprogrammingoftheMulti-Queuedevicehasbeenselectedduringmasterreset,theSCLKinput

INPUT clockstheserialdatathroughtheMulti-Queuedevice.DatasetupontheSIinputisloadedintothedevice

ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed

theSCLKofalldevices shouldbeconnectedtothesamesource.

SENI

SerialInputEnable

LVTTL DuringserialprogrammingofaMulti-Queuedevice,dataloadedontotheSIinputwillbeclockedintothe

INPUT part(via a risingedge ofSCLK), providedthe SENI inputofthatdevice is LOW. Ifmultiple devices are

cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial

loadingofagivendeviceiscomplete,its SENOoutputgoesLOW,allowingthenextdeviceinthechain

tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI

inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.

SENO

SerialOutputEnable LVTTL ThisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingoftheMulti-Queuedevice

OUTPUT hasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO

willgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENOwillalso

goHIGH.WhentheSENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.

Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENO output

shouldbeconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogrammingofthe

firstdeviceiscomplete, SENOwillgoLOW,therebytakingtheSENIinputofthenextdeviceLOWand

soonthroughoutthe chain. Whena givendevice inthe chainis fullyprogrammedthe SENO output

essentiallyfollowstheSENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.

WhenthisoutputgoesLOW,serialloadingofalldeviceshasbeencompleted.

SerialIn

LVTTL DuringserialprogrammingthispinisloadedwiththeserialdatathatwillconfiguretheMulti-Queuedevices.

INPUT Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion

modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO

hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice

connectstotheSIpinofthesecondandsoon.TheMulti-Queuedevicesetupregistersareshiftregisters.

SerialOut

LVTTL Thisoutputisusedinexpansionmodeandallowsserialdatatobepassedthroughdevicesinthechain

OUTPUT tocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdeviceinthe

chain. The SOofthe finaldevice ina chainshouldnotbe connected.

IDT72T51543/72T515532.5V,MULTI-QUEUEFIFO(32QUEUES)

18BITWIDECONFIGURATION1,179,648and2,359,296bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/OTYPE

Description

TCK

JTAGClock

LVTTL ClockinputforJTAGfunction. TMSandTDIare sampledonthe risingedge ofTCK. TDOis outputon

INPUT thefallingedgeofTCK.

TDI

TestDataInput

TestDataOutput

LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK.

INPUT This is alsothedatafortheInstructionRegister,JTAGIDRegisterandBypass Register.

TDO

LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK.

INPUT ThisoutputisinHigh-ImpedanceexceptwhenshiftingdatawhileinSHIFT-DRandSHIFT-IRcontroller

states.

TMS

JTAGModeSelect

JTAGReset

LVTTL TMSis a serialinputpin. Bits are seriallyloadedonthe risingedge ofTCK, whichselects 1of5modes

INPUT ofoperationforthe JTAGboundaryscan.

TRST

WADEN

LVTTL TRSTistheasynchronousresetpinfortheJTAGcontroller.IftheJTAGportisnotutilized,TRSTshould

INPUT be tiedtoGND.

WriteAddressEnable LVTTL TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto

INPUT be written in to. A FIFO queue addressed via the WRADD bus is selected on the rising edge of WCLK

providedthatWADENis HIGH. WADENcannotbe HIGHforthe same WCLKcycle as FSTR.

WCLK

WriteClock

LVTTL WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheselectedFIFOqueueviatheinput

INPUT bus, Din. The FIFO queue to be written to is selected via the WRADD address bus and a rising edge

ofWCLKwhileWADENisHIGH.ArisingedgeofWCLKinconjunctionwithFSTRandWRADDwillalso

selectthe flagquadranttobe placedonthe PAFnbus duringdirectflagoperation. Duringpolledflag

operationthePAFnbusiscycledwithrespecttoWCLKandtheFSYNCsignalissynchronizedtoWCLK.

The PAFn, PAF andFF outputs are allsynchronizedtoWCLK. Duringdevice expansionthe FXOand

FXIsignals are basedonWCLK. The WCLKmustbe continuous andfree-running.

WEN

WriteEnable

LVTTL The WEN input enables write operations to a selected FIFO queue based on a rising edge of WCLK.

INPUT AqueuetobewrittentocanbeselectedviaWCLK,WADENandtheWRADDaddress bus regardless

ofthestateofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLK

cycleafterqueueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFn

bus (in polled mode) or to select the PAFn quadrant , (in direct mode).

WRADD

[7:0]

WriteAddressBus

LVTTL Forthe32QdevicetheWRADDbusis8bits.TheWRADDbusisadualpurposeaddressbus.Thefirst

INPUT functionofWRADDistoselectaFIFOqueuetobewrittento.Theleastsignificant5bitsofthebus,

WRADD[4:0]areusedtoaddress1of32possiblequeueswithinaMulti-Queuedevice.Themostsignificant

3bits,WRADD[7:5]areusedtoselect1of8possibleMulti-Queuedevices thatmaybeconnectedin

expansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent

ontheWRADDbuswillbeselectedonarisingedgeofWCLKprovidedthatWADENisHIGH,(note,that

datapresentontheDinbuscanbewrittenintothepreviouslyselectedFIFOqueueonthisWCLKedge

andonthenextrisingWCLKalso,providingthatWENisLOW).TwoWCLKrisingedgesafterwritequeue

select,datacanbewrittenintothenewlyselectedqueue.

ThesecondfunctionoftheWRADDbusistoselectthequadrantofFIFOqueuestobeloadedontothe

PAFnbusduringstrobedflagmode.Theleastsignificant2bits,WRADD[1:0]areusedtoselectthequadrant

ofadevicetobeplacedonthePAFnbus.Themostsignificant3bits,WRADD[7:5]areagainusedtoselect

1of8possibleMulti-Queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsWRADD[4:2]

aredon’tcareduringquadrantselection.ThequadrantaddresspresentontheWRADDbuswillbeselected

ontherisingedgeofWCLKprovidedthatFSTRisHIGH,(note,thatdatacanbewrittenintothepreviously

selectedFIFO queue on this WCLKedge). Please refertoTable 1 for details onthe WRADD bus.

VCC

+2.5VSupply

Power These are VCC power supply pins and must all be connected to a +2.5V supply rail.

VDDQ

O/PRailVoltage

Power Thesepinsmustbetiedtothedesiredoutputrailvoltage.ForLVTTLI/Othesepinsmustbeconnected

to+2.5V,forHSTLthesepinsmustbeconnectedto+1.5VandforeHSTLthesepinsmustbeconnected

to+1.8V.

GND

Vref

GroundPin

Power These are Ground pins and must all be connected to the GND supply rail.

ReferenceVoltage

HSTL ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable

INPUT "RecommendedDCOperatingConditions". The inputprovides the reference levelforHSTL/eHSTL

inputs. ForLVTTLI/Omode this inputshouldbe tiedtoGND.

NOTE:

1. Inputs should not change after Master Reset.

ORDERINGINFORMATION

IDT

XXXXX

Process /

Temperature

Range

Device Type

Power

Speed

Package

BLANK

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Plastic Ball Grid Array (PBGA, BB256-1)

7-5

Commercial Only

Commercial & Industrial

Clock Cycle Time (tCLK

Speed in Nanoseconds

)

Low Power

72T51543 1,179,648 bits 2.5V Multi-Queue FIFO

72T51553 2,359,296 bits 2.5V Multi-Queue FIFO

5999 drw34

NOTE:

1. Industrial temperature range product for 6ns and 7-5ns speed grades are available as a standard device. All other speed grades available by special order.

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

408-330-1753

email:FIFOhelp@idt.com

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

IDT72T51543L7-5BB [IDT]

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