IDT72T51546 [IDT]
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits; 2.5V多队列流量控制器件（ 32队列） 36位宽配置1,179,648位和2,359,296位
| 型号： | IDT72T51546 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 文件： | 总64页 (文件大小：611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION
1,179,648 bits and 2,359,296 bits
IDT72T51546
IDT72T51556
•
•
Direct or polled operation of flag status bus
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
– x36in to x36out
– x18in to x36out
– x9in to x36out
– x36in to x18out
– x36in to x9out
FWFT mode of operation on read port
Packet mode operation
Partial Reset, clears data in single Queue
Expansion of up to 8 multi-queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
FEATURES:
•
Choose from among the following memory density options:
IDT72T51546
IDT72T51556
Configurable from 1 to 32 Queues
Total Available Memory = 1,179,648 bits
Total Available Memory = 2,359,296 bits
•
•
•
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
Independent Read and Write access per queue
User programmable via serial port
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
Default multi-queue device configurations
– IDT72T51546 : 1,024 x 36 x 32Q
•
•
•
•
•
•
•
•
•
– IDT72T51556 : 2,048 x 36 x 32Q
•
•
•
•
•
•
•
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
Individual, Active queue flags (OV, FF, PAE, PAF, PR)
8 bit parallel flag status on both read and write ports
Shows PAE and PAF status of 8 Queues
•
•
•
•
FUNCTIONALBLOCKDIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
RADEN
ESTR
Q0
WADEN
FSTR
RDADD
8
WRADD
REN
Q1
Q2
8
RCLK
WEN
EREN
WCLK
ERCLK
OE
Q
out
D
in
x36
x36
DATA IN
DATA OUT
OV
PR
FF
PAF
PAFn
PAE
Q31
PAEn
PRn
8
8
5998 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc
NOVEMBER 2003
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5998/3
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Theuserhasfullflexibilityconfiguringqueueswithinthedevice,beingable
toprogramthetotalnumberofqueuesbetween1and32,theindividualqueue
depthsbeingindependentofeachother.Theprogrammableflagpositionsare
alsouserprogrammable.Allprogrammingisdoneviaadedicatedserialport.
Iftheuserdoesnotwishtoprogramthemulti-queuedevice,adefaultoptionis
availablethatconfiguresthedeviceinapredeterminedmanner.
BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster
Reset latches in all configuration setup pins and must be performed before
programmingofthedevicecantakeplace.APartialResetwillresetthereadand
writepointersofanindividualqueue,providedthatthequeueisselectedonboth
thewriteportandreadportatthetimeofpartialreset.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided.TheseareoutputsfromthereadportoftheQueuethatarerequired
forhighspeeddatacommunication,toprovidetightersynchronizationbetween
thedatabeingtransmittedfromtheQnoutputsandthedatabeingreceivedby
theinputdevice.Datareadfromthereadportisavailableontheoutputbuswith
respecttoERENandERCLK,thisisveryusefulwhendataisbeingreadathigh
speed.
Themulti-queueflow-controldevicehasthecapabilityofoperatingitsIOin
either2.5VLVTTL,1.5VHSTLor1.8VeHSTLmode.ThetypeofIOisselected
viatheIOSELinput.Thecoresupplyvoltage(VCC)tothemulti-queueisalways
2.5V,howevertheoutputlevelscanbesetindependentlyviaaseparatesupply,
VDDQ.
ThedevicesalsoprovideadditionalpowersavingsviaaPowerDownInput.
This input disables the write port data inputs when no write operations are
required.
DESCRIPTION:
TheIDT72T51546/72T51556multi-queueflow-controldevicesisasingle
chipwithinwhichanywherebetween1and32discreteFIFOqueuescanbe
setup.Allqueueswithinthedevicehaveacommondatainputbus,(writeport)
andacommondataoutputbus,(readport).Datawrittenintothewriteportis
directed to a respective queue via an internal de-multiplex operation, ad-
dressedbytheuser.Datareadfromthereadportisaccessedfromarespective
queueviaaninternalmultiplexoperation,addressedbytheuser.Datawrites
andreadscanbeperformedathighspeedsupto200MHz,withaccesstimes
of3.6ns.Datawriteandreadoperationsaretotallyindependentofeachother,
aqueuemaybeselectedonthewriteportandadifferentqueueontheread
portorbothportsmayselectthesamequeuesimultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.
Two8bitprogrammableflagbussesareavailable,providingstatusofqueues
notselectedforwriteorreadoperations.When8orlessqueuesareconfigured
in the device these flag busses provide an individual flag per queue, when
morethan8queuesareused,eitheraPolledorDirectmodeofbusoperation
providestheflagbusseswithallqueuesstatus.
Bus Matchingis availableonthis device,eitherportcanbe9bits,18bits
or36bitswideprovidedthatatleastoneportis36bitswide.WhenBusMatching
is usedthe device ensures the logicaltransferofdata throughputina Little
Endianmanner.
Apacketmodeofoperationisalsoprovidedwhenthedeviceisconfigured
for36bitinputand36bitoutputportsizes.ThePacketmodeprovidestheuser
withaflagoutputindicatingwhenatleastone(ormore)packetsofdatawithin
a queue is available for reading. The Packet Ready provides the user with
ameansbywhichtomarkthestartandendofpacketsofdatabeingpassed
throughthequeues.Themulti-queuedevicethenprovidestheuserwithan
internallygeneratedpacketreadystatusperqueue.
AJTAGtestportisprovided,herethemulti-queueflow-controldevicehasa
fullyfunctionalBoundaryScanfeature,compliantwithIEEE1149.1Standard
TestAccessPortandBoundaryScanArchitecture.
SeeFigure1,Multi-QueueFlow-ControlDeviceBlockDiagramforanoutline
ofthefunctionalblockswithinthedevice.
2
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D
= TEOP
= TSOP
D
35
34
in
x9, x18, x36
- D
D
2
D
0
35
WCLK
WEN
TMS
TDI
INPUT
DEMUX
JTAG
Logic
TDO
TCK
8
WRADD
WADEN
Write Control
Logic
TRST
Write Pointers
PR
Packet
Mode Logic
8
PAF
PRn/PAEn
FSTR
PAFn
8
General Flag
Monitor
FSYNC
Upto 32
FIFO
Queues
FXO
FXI
OV
Active Q
Flags
PAE
2.3 Mbit
Dual Port
Memory
Active Q
Flags
FF
PAF
PAE
SI
SO
SCLK
General Flag
Monitor
Serial
Multi-Queue
Program-
ming
ESTR
ESYNC
EXI
SENI
SENO
EXO
Read Pointers
FM
IW
OW
BM
8
Reset
Logic
RDADD
RADEN
NULL-Q
Read Control
Logic
MAST
PKT
REN
RCLK
ID0
ID1
ID2
DF
Device ID
3 Bit
OUTPUT
MUX
PAE/ PAF
2
Offset
Q
Q
= REOP
= RSOP
DFM
35
34
OUTPUT
REGISTER
EREN
PRS
MRS
ERCLK
5998 drw02
IOSEL
Vref
IO Level Control
&
Power Down
OE
Q
- Q
0
35
PD
Q
x9, x18, x36
out
Figure 1. Multi-Queue Flow-Control Device Block Diagram
3
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINCONFIGURATION
A1 BALL PAD CORNER
A
D14
D15
D17
D20
D23
D26
D29
D32
GND
PD
D13
D16
D12
D11
D19
D22
D25
D28
D31
D34
D35
VREF
D10
D9
Q9
Q8
Q7
Q15
Q19
D7
D6
D5
D4
D3
D2
D1
D0
TCK
TMS
TDO
TDI
ID2
ID1
ID0
Q3
Q2
Q1
Q6
Q5
Q4
Q12
Q11
Q10
Q16
Q24
Q14
Q13
Q17
Q21
Q23
B
C
D
E
F
D18
D8
TRST
IOSEL
Q0
Q18
Q20
Q22
D21
VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
VDDQ
VDDQ
VDDQ
VCC
V
CC
GND
GND
GND
GND
VCC
GND
GND
GND
GND
GND
VCC
VDDQ
VDDQ
GND
GND
D24
VDDQ
VCC
VDDQ
VCC
GND
VCC
VDDQ
D27
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
Q27
Q30
Q25
Q28
Q26
Q29
G
H
J
D30
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
D33
VCC
GND
GND
VCC
Q33
PKT
GND
Q32
Q31
Q34
FM
GND
GND
NULL-Q
GND
VCC
VCC
Q35
K
L
ADVANCE
VCC
VCC
VCC
MAST
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SI
VDDQ
GND
VCC
DFM
DF
SO
VCC
GND
VDDQ
BM
IW
OW
GND
M
N
P
R
T
SENO
SENI
OE
VDDQ
RDADD0 RDADD1
VDDQ
VDDQ
VCC
VCC
VCC
VCC
VDDQ
VDDQ
WRADD1 WRADD0 SCLK
RDADD2 RDADD3 RDADD4
VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
VCC
V
DDQ
VDDQ
INFORMATION
WRADD4 WRADD3 WRADD2 WADEN
FF
PAF
PRS
OV
RDADD5 RDADD6 RDADD7
PAF3
PAF2
PAF1
PAF6
PAF5
WEN
PAF7
PAE
PAE6
PAE5
PAE4
PAE7
EREN
REN
PAE3
PAE2
PAE1
WRADD6 WRADD5 FSYNC
ESTR ESYNC
RADEN
FSTR
PR
ERCLK
RCLK
PAF4
EXO
EXI
WRADD7 FXI
FXO
MRS
PAE0
PAF0
WCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
5998 drw03
PBGA (BB256-1, order code: BB)
TOP VIEW
4
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
respectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus
for that queue. Conversely, the read port has an output valid flag, providing
statusofthedatabeingreadfromthequeueselectedonthereadport.Aswell
astheoutputvalidflagthedeviceprovidesadedicatedalmostemptyflag.This
almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.
Thedeviceprovidesauserprogrammablealmostemptyflagforall32queues
andwhenarespectivequeueisselectedonthereadport,thealmostemptyflag
providesstatusforthatqueue.
DETAILEDDESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
singledataoutputportwithupto32FIFOqueuesinparallelbufferingbetween
thetwoports.Theusercansetupbetween1and32Queueswithinthedevice.
Thesequeuescanbeconfiguredtoutilizethetotalavailablememory,providing
theuserwithfullflexibilityandabilitytoconfigurethequeuestobevariousdepths,
independentofoneanother.
PROGRAMMABLE FLAG BUSSES
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost
fullflagstatusbusisprovided,thisbusis8bitswide.Also,analmostemptyflag
statusbusisprovided,againthisbusis8bitswide.Thepurposeoftheseflag
bussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels
withinqueuesthatmaynotbeselectedonthewriteorreadport.Asmentioned,
thedeviceprovidesalmostfullandalmostemptyregisters(programmableby
the user) for each of the 32 queues in the device.
IntheIDT72T51546/72T51556multi-queueflow-controldevicestheuser
has theoptionofutilizinganywherebetween1and32queues,thereforethe
8bitflagstatusbussesaremultiplexedbetweenthe32queues,aflagbuscan
onlyprovidestatusfor8ofthe32queuesatanymoment,thisisreferredtoas
a“Quadrant”,suchthatwhenthebusisprovidingstatusofqueues1through
8,thisisquadrant1,whenitisqueues9through16,thisisquadrant2andso
onuptoquadrant4. Ifless than32queues are setupinthe device, there are
still4quadrants,suchthatin“Polled”modeofoperationtheflagbuswillstillcycle
through4quadrants.Ifforexampleonly22queuesaresetup,quadrants1and
2 will reflect status of queues 1 through 8 and 9 through 16 respectively.
Quadrant3willreflectthestatusofqueues17through22ontheleastsignificant
6bits,themostsignificant2bitsoftheflagbusaredon’tcareandthe4thquadrant
outputswillbedon’tcarealso.
MEMORYORGANIZATION/ALLOCATION
Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing
256x36bits.Whentheuserisconfiguringthenumberofqueuesandindividual
queuesizestheusermustallocatethememorytorespectivequeues,inunits
ofblocks,thatis,asinglequeuecanbemadeupfrom0tomblocks,wherem
isthetotalnumberofblocksavailablewithinadevice.Alsothetotalsizeofany
given queue must be in increments of 256 x36. For the IDT72T51546 and
IDT72T51556theTotalAvailableMemoryis128and256blocksrespectively
(a blockbeing256x36). Queues canbe builtfromthese blocks tomake any
size queue desired and any number of queues desired.
BUS WIDTHS
Theinputportiscommontoallqueueswithinthedevice,asistheoutputport.
ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinputport
andoutputportcanbeeitherx9,x18orx36bitswideprovidedthatatleastone
of the ports is x36 bits wide, the read and write port widths being set
independentlyofoneanother.Becausetheportsarecommontoallqueuesthe
widthofthequeuesisnotindividuallyset,sothattheinputwidthofallqueues
are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
The flag busses are available in two user selectable modes of operation,
“Polled”or“Direct”.Whenoperatinginpolledmodeaflagbusprovidesstatus
ofeachquadrantsequentially,thatis,oneachrisingedgeofaclocktheflagbus
isupdatedtoshowthestatusofeachquadrantinorder.Therisingedgeofthe
writeclockwillupdatethealmostfullbusandarisingedgeonthereadclockwill
updatethealmostemptybus.Themodeofoperationisalwaysthesameforboth
thealmostfullandalmostemptyflagbusses.Whenoperatingindirectmode,the
quadrantontheflagbusisselectedbytheuser.Sotheusercanactuallyaddress
thequadranttobeplacedontheflagstatusbusses,theseflagbussesoperate
independentlyofoneanother.Addressingofthealmostfullflagbusisdonevia
thewriteportandaddressingofthealmostemptyflagbusisdoneviatheread
port.
Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete
queueviathewritequeueselectaddressinputs.Conversely,databeingread
fromthedevicereadportisreadfromaqueueselectedviathereadqueueselect
addressinputs.Datacanbesimultaneouslywrittenintoandreadfromthesame
queueordifferentqueues.Onceaqueueisselectedfordatawritesorreads,
the writing and reading operation is performed in the same manner as a
conventionalIDTsynchronous FIFO,utilizingclocks andenables,thereis a
singleclockandenableperport.Whenaspecificqueueisaddressedonthe
writeport,dataplacedonthedatainputsiswrittentothatqueuesequentially
basedontherisingedgeofawriteclockprovidedsetupandholdtimesaremet.
Conversely,dataisreadontotheoutputportafteranaccesstimefromarising
edge on a read clock.
Theoperationofthewriteportiscomparabletothefunctionofaconventional
FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput
provides status of the selected queue. The operation of the read port is
comparabletothefunctionofaconventionalFIFOoperatinginFWFTmode.
Whenaqueueis selectedontheoutputport,thenextwordinthatqueuewill
automaticallyfallthroughtotheoutputregister.Allsubsequentwordsfromthat
queue require an enabled read cycle. Data cannot be read from a selected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
whendata readoutis valid. Ifthe userswitches toa queue thatis empty, the
lastwordfromtheprevious queuewillremainontheoutputregister.
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost
fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice
provides a user programmable almost full flag for all 32 queues and when a
PACKETREADY
Themulti-queueflow-controldevicealsooffersa“PacketMode”operation.
PacketModeisuserselectableandrequiresthedevicetobeconfiguredwith
bothwriteandreadportsas36bitswide.Inpacketmode,userscandefinethe
lengthofpacketsorframebyusingthetwomostsignificantbitsofthe36-bitword.
Bit34isusedtomarktheStartofPacket(SOP)andbit35isusedtomarkthe
EndofPacket(EOP)asshowninTable5).Whenwritingdataintoagivenqueue
,thefirstwordbeingwrittenis marked,bytheusersettingbit34as the“Start
ofPacket”(SOP)andthelastwordwrittenismarkedasthe“EndofPacket”(EOP)
withallwordswrittenbetweentheStartofPacket(SOP)marker(bit34)andthe
Endofpacket(EOP)packetmarker(bit35)constitutingthe entire packet. A
packetcanbeanylengththeuserdesires,uptothetotalavailablememoryin
themulti-queuedevice.ThedevicemonitorstheSOP(bit34)andlooksforthe
wordthatcontainstheEOP(bit35).Thereadportissuppliedwithanadditional
5
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
statusflag,“PacketReady”.ThePacketReady(PR)flaginconjunctionwith memoryblocks withinamulti-queuedevicecanbeallocatedtoincreasethe
OutputValid(OV)indicateswhenatleastonepacketisavailabletoread.When depth of a queue. For example, depth expansion of 8 devices provides the
inpacketmodethealmostemptyflagstatus,providespacketreadyflagstatus possibilityof8queuesof64Kx36deep,eachqueuebeingsetupwithinasingle
forindividualqueues.
deviceutilizingallmemoryblocksavailabletoproduceasinglequeue.Thisis
thedeepestqueuethatcansetupwithinadevice.
EXPANSION
Forqueue expansiona maximumnumberof256(8x32)queues maybe
Expansionofmulti-queuedevicesisalsopossible,upto8devicescanbe setup, each queue being 2K x36 deep, if less queues are setup, then more
connectedinaparallelfashionprovidingthepossibilityofbothdepthexpansion memory blocks will be available to increase queue depths if desired. When
or queue expansion. Depth Expansion means expanding the depths of connectingmulti-queuedevicesinexpansionmodeallrespectiveinputpins
individual queues. Queue expansion means increasing the total number of (data&control)andoutputpins(data&flags),shouldbe“connected”together
queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore betweenindividualdevices.
6
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS
Symbol &
Pin No.
Name
I/OTYPE
Description
BM
(L14)
BusMatching
LVTTL
INPUT
ThispinissetupbeforeMasterResetandmustnottoggleduringanydeviceoperation.Thispinisused
alongwithIWandOWtosetupthemulti-queueflow-controldevicebuswidth.PleaserefertoTable3
fordetails.
D[35:0]
DataInputBus HSTL-LVTTL These are the 36data inputpins. Data is writtenintothe device via these inputpins onthe risingedge
Din
INPUT
ofWCLKprovidedthatWEN is LOW.Note,thatinPacketmodeD32-D35maybeusedas packet
markers,pleaseseepacketreadyfunctionaldiscussionformoredetail.Duetobusmatchingnotallinputs
maybe used, anyunusedinputs shouldbe tiedLOW.
(See Pin No.
tablefordetails)
DF(1)
(L3)
DefaultFlag
DefaultMode
LVTTL
INPUT
Iftheuserrequiresdefaultprogrammingofthemulti-queuedevice,thispinmustbesetupbeforeMaster
Resetandmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
(1)
DFM
(L2)
LVTTL
INPUT
The multi-queue device requires programmingaftermasterreset. The usercandothis seriallyvia the
serialport,ortheusercanusethedefaultmethod.IfDFMisLOWatmasterresetthenserialmodewillbe
selected,ifHIGHthendefaultmodeisselected.
ERCLK
(R10)
RCLK Echo
HSTL-LVTTL ReadClockEchooutput,thisoutputgeneratesaclockbasedonthereadclockinput,thisisusedforSource
OUTPUT SynchronousclockingwherethereceivingdevicesutilizestheERCLKtoclockdataoutputfromtheQueue.
HSTL-LVTTL ReadEnableEchooutput,canbeusedinconjunctionwiththeERCLKoutputtoloaddataoutputfromthe
EREN
(R11)
REN Echo
OUTPUT
Queueintothereceivingdevice.
ESTR
(R15)
PAEn Flag Bus
Strobe
LVTTL
INPUT
IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK
andtheRDADDbustoselectaquadrantofqueuestobeplacedontothePAEnbusoutputs.Aquadrant
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polledoperationshasbeenselected,ESTRshouldbetiedinactive,LOW.Note,thataPAEnflagbus
selectioncannotbemade,(ESTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
andSENO has gone LOW.
ESYNC
(R16)
PAEn Bus Sync HSTL-LVTTL ESYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAEnbus
OUTPUT
duringPolledoperationofthePAEnbus.DuringPolledoperationeachquadrantofqueuestatusflagsis
loadedontothePAEnbus outputs sequentiallybasedonRCLK. The firstRCLKrisingedge loads
quadrant1ontoPAEn,thesecondRCLKrisingedgeloadsquadrant2andsoon.ThefifthRCLKrising
edge will again load quadrant 1. During the RCLK cycle that quadrant 1 of a selected device is placed
ontothePAEnbus,theESYNCoutputwillbeHIGH.Forallotherquadrantsofthatdevice,theESYNC
outputwillbeLOW.
EXI
(T16)
PAEnBus
ExpansionIn
LVTTL
INPUT
The EXIinputis usedwhenmulti-queue devices are connectedinexpansionmode andPolledPAEn
bus operationhas beenselected. EXIofdevice ‘N’connects directlytoEXOofdevice ‘N-1’. The EXI
receives a tokenfromthe previous device ina chain. Insingle device mode the EXIinputmustbe tied
LOWifthePAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheEXIinput
mustbeconnectedtotheEXOoutputofthesamedevice.InexpansionmodetheEXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
EXO
(T15)
PAEnBus
ExpansionOut
LVTTL
OUTPUT
EXOis anoutputthatis usedwhenmulti-queuedevices areconnectedinexpansionmodeandPolled
PAEnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.This
pinpulses whendevice Nhas placedits final(4th)quadrantontothe PAEnbus withrespecttoRCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising
edgethefirstquadrantofdeviceN+1willbeloadedontothePAEnbus.Thiscontinuesthroughthechain
andEXOofthelastdeviceisthenloopedbacktoEXIofthefirstdevice.TheESYNCoutputofeachdevice
inthechainprovides synchronizationtotheuserofthis loopingevent.
FF
(P8)
Full Flag
HSTL-LVTTL This pinprovidesthefullflagoutputfortheactiveQueue,thatis,thequeueselectedontheinputport
OUTPUT
forwriteoperations,(selectedviaWCLK,WRADDbusandWADEN).OntheWCLKcycleafteraqueue
selection,thisflagwillshowthestatusofthenewlyselectedqueue.Datacanbewrittentothisqueueon
thenextcycleprovidedFF is HIGH.This flaghas High-Impedancecapability,this is importantduring
expansionofdevices,whentheFFflagoutputofupto8devicesmaybeconnectedtogetheronacommon
line.ThedevicewithaqueueselectedtakescontroloftheFFbus,allotherdevicesplacetheirFFoutput
intoHigh-Impedance.Whenaqueueselectionismadeonthewriteportthisoutputwillswitchfrom
High-ImpedancecontrolonthenextWCLKcycle.ThisflagissynchronizedtoWCLK.
7
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Name
I/OTYPE
Description
Pin No.
(1)
FM
Flag Mode
HSTL-LVTTL Thispinissetupbeforeamasterresetandmustnottoggleduringanydeviceoperation.Thestateofthe
(K16)
INPUT
FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbussesoperateineitherPolled
orDirectmode.Ifthis pinis HIGHthemodeis Polled,ifLOWthenitwillbeDirect.
FSTR
(R4)
PAFn Flag Bus
Strobe
LVTTL
INPUT
IfdirectoperationofthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK
andtheWRADDbustoselectaquadrantofqueuestobeplacedontothePAFnbusoutputs.Aquadrant
addressedviatheWRADDbus is selectedontherisingedgeofWCLKprovidedthatFSTRis HIGH.If
Polledoperations has beenselected,FSTRshouldbetiedinactive,LOW.Note,thataPAFnflagbus
selectioncannotbemade,(FSTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
andSENO has gone LOW.
FSYNC
(R3)
PAFn Bus Sync
LVTTL
OUTPUT
FSYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAFnbus
duringPolledoperationofthePAFnbus.DuringPolledoperationeachquadrantofqueuestatusflags
is loadedontothePAFnbus outputs sequentiallybasedonWCLK.ThefirstWCLKrisingedgeloads
quadrant1ontoPAFn,thesecondWCLKrisingedgeloadsquadrant2andsoon.ThefifthWCLKrising
edgewillagainloadquadrant1.DuringtheWCLKcyclethatquadrant1ofaselecteddeviceis placed
ontothePAFnbus,theFSYNCoutputwillbeHIGH.Forallotherquadrantsofthatdevice,theFSYNC
outputwillbeLOW.
FXI
(T2)
PAFnBus
ExpansionIn
LVTTL
INPUT
The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn
bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receives a tokenfromthe previous device ina chain. Insingle device mode the FXIinputmustbe tied
LOWifthePAFnbusisoperatedindirectmode.IfthePAFnbusisoperatedinpolledmodetheFXIinput
mustbeconnectedtotheFXOoutputofthesamedevice.InexpansionmodetheFXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
FXO
(T3)
PAFnBus
ExpansionOut
LVTTL
OUTPUT
FXOisanoutputthatisusedwhenmulti-queuedevicesareconnectedinexpansionmodeandPolled
PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This
pinpulseswhendeviceNhasplaceditsfinal(4th)quadrantontothePAFnbuswithrespecttoWCLK.
This pulse (token)is thenpassedontothe nextdevice inthe chain‘N+1’andonthe nextWCLKrising
edgethefirstquadrantofdeviceN+1willbeloadedontothePAFnbus.Thiscontinuesthroughthechain
andFXOofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdevice
inthechainprovides synchronizationtotheuserofthis loopingevent.
(1)
ID[2:0]
Device ID Pins HSTL-LVTTL Forthe32Qmulti-queuedevicetheWRADDandRDADDaddressbussesare8bitswide.Whenaqueue
ID2-C9
ID1-A10
ID0-B10
INPUT
selectiontakes placethe3MSb’s ofthis 8bitaddress bus areusedtoaddress thespecificdevice(the
5 LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s
oftheaddressarecomparedtothedeviceIDpins.Thefirstdeviceinachainofmulti-queue’s(connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which
is‘111’,howevertheIDdoesnothavetomatchthedeviceorder.Insingledevicemodethesepinsshould
besetupas‘000’andthe3MSb’softheWRADDandRDADDaddressbussesshouldbetiedLOW.The
ID[2:0]inputssetuparespectivedevicesIDduringmasterreset.TheseIDpinsmustnottoggleduring
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
IOSEL
(C8)
IOSelect
LVTTL
INPUT
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
required then IOSEL should be tied HIGH. If LVTTL I/O are required then it should be tied LOW.
(1)
IW
InputWidth
LVTTL
INPUT
ThispinisusedinconjunctionwithOWandBMtosetuptheinputandoutputbuswidthstobeacombination
of x9, x18 or x36, (providing that one port is x36).
(L15)
(1)
MAST
MasterDevice HSTL-LVTTL ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe
(K15)
INPUT
Masterdevice ora Slave. Ifthis pinis HIGH, the device is the masterifitis LOWthenitis a Slave. The
masterdeviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgotoHigh-
Impedance,preventingbuscontention.Ifamulti-queuedeviceisbeingusedinsingledevicemode,this
pinmustbesetHIGH.
MRS
MasterReset
HSTL-LVTTL AmasterresetisperformedbytakingMRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired
INPUT aftermasterreset.
HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD
(T9)
NULL-Q
(J2)
NullQueue
Select
INPUT
and RADEN address bus to address the Null-Q.
8
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
OE
(M14)
OutputEnable HSTL-LVTTL TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontrolofthemulti-queue
INPUT
dataoutputbus,Qout.Ifadevicehasbeenconfiguredasa“Master”device,theQoutdataoutputswill
beinaLowImpedanceconditioniftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbe
inHighImpedance.Ifadeviceisconfigureda“Slave”device,thentheQoutdataoutputswillalwaysbe
inHighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpointOEprovidesthree-
stateofthatrespectivedevice.
OV
OutputValid
Flag
HSTL-LVTTL Thisoutputflagprovidesoutputvalidstatusforthedatawordpresentonthemulti-queueflow-controldevice
(P9)
OUTPUT
dataoutputport,Qout.Thisflagistherefore,2-stagedelayedtomatchthedataoutputpathdelay.That
is, there is a 2RCLKcycle delayfromthe time a givenqueue is selectedforreads, tothe time the OV
flagrepresents the data inthatrespective queue. Whena selectedqueue onthe readportis readto
empty,theOVflagwillgoHIGH,indicatingthatdataontheoutputbusisnotvalid.TheOVflagalsohas
High-Impedancecapability,requiredwhenmultipledevicesareusedandtheOVflagsaretiedtogether.
(1)
OW
(L16)
OutputWidth
LVTTL
INPUT
ThispinissetupduringMasterResetandmustnottoggleduringanydeviceoperation.Thispinisused
inconjunctionwithIWandBMtosetupthedatainputandoutputbuswidthstobeacombinationofx9,
x18 or x36, (providing that one port is x36).
PAE
(P10)
Programmable HSTL-LVTTL ThispinprovidestheAlmost-EmptyflagstatusfortheQueuethathasbeenselectedontheoutputport
Almost-Empty
Flag
OUTPUT
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
Queueisalmost-empty.ThisflagoutputmaybeduplicatedononeofthePAEnbuslines.Thisflagis
synchronizedtoRCLK.
PAEn/PRn
(PAE7-P11
PAE6-P12
PAE5-R12
PAE4-T12
PAE3-P13
PAE2-R13
PAE1-T13
PAE0-T14)
Programmable HSTL-LVTTL Onthe 32Qdevice the PAEn/PRnbus is 8bits wide. Duringa MasterResetthis bus is setupforeither
Almost-Empty
OUTPUT
AlmostEmptymodeorPacketmode.ThisoutputbusprovidesPAE/PRnstatusof8queues(1quadrant),
withinaselecteddevice,havingatotalof4quadrants.DuringQueueread/writeoperationstheseoutputs
provideprogrammableemptyflagstatusorpacketreadystatus,ineitherdirectorpolledmode.Themode
offlagoperationisdeterminedduringmasterresetviathestateoftheFMinput.Thisflagbusiscapableof
High-Impedancestate,thisisimportantduringexpansionofmulti-queuedevices.Duringdirectoperation
thePAEn/PRnbusisupdatedtoshowthePAE/PRstatusofaquadrantofqueueswithinaselecteddevice.
Selection is made using RCLK, ESTR and RDADD. During Polled operation the PAEn/PRn bus is
loadedwiththePAE/PRnstatusofmulti-queueflow-controlquadrantssequentiallybasedontherising
edge ofRCLK. PAE orPR operationis determinedbythe state ofPKTduringmasterreset.
FlagBus/Packet
ReadyFlag Bus
PAF
(R8)
Programmable HSTL-LVTTL ThispinprovidestheAlmost-FullflagstatusfortheQueuethathasbeenselectedontheinputportfor
Almost-FullFlag OUTPUT
writeoperations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselected
Queueisalmost-full.ThisflagoutputmaybeduplicatedononeofthePAFnbuslines.Thisflagis
synchronizedtoWCLK.
PAFn
Programmable HSTL-LVTTL Onthe 32Qdevice the PAFnbus is 8bits wide. Atanyone time this outputbus provides PAF status
(PAF7-P7
PAF6-P6
PAF5-R6
PAF4-R7
PAF3-P5
PAF2-R5
PAF1-T5
PAF0-T4)
Almost-FullFlag OUTPUT
Bus
of 8 queues (1 quadrant), within a selected device, having a total of 4 quadrants. During Queue read/
writeoperationstheseoutputsprovideprogrammablefullflagstatus,ineitherdirectorpolledmode.The
modeofflagoperationisdeterminedduringmasterresetviathestateoftheFMinput.Thisflagbusis
capableofHigh-Impedancestate,thisisimportantduringexpansionofmulti-queuedevices.Duringdirect
operationthePAFnbus is updatedtoshowthe PAF status ofaquadrantofqueues withinaselected
device.SelectionismadeusingWCLK,FSTR,WRADDandWADEN.DuringPolledoperationthePAFn
busisloadedwiththePAFstatusofmulti-queueflow-controlquadrantssequentiallybasedontherising
edgeofWCLK.
PD
(K1)
Power Down
PacketMode
HSTL
INPUT
This inputis usedtoprovide additionalpowersavings. Whenthe device I/Ois setupforHSTL/eHSTL
modeaHIGHonthePDinputdisablesthedatainputsonthewriteportonly,providingsignificantpower
savings. In LVTTL mode this pin has no operation
(1)
PKT
(J14)
LVTTL
INPUT
ThestateofthispinduringaMasterResetwilldeterminewhetherthepartisoperatinginPacketmode
providingbothaPacketReady(PR)outputandaProgrammableAlmostEmpty(PAE)discreteoutput,
or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will
operateinpacketmode,ifitisLOWthenalmostemptymode.Ifpacketmodehasbeenselectedtheread
portflagbusbecomespacketreadyflagbus,PRnandthediscretepacketreadyflag,PRisfunctional.
Ifalmostemptyoperationhasbeenselectedthentheflagbusprovidesalmostemptystatus,PAEnand
9
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
(1)
Name
I/OTYPE
Description
PKT
PacketMode
LVTTL
INPUT
thediscretealmostemptyflag,PAEisfunctional,thePRflagisinactiveandshouldnotbeconnected.
PacketReadyutilizesusermarkedlocationstoidentifystartandendofpacketsbeingwrittenintothe
device.PacketModecanonlybeselectedifboththeinputportwidthandoutputportwidthare36bits.
(Continued)
(J14)
PR
(R9)
PacketReady HSTL-LVTTL IfpacketmodehasbeenselectedthisflagoutputprovidesPacketReadystatusoftheQueueselected
Flag
OUTPUT
forreadoperations.DuringamasterresetthestateofthePKTinputdetermineswhetherPacketmode
ofoperationwillbeused.IfPacketmodeisselected,thentheconditionofthePRflagandOVsignalare
assertedindicatesapacketisreadyforreading.Theusermustmarkthestartofapacketandtheendof
apacketwhenwritingdataintoaqueue.UsingtheseStartOfPacket(SOP)andEndOfPacket(EOP)
markers,themulti-queuedevicesetsPRLOWifoneormore“complete”packetsareavailableinthequeue.
Acompletepacket(s)mustbewrittenbeforetheuserisallowedtoswitchqueues.
PRS
(T8)
PartialReset
HSTL-LVTTL APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial
INPUT
Resetcanbe performedona queue, thatqueue mustbe selectedonboththe write portandreadport
2clockcycles beforetheresetis performed.APartialResetis thenperformedbytakingPRSLOWfor
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
thefirstmemorylocation,noneofthedevicesconfigurationwillbechanged.
Q[35:0]
DataOutputBus HSTL-LVTTL Thesearethe36dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge
Qout
(See Pin No.
tablefordetails)
OUTPUT
ofRCLKprovidedthatRENisLOW,OEisLOWandtheQueueisselected.Note,thatinPacketReady
modeQ32-Q35maybeusedaspacketmarkers,pleaseseepacketreadyfunctionaldiscussionformore
detail.Duetobusmatchingnotalloutputsmaybeused,anyunusedoutputsshouldnotbeconnected.
RADEN
(R14)
ReadAddress HSTL-LVTTL The RADENinputis usedinconjunctionwithRCLKandthe RDADDaddress bus toselecta queue to
Enable
INPUT
bereadfrom.AqueueaddressedviatheRDADDbusisselectedontherisingedgeofRCLKprovided
thatRADENisHIGH.RADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).RADEN
shouldnotbepermanentlytiedHIGH.RADENcannotbeHIGHforthesameRCLKcycleasESTR.Note,
thatareadqueueselectioncannotbemade,(RADENmustNOTgoactive)untilprogrammingofthe
parthas beencompletedandSENO has goneLOW.
RCLK
(T10)
ReadClock
HSTL-LVTTL When enabledbyREN, the risingedge ofRCLKreads data fromthe selectedqueue via the output
INPUT
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
whileRADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthe
PAEn/PRnflagquadranttobeplacedonthePAEn/PRnbusduringdirectflagoperation.Duringpolled
flagoperationthePAEn/PRnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronized
toRCLK.ThePAE,PRandOVoutputsareallsynchronizedtoRCLK.DuringdeviceexpansiontheEXO
and EXI signals are based on RCLK. RCLK must be continuous and free-running.
RDADD
ReadAddress HSTL-LVTTL Forthe32QdevicetheRDADDbus is 8bits.TheRDADDbus is adualpurposeaddress bus.Thefirst
[7:0]
Bus
INPUT
functionofRDADDistoselectaQueuetobereadfrom.Theleastsignificant5bitsofthebus,RDADD[4:0]
areusedtoaddress 1of32possiblequeueswithinamulti-queuedevice.Themostsignificant3bits,
RDADD[7:5]areusedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
RDADDbus willbe selectedona risingedge ofRCLKprovidedthatRADENis HIGH, (note, thatdata
canbeplacedontotheQoutbus,readfromthepreviouslyselectedqueueonthisRCLKedge).Onthe
next rising RCLK edge after a read queue select, a data word from the previous queue will be placed
ontotheoutputs,Qout,regardless oftheREN input.TwoRCLKrisingedges afterreadqueueselect,
datawillbeplacedontotheQoutoutputsfromthenewlyselectedqueue,regardlessofRENduetothe
firstwordfallthrougheffect.
(RDADD7-P16
RDADD6-P15
RDADD5-P14
RDADD4-N16
RDADD3-N15
RDADD2-N14
RDADD1-M16
RDADD0-M15)
The secondfunctionofthe RDADDbus is toselectthe quadrantofqueues tobe loadedontothe
PAEn/PRnbusduringstrobedflagmode.Theleastsignificant2bits,RDADD[1:0]areusedtoselectthe
quadrantofadevicetobeplacedonthePAEnbus.Themostsignificant3bits,RDADD[7:5]areagain
usedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansionmode.Address
bitsRDADD[4:2]aredon’tcareduringquadrantselection.ThequadrantaddresspresentontheRDADD
buswillbeselectedontherisingedgeofRCLKprovidedthatESTRisHIGH,(note,thatdatacanbeplaced
ontotheQoutbus,readfromthepreviouslyselectedQueueonthisRCLKedge).PleaserefertoTable2
fordetails onRDADDbus.
10
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
REN
(T11)
ReadEnable
HSTL-LVTTL The REN input enables read operations from a selected Queue based on a rising edge of RCLK.
INPUT
A queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless
ofthestateofREN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond
RCLKcycle afterqueue selectionregardless ofREN due tothe FWFToperation. Areadenable is not
requiredtocyclethe PAEn/PRnbus(inpolledmode)ortoselectthePAEnquadrant,(indirectmode).
SCLK
(N3)
SerialClock
HSTL-LVTTL Ifserialprogrammingofthemulti-queuedevicehasbeenselectedduringmasterreset,theSCLKinput
INPUT
clockstheserialdatathroughthemulti-queuedevice.DatasetupontheSIinputisloadedintothedevice
ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed
theSCLKofalldevices shouldbeconnectedtothesamesource.
SENI
(M2)
SerialInput
Enable
HSTL-LVTTL Duringserialprogrammingofamulti-queuedevice,dataloadedontotheSIinputwillbeclockedintothe
INPUT
part(via a risingedge ofSCLK), providedthe SENI inputofthatdevice is LOW. Ifmultiple devices are
cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
loadingofagivendeviceiscomplete,its SENOoutputgoesLOW,allowingthenextdeviceinthechain
tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.
SENO
(M1)
SerialOutput
Enable
HSTL-LVTTL Thisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingofthemulti-queuedevice
OUTPUT hasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO
willgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENOwillalso
goHIGH.WhentheSENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.
Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENO output
shouldbeconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogrammingofthe
firstdeviceiscomplete,SENO willgoLOW,therebytakingtheSENIinputofthenextdeviceLOWand
soonthroughoutthe chain. Whena givendevice inthe chainis fullyprogrammedthe SENO output
essentiallyfollowstheSENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.
WhenthisoutputgoesLOW,serialloadingofalldeviceshasbeencompleted.
SI
SerialIn
HSTL-LVTTL Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.
(L1)
INPUT
Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO
hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connectstotheSIpinofthesecondandsoon.Themulti-queuedevicesetupregistersareshiftregisters.
SO
(M3)
SerialOut
HSTL-LVTTL Thisoutputisusedinexpansionmodeandallowsserialdatatobepassedthroughdevicesinthechain
OUTPUT tocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdeviceinthe
chain. The SOofthe finaldevice ina chainshouldnotbe connected.
(2)
TCK
(A8)
JTAGClock
LVTTL
INPUT
ClockinputforJTAGfunction.Oneoffourterminals requiredbyIEEEStandard1149.1-1990.Test
operationsofthedevicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedge
ofTCKandoutputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneeds
tobe tiedtoGND.
(2)
TDI
JTAGTestData
Input
LVTTL
INPUT
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,
testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegister
andBypassRegister.Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(B9)
(2)
TDO
(A9)
JTAGTestData
Output
LVTTL
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
OUTPUT operation,testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstruction
Register,IDRegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whilein
SHIFT-DR and SHIFT-IR controller states.
TMS(2)
(B8)
JTAGMode
Select
LVTTL
INPUT
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthe
devicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST
(C7)
JTAGReset
LVTTL
INPUT
TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
resetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHforfiveTCKcycles.
IftheTAPcontrollerisnotproperlyresetthentheoutputswillalwaysbeinhigh-impedance.IftheJTAG
function is used but the user does not want to use TRST, thenTRST can be tied with MRS to ensure
11
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Name
I/OTYPE
Description
Pin No.
(2)
TRST
JTAGReset
LVTTL
properqueue operation. Ifthe JTAGfunctionis notusedthenthis signalneeds tobe tiedtoGND. An
internalpull-upresistorforcesTRSTHIGHifleftunconnected.
(Continued)
WADEN
(P4)
WriteAddress HSTL-LVTTL TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto
Enable
INPUT
bewritteninto.AqueueaddressedviatheWRADDbusisselectedontherisingedgeofWCLKprovided
thatWADENisHIGH.WADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).WADEN
shouldnotbepermanentlytiedHIGH.WADENcannotbeHIGHforthesameWCLKcycleasFSTR.Note,
thatawritequeueselectioncannotbemade,(WADENmustNOTgoactive)untilprogrammingofthepart
has beencompletedandSENO has goneLOW.
WCLK
(T7)
WriteClock
HSTL-LVTTL WhenenabledbyWEN,therisingedgeofWCLKwrites dataintotheselectedQueueviatheinput
INPUT
bus, Din. The Queue to be written to is selected via the WRADD address bus and a rising edge of
WCLKwhile WADENis HIGH. Arisingedge ofWCLKinconjunctionwithFSTRandWRADDwillalso
selectthe flagquadranttobe placedonthePAFnbus duringdirectflagoperation. Duringpolledflag
operationthePAFnbusiscycledwithrespecttoWCLKandtheFSYNCsignalissynchronizedtoWCLK.
The PAFn, PAF and FF outputs are allsynchronizedtoWCLK. Duringdevice expansionthe FXOand
FXIsignals are basedonWCLK. The WCLKmustbe continuous andfree-running.
WEN
(T6)
WriteEnable
HSTL-LVTTL The WEN input enables write operations to a selected Queue based on a rising edge of WCLK. A
INPUT
queue tobe writtentocanbe selectedvia WCLK, WADENandthe WRADDaddress bus regardless
ofthestateofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLK
cycleafterqueueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFn
bus (in polled mode) or to select the PAFn quadrant , (in direct mode).
WRADD
WriteAddress HSTL-LVTTL For the 32Q device the WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The
[7:0]
Bus
INPUT
firstfunctionofWRADDistoselectaQueuetobewrittento. The leastsignificant5bits ofthe bus,
WRADD[4:0]areusedtoaddress1of32possiblequeueswithinamulti-queuedevice.Themostsignificant
3bits,WRADD[7:5]areusedtoselect1of8possiblemulti-queuedevices thatmaybeconnectedin
expansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent
ontheWRADDbuswillbeselectedonarisingedgeofWCLKprovidedthatWADENisHIGH,(note,that
data presentonthe Dinbus canbe writtenintothe previouslyselectedqueue onthis WCLKedge and
on the nextrisingWCLKalso, providingthatWEN is LOW). TwoWCLKrisingedges afterwrite queue
select,datacanbewrittenintothenewlyselectedqueue.
ThesecondfunctionoftheWRADDbusistoselectthequadrantofqueuestobeloadedontothePAFn
busduringstrobedflagmode.Theleastsignificant2bits,WRADD[1:0]areusedtoselectthequadrant
ofa device tobe placedonthePAFnbus. The mostsignificant3bits, WRADD[7:5]are againusedto
select1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansionmode.Addressbits
WRADD[4:2]aredon’tcareduringquadrantselection.Thequadrantaddress presentontheWRADD
bus will be selected on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be
writtenintothepreviouslyselectedqueueonthisWCLKedge).PleaserefertoTable1fordetailsonthe
WRADDbus.
(WRADD7-T1
WRADD6-R1
WRADD5-R2
WRADD4-P1
WRADD3-P2
WRADD2-P3
WRADD1-N1
WRADD0-N2)
VCC
(See pg. 13)
+2.5VSupply
Power
Power
These are VCC power supply pins and must all be connected to a +2.5V supply rail.
VDDQ
(See pg. 13)
O/PRailVoltage
Thesepinsmustbetiedtothedesiredoutputrailvoltage.ForLVTTLI/Othesepinsmustbeconnected
to+2.5V,forHSTLthesepinsmustbeconnectedto+1.5VandforeHSTLthesepinsmustbeconnected
to+1.8V.
GND
GroundPin
Ground
These are Ground pins and must all be connected to the GND supply rail.
(See pg. 13)
Vref
(K3)
Reference
Voltage
HSTL
INPUT
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable
"RecommendedDCOperatingConditions". The inputprovides the reference levelforHSTL/eHSTL
inputs. ForLVTTLI/Omode this inputshouldbe tiedtoGND.
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 59-62 and Figures 36-38.
12
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN NUMBER TABLE
Symbol
Name
I/OTYPE
Pin Number
D[35:0]
Din
DataInputBus HSTL-LVTTL D35-J3, D(34-32)-H(3-1), D(31-29)-G(3-1), D(28-26)-F(3-1), D(25-23)-E(3-1), D(22-20)-D(3-1),
INPUT
D(19-17)-C(3-1), D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5, D6-B5,
D5-C5, D4-A6, D3-B6, D2-C6, D1-A7, D0-B7
Q[35:0]
Qout
DataOutputBus HSTL-LVTTL Q(35,34)-J(15,16), Q(33-31)-H(14-16), Q(30-28)-G(14-16), Q(27-25)-F(14-16), Q(24-22)-E(14-16),
OUTPUT Q(21,20)-D(15,16), Q19-B16, Q(18,17)-C(16,15), Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14,
Q11-B14, Q10-C14, Q9-A13, Q8-B13, Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11,
Q(1,0)-C(11,10)
VCC
+2.5VSupply
O/PRailVoltage
GroundPin
Power
Power
Ground
D(7-10),E(6,7,10,11),F(5,12),G(4,5,12,13),H(4,13),J(4,13),K(4,5,12,13),L(5,12),M(6,7,10,11),N(7-10)
D(4-6,11-13), E(4,5,12,13), F(4,13), L(4,13), M(4,5,12,13), N(4-6,11-13)
VDDQ
GND
E(8-9), F(6-11), G(6-11), H(5-12), J(1,5-12), K(2,6-11,14), L(6-11), M(8-9)
13
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
–0.5to+3.6(2)
Unit
Symbol
Parameter(1)
Conditions
Max.
Unit
VTERM
TerminalVoltage
with respect to GND
V
(2,3)
CIN
Input
Capacitance
VIN = 0V
10(3)
pF
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
(1,2)
COUT
Output
Capacitance
VOUT = 0V
15
pF
NOTES:
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
RECOMMENDEDDCOPERATINGCONDITIONS
Symbol
VCC
Parameter
Min.
2.375
0
Typ.
2.5
0
Max.
2.625
0
Unit
V
SupplyVoltage
SupplyVoltage
GND
V
VIH
InputHighVoltage
LVTTL
eHSTL
HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
3.45
—
—
V
V
V
VIL
InputLowVoltage
LVTTL
eHSTL
HSTL
-0.3
—
—
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
VREF
(HSTL only)
VoltageReferenceInput eHSTL
HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
TA
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
0
—
—
70
85
°C
°C
TA
-40
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
14
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
ILI
Parameter
Min.
–10
–10
Max.
10
Unit
µA
µA
V
V
V
InputLeakageCurrent
OutputLeakageCurrent
ILO
10
(3)
VOH
OutputLogic“1”Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
VDDQ-0.4
VDDQ-0.4
VDDQ-0.4
—
—
—
IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
VOL
OutputLogic“0”Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
—
—
—
0.4V
0.4V
0.4V
V
V
V
IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
ICC1(1,2)
ICC2(1)
ICC3(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
80
150
150
mA
mA
mA
Standby VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
25
100
100
mA
mA
mA
Standby VCC Current in Power Down mode(VCC = 2.5V) I/O = LVTTL
—
—
—
—
50
50
mA
mA
mA
I/O = HSTL
I/O = eHSTL
(1,2)
IDDQ
ActiveVDDQ Current (VDDQ =2.5VLVTTL)
(VDDQ = 1.5V HSTL)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
10
10
10
mA
mA
mA
(VDDQ = 1.8V eHSTL)
NOTES:
1. Both WCLK and RCLK toggling at 20MHz.
2. Data inputs toggling at 10MHz.
3. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)].
4. Outputs are not 3.3V tolerant.
5. The following inputs should be pulled to GND: WRADD, RDADD, WADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.
The following inputs should be pulled to VCC: WEN, REN, SENI, PRS, MRS, TDI, TMS and TRST.
All other inputs are don't care and should be at a known state.
15
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
HSTL
AC TEST LOADS
1.5V AC TEST CONDITIONS
V
DDQ/2
InputPulseLevels
0.25to1.25V
0.4ns
InputRise/FallTimes
50Ω
InputTimingReferenceLevels
OutputReferenceLevels
0.75
Z0 = 50Ω
VDDQ/2
I/O
5998 drw04
NOTE:
1. VDDQ = 1.5V±.
Figure 2a. AC Test Load
EXTENDEDHSTL
1.8V AC TEST CONDITIONS
6
5
4
3
2
1
InputPulseLevels
0.4 to 1.4V
0.4ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.9
VDDQ/2
NOTE:
1. VDDQ = 1.8V±.
20 30 50 80 100
200
Capacitance (pF)
5998 drw04a
2.5VLVTTL
2.5V AC TEST CONDITIONS
Figure 2b. Lumped Capacitive Load, Typical Derating
InputPulseLevels
GND to 2.5V
1ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
VCC/2
VDDQ/2
NOTE:
1. For LVTTL VCC = VDDQ.
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
Output
Normally
LOW
V
CC/2
OL
V
CC/2
100mV
100mV
100mV
V
V
OH
Output
Normally
HIGH
100mV
VCC/2
VCC/2
5998 drw04b
NOTE:
1. REN is HIGH.
16
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72T51546L5
IDT72T51556L5
IDT72T51546L6
IDT72T51556L6
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency (WCLK & RCLK)
DataAccessTime
—
0.6
5
200
3.6
—
—
—
—
—
—
—
—
—
—
—
—
3.6
3.6
3.6
10
—
0.6
6
166
3.7
—
—
—
—
—
—
—
—
—
—
—
—
3.7
3.7
3.7
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock High Time
2.3
2.3
1.5
0.5
1.5
0.5
30
2.7
2.7
2.0
0.5
2.0
0.5
30
Clock Low Time
DataSetupTime
tDH
DataHoldTime
tENS
tENH
tRS
EnableSetupTime
EnableHoldTime
ResetPulseWidth
tRSS
tRSR
tPRSS
tPRSH
ResetSetupTime
15
15
ResetRecoveryTime
10
10
PartialResetSetup
1.5
0.5
0.6
0.6
0.6
—
100
45
2.0
0.5
0.6
0.6
0.6
—
100
45
PartialResetHold
(2)
tOLZ(OE-Qn)
OutputEnabletoOutputinLow-Impedance
OutputEnabletoOutputinHigh-Impedance
OutputEnabletoDataOutputValid
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
(2)
tOHZ
tOE
fC
tSCLK
tSCKH
tSCKL
tSDS
—
—
—
—
—
—
—
20
—
—
—
—
—
—
—
20
Serial Clock High
Serial Clock Low
45
45
SerialDataInSetup
20
20
tSDH
tSENS
tSENH
tSDO
tSENO
tSDOP
tSENOP
tPCWQ
tPCRQ
tAS
Serial Data In Hold
1.2
20
1.2
20
SerialEnableSetup
SerialEnableHold
1.2
—
—
1.5
1.5
20
1.2
—
—
1.5
1.5
20
SCLK to Serial Data Out
SCLK to Serial Enable Out
SerialDataOutPropagationDelay
SerialEnablePropagationDelay
ProgrammingCompletetoWriteQueueSelection
ProgrammingCompletetoReadQueueSelection
AddressSetup
20
20
3.7
3.7
—
—
—
—
3.6
3.6
—
—
—
—
3.6
3.6
3.6
3.6
3.7
3.7
—
—
—
3.7
3.7
—
—
—
—
3.7
3.7
3.7
3.7
20
20
1.5
1.0
—
—
1.5
0.5
1.5
1.0
0.6
0.6
0.6
0.6
2.5
1.5
—
—
2.0
0.5
2.0
0.5
0.6
0.6
0.6
0.6
tAH
Address Hold
tWFF
tROV
tSTS
Write Clock to Full Flag
ReadClocktoOutputValid
PAE/PAF Strobe Setup
PAE/PAF Strobe Hold
QueueSetup
tSTH
tQS
tQH
QueueHold
tWAF
tRAE
tPAF
tPAE
WCLK to PAF flag
RCLK to PAE flag
Write ClocktoSynchronous Almost-FullFlagBus
Read Clock to Synchronous Almost-Empty Flag Bus
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
17
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(CONTINUED)
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72T51546L5
IDT72T51556L5
IDT72T51546L6
IDT72T51556L6
Symbol
Parameter
RCLK to Echo RCLK Output
Min.
Max.
Min.
Max.
Unit
tERCLK
tCLKEN
—
—
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
4
4.0
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
—
—
—
—
—
—
—
—
—
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
4.5
6
4.2
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RCLK to Echo REN Output
(2)
tPAELZ
RCLK to PAE Flag Bus to Low-Impedance
RCLK to PAE Flag Bus to High-Impedance
WCLK to PAF Flag Bus to Low-Impedance
WCLK to PAF Flag Bus to High-Impedance
WCLKtoFullFlagtoHigh-Impedance
(2)
tPAEHZ
(2)
tPAFLZ
(2)
tPAFHZ
(2)
tFFHZ
(2)
tFFLZ
WCLKtoFullFlagtoLow-Impedance
(2)
tOVLZ
RCLKtoOutputValidFlagtoLow-Impedance
RCLKtoOutputValidFlagtoHigh-Impedance
WCLK to PAF Bus Sync to Output
WCLK to PAF Bus Expansion to Output
RCLK to PAE Bus Sync to Output
(2)
tOVHZ
tFSYNC
tFXO
tESYNC
tEXO
RCLK to PAE Bus Expansion to Output
RCLK to Packet Ready Flag
tPR
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tSKEW5
tXIS
SKEW time between RCLK and WCLK for FF and OV
SKEW time between RCLK and WCLK for PAF and PAE
SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7]
SKEW time between RCLK and WCLK for PR and OV
SKEW time between RCLK and WCLK for OV when in Packet Mode
ExpansionInputSetup
5
5
6
5
6
8
10
1.0
0.5
1.0
0.5
tXIH
ExpansionInputHold
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
18
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
completedthedevicewillindicatethisviatheSENO(serialoutputenable)going
active,LOW.Upondetectionofcompletionofprogramming,theusershould
ceaseallprogrammingandtakeSENIinactive,HIGH.Note,SENOfollowsSENI
onceprogrammingofadeviceiscomplete.Therefore,SENOwillgoLOWafter
programmingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENO
willalsogoHIGH.TheoperationoftheSOoutputissimilar,whenprogramming
ofagivendeviceiscomplete,theSOoutputwillfollowtheSIinput.
Ifdevicesarebeingusedinexpansionmodetheserialportsofdevicesshould
becascaded.Theusercanloadalldevicesviatheserialinputportcontrolpins,
SI & SENI, of the first device in the chain. Again, the user may utilize the ‘C’
programtogeneratetheserialbitstream,theprogrampromptingtheuserfor
the numberofdevices tobe programmed. The SENO andSO(serialout)of
thefirstdeviceshouldbeconnectedtotheSENI andSIinputs ofthesecond
devicerespectivelyandsoon,withtheSENO&SOoutputsconnectingtothe
SENI&SIinputsofalldevicesthroughthechain.Alldevicesinthechainshould
beconnectedtoacommonSCLK.Theserialoutputportofthefinaldeviceshould
be monitored by the user. When SENO of the final device goes LOW, this
indicates thatserialprogrammingofalldevices has beensuccessfullycom-
pleted.Upondetectionofcompletionofprogramming,theusershouldceaseall
programmingandtakeSENIofthefirstdeviceinthechaininactive,HIGH.
Asmentioned,thefirstdeviceinthechainhasitsserialinputportcontrolled
bytheuser,thisisthefirstdevicetohaveitsinternalregistersseriallyloaded
bytheserialbitstream.Whenprogrammingofthisdeviceiscompleteitwilltake
its SENOoutputLOWandbypasstheserialdataloadedontheSIinputtoits
SOoutput.Theserialinputoftheseconddeviceinthechainisnowloadedwith
thedatafromtheSOofthefirstdevice,whiletheseconddevicehasitsSENI
input LOW. This process continues through the chain until all devices are
programmedandtheSENO ofthefinaldevicegoesLOW.
FUNCTIONALDESCRIPTION
MASTERRESET
AMasterResetisperformedbytogglingtheMRSinputfromHIGHtoLOW
toHIGH.Duringamasterresetallinternalmulti-queuedevicesetupandcontrol
registersareinitializedandrequireprogrammingeitherseriallybytheuservia
theserialport,orusingthedefaultsettings.Duringamasterresetthestateof
thefollowinginputsdeterminethefunctionalityofthepart,thesepinsshouldbe
held HIGH or LOW.
PKT–PacketMode
FM – Flag bus Mode
IW,OW,BM–BusMatchingoptions
MAST – Master Device
ID0, 1, 2 – Device ID
DFM–Programmingmode,serialordefault
DF – Offset value for PAE and PAF
Onceamasterresethastakenplace,thedevicemustbeprogrammedeither
seriallyorviathedefaultmethodbeforeanyread/writeoperationscanbegin.
See Figure 5, Master Reset for relevant timing.
PARTIALRESET
APartialResetisameansbywhichtheusercanresetboththereadandwrite
pointers of a single queue that has been setup within a multi-queue device.
Beforeapartialresetcantakeplaceonaqueue,therespectivequeuemustbe
selectedonboththereadportandwriteportaminimumof2RCLKand2WCLK
cyclesbeforethePRSgoesLOW.Thepartialresetisthenperformedbytoggling
thePRSinputfromHIGHtoLOWtoHIGH,maintainingtheLOWstateforatleast
oneWCLKandoneRCLKcycle.Onceapartialresethastakenplaceaminimum
of3WCLKand3RCLKcyclesmustoccurbeforeenabledwritesorreadscan
occur.
Once all serial programming has been successfully completed, normal
operations,(queueselectionsonthereadandwriteports)maybegin.When
connectedinexpansionmode,theIDT72T51546/72T51556devicesrequire
atotalnumberofseriallyloadedbitsperdevicetocompleteserialprogramming,
(SCLKcycleswithSENIenabled),calculatedby:n[19+(Qx72)]whereQisthe
numberofqueues the userwishes tosetupwithinthe device, where nis the
numberofdevices inthechain.
APartialResetonlyresets thereadandwritepointers ofagivenqueue,a
partialresetwillnoteffecttheoverallconfigurationandsetupofthemulti-queue
deviceandits queues.
See Figure 6, PartialReset for relevant timing.
SeeFigure7,SerialPortConnectionandFigure8,SerialProgrammingfor
connectionandtiminginformation.
SERIAL PROGRAMMING
Themulti-queueflow-controldeviceisafullyprogrammabledevice,provid-
ingtheuserwithflexibilityinhowqueuesareconfiguredintermsofthenumber
of queues, depth of each queue and position of the PAF/PAE flags within
respectivequeues.Alluserprogrammingisdoneviatheserialportafteramaster
resethas takenplace. Internallythe multi-queue device has setupregisters
whichmustbeseriallyloaded,theseregisterscontainvaluesforeveryqueue
within the device, such as the depth and PAE/PAF offset values. The
IDT72T51546/72T51556 devices are capable of up to 32 queues and
thereforecontain32setsofregistersforthesetupofeachqueue.
DuringaMasterResetiftheDFM(DefaultMode)inputisLOW,thenthedevice
willrequire serialprogrammingbythe user. Itis recommendedthatthe user
utilizea‘C’programprovidedbyIDT,thisprogramwillprompttheuserforall
informationregardingthemulti-queuesetup.Theprogramwillthengenerate
aserialbitstreamwhichshouldbeseriallyloadedintothedeviceviatheserial
port. For the IDT72T51546/72T51556 devices the serial programming re-
quiresatotalnumberofseriallyloadedbitsperdevice,(SCLKcycleswithSENI
enabled),calculatedby:19+(Qx72)whereQisthenumberofqueuestheuser
wishestosetupwithinthedevice.
DEFAULTPROGRAMMING
Duringa MasterResetifthe DFM(DefaultMode)inputis HIGHthe multi-
queuedevicewillbeconfiguredfordefaultprogramming,(serialprogramming
is not permitted). Default programming provides the user with a simpler,
howeverlimitedmeansbywhichtosetupthemulti-queueflow-controldevice,
rather than using the serial programming method. The default mode will
configure a multi-queue device such that the maximum number of queues
possiblearesetup,withallofthepartsavailablememoryblocksbeingallocated
equallybetweenthequeues.ThevaluesofthePAE/PAFoffsetsisdetermined
bythe state ofthe DF(default)pinduringa masterreset.
For the IDT72T51546/72T51556 devices the default mode will setup 32
queues,eachqueuebeing1024x36and2048x36deeprespectively.Forboth
devicesthevalueofthePAE/PAFoffsetsisdeterminedatmasterresetbythe
stateoftheDFinput.IfDFisLOWthenboththe PAE&PAF offsetwillbe8,if
HIGH then the value is 128.
WhenconfiguringtheIDT72T51546/72T51556devicesindefaultmodethe
usersimplyhastoapplyWCLKcyclesafteramasterreset,untilSENO goes
LOW,thissignalsthatdefaultprogrammingiscomplete.Theseclockcyclesare
requiredforthedevicetoloaditsinternalsetupregisters.Whenasinglemulti-
queuedeviceisused,thecompletionofdeviceprogrammingissignaledbythe
Once the master reset is complete and MRS is HIGH, the device can be
seriallyloaded.DatapresentontheSI(serialin),inputisloadedintotheserial
port on a rising edge of SCLK (serial clock), provided that SENI (serial in
enable),isLOW.Onceserialprogrammingofthedevicehasbeensuccessfully
19
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SENO outputofadevicegoingfromHIGHtoLOW.Note,thatSENImustbe selection. The queue selectionrequires 1WCLKcycle. Allsubsequentdata
heldLOWwhenadeviceissetupfordefaultprogrammingmode.
writeswillbetothisqueueuntilanotherqueueisselected.
Whenmulti-queuedevicesareconnectedinexpansionmode,theSENIof
Standardmodeoperationisdefinedasindividualwordswillbewrittentothe
the first device in a chain can be held LOW. The SENO of a device should deviceasopposedtoPacketModewherecompletepacketsmaybewritten.
connecttotheSENIofthenextdeviceinthechain.TheSENOofthefinaldevice Thewriteportisdesignedsuchthat100%busutilizationcanbeobtained.This
isusedtoindicatethatdefaultprogrammingofalldevicesiscomplete.Whenthe means that data can be written into the device on every WCLK rising edge
finalSENOgoesLOWnormaloperationsmaybegin.Again,alldeviceswillbe includingthe cycle thata newqueue is beingaddressed.
programmedwiththeirmaximumnumberofqueuesandthememorydivided
equally between them. Please refer to Figure 9, DefaultProgramming.
Changingqueues requires aminimumof3WCLKcycles onthewriteport
(seeFigure10,WriteQueueSelect,WriteOperationandFullflagOperation).
WADENgoeshighsignalingachangeofqueue(clockcycle“A”).Theaddress
onWRADDatthattimedeterminesthenextqueue.Datapresentedduringthat
cycle (“A”) and the next cycle (“B” and “C”), will be written to the active (old)
READING AND WRITING TO THE IDT MULTI-QUEUE
FLOW-CONTROL DEVICE
The IDT72T51546/72T51556 multi-queue flow-control devices can be queue,providedWENisactiveLOW.IfWENisHIGH(inactive)forthese3clock
configuredintwodistinctmodes,namelyStandardModeandPacketMode. cycles,datawillnotbewrittenintothepreviousqueue.Thewriteportdiscrete
fullflagwillupdatetoshowthefullstatusofthenewlyselectedqueue(QX)atthis
STANDARD MODE OPERATION (PKT = LOW ON MASTER RESET)
lastcycle’srisingedge(“C”).Datapresentonthedatainputbus(Din),canbe
writtenintothenewlyselectedqueue(QX)ontherisingedgeofWCLKonthe
thirdcycle(“D”)followingachangeofqueue,providedWENis LOWandthe
newqueueisnotfull.Ifthenewlyselectedqueueisfullatthepointofitsselection,
WRITE QUEUE SELECTION AND WRITE OPERATION
(STANDARDMODE)
The IDT72T51546/72T51556 multi-queue flow-control devices can be any writes to that queue will be prevented. Data cannot be written into a full
configureduptoamaximumof32queues intowhichdatacanbewrittenvia queue.
acommonwriteportusingthedatainputs(Din),writeclock(WCLK)andwrite
Refer to Figure 10, Write Queue Select, Write Operation and Full flag
enable(WEN).Thequeuetobewrittenisselectedbytheaddresspresenton Operation, Figure 11, Write Operations &FirstWordFallThroughfortiming
the write address bus (WRADD) during a rising edge on WCLK while write diagrams and Figure 12, Full Flag Timing in Expansion Mode for timing
addressenable(WADEN)isHIGH.ThestateofWENdoesnotimpactthequeue diagrams.
TABLE 1 — WRITE ADDRESS BUS, WRADD[7:0]
Operation WCLK WADEN FSTR
WRADD[7:0]
7 6 5 4 3 2
1 0
Write
Queue
Select
1
0
Device Select
(Compared to
ID0,1,2)
Write Queue Address
(5 bits = 32 Queues)
7 6 5 4 3 2
1 0
PAFn
Quadrant
Select
0
1
Device Select
(Compared to
ID0,1,2)
X
X
X
Quadrant
Address
Quadrant
Address
Queue Status on PAFn Bus
00
Q0 : Q7 → PAF0 : PAF7
Q8 : Q15 → PAF0 : PAF7
Q16 : Q23 → PAF0 : PAF7
Q24 : Q31 → PAF0 : PAF7
01
10
11
5998 drw05
20
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
READ QUEUE SELECTION AND READ OPERATION
(STANDARDMODE)
cycle’srisingedge(“F”),thereadportdiscreteemptyflagwillupdatetoshow
theemptystatusofthenewlyselectedqueue(QF).Theinternalpipelineisalso
The IDT72T51546/72T51556 multi-queue flow-control devices can be loadedatthis time(“F”)withthelastwordfromtheprevious (old)queue(QF)
configureduptoamaximumof32queueswhichdatacanbereadviaacommon aswellasthenextwordfromthenewqueue(QF).Bothofthesewordswillfall
readportusingthe data outputs (Qout), readclock(RCLK)andreadenable through to the output register (provided the OE is asserted) consecutively
(REN). An output enable, OE control pin is also provided to allow High- (cycles “F” and “G” respectively) following the selection of the new queue
ImpedanceselectionoftheQoutdataoutputs.Themulti-queuedevicereadport regardlessofthestateofREN,unlessthenewqueue(Q )isempty.Ifthenewly
F
operates ina mode similarto“FirstWordFallThrough”ona SuperSyncIDT selectedqueue is empty, anyreads fromthatqueue willbe prevented. Data
FIFO,butwiththeaddedfeatureofdataoutputpipelining(seeFigure11,Write cannotbereadfromanemptyqueue.Thelastwordinthedataoutputregister
Operations & First Word Fall Through). The queue to be read is selected by (fromthepreviousqueue),willremainonthedatabus,buttheoutputvalidflag,
theaddresspresentedonthereadaddressbus(RDADD)duringarisingedge OVwillgoHIGH,toindicatethatthedatapresentisnolongervalid.Thispipelining
onRCLKwhilereadaddressenable(RADEN)isHIGH.ThestateofRENdoes effectprovidestheuserwith100%busutilization,andbringsaboutthepossibility
notimpactthequeueselection.Thequeueselectionrequires1RCLKcycles. thata“NULL”queuemayberequiredwithinamulti-queuedevice.Nullqueue
Allsubsequentdatareadswillbefromthisqueueuntilanotherqueueisselected. operationisdiscussedinthenextsection.RememberthatOEallowstheuser
Standardmodeoperationisdefinedasindividualwordswillbereadfromthe toplacethedataoutputbus(Qout)intoHigh-Impedanceandthedatacanbe
deviceasopposedtoPacketModewherecompletepacketsmayberead.The readintotheoutputregisterregardless ofOE.
readportisdesignedsuchthat100%busutilizationcanbeobtained.Thismeans
RefertoTable2,forReadAddressBusarrangement.Also,refertoFigures
that data can be read out of the device on every RCLK rising edge including 13,15,and16forreadqueueselectionandreadportoperationtimingdiagrams.
the cycle that a new queue is being addressed.
ChangingqueuesrequiresaminimumofthreeRCLKcyclesonthereadport PACKET MODE OPERATION (PKT = HIGH on Master Reset)
(see Figure 13, Read Queue Select, Read Operation). RADEN goes high
The Packet mode operation provides the capability where, user defined
signalingachangeofqueue(clockcycle“D”).TheaddressonRDADDatthat packetsorframescanbewrittentothedeviceasopposedtoStandardmode
timedeterminesthenextqueue.Datapresentedduringthatcycle(“D”)willbe whereindividualwordsarewritten.Forclarification,inPacketMode,apacket
readat“D”(+tA),andthenextcycle(“E”),cancontinuetobereadfromtheactive canbewrittentothedevicewiththestartinglocationdesignatedasTransmitStart
(old)queue (QP), providedREN is active LOW. IfREN is HIGH(inactive)for ofPacket(TSOP)andtheendinglocationdesignatedasTransmitEndofPacket
thesetwoclockcycles,datawillnotbereadfromthepreviousqueue.Thenext (TEOP). Inconjunction, a packetreadfromthe device willbe designatedas
TABLE 2 — READ ADDRESS BUS, RDADD[7:0]
Operation
RCLK RADEN ESTR
Null-Q
0
RDADD[7:0]
4 3 2
7
6
5
1 0
Read Queue
Select
1
0
1
0
1
0
Device Select
(Compared to
ID0,1,2)
Read Queue Address
(5 bits = 32 Queues)
7
6
5
4 3 2
1 0
Quadrant
Address
PAEn/PRn
Quadrant
Select
0
1
Device Select
(Compared to
ID0,1,2)
X
X
X
7
X
6
X
5
X
4 3 2
1 0
Null Queue
Select
X
X
X
X
X
Quadrant
Address
Queue Status on PAEn/PRn Bus
00
Q0 : Q7 → PAE0 : PAE7
Q8 : Q15 → PAE0 : PAE7
Q16 : Q23 → PAE0 : PAE7
Q24 : Q31 → PAE0 : PAE7
01
10
11
5998 drw06
21
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Receive StartofPacket(RSOP)anda Receive EndofPacket(REOP). The requestismade(“C”or“J”).IfRENisHIGH(inactive)forthesetwoclockcycles,
minimumsizeforapacketisfourwords(SOP,twowordsofdataandEOP).The datawillnotbereadfromtheprevious queue(QA).Inapplications wherethe
almostemptyflagbusbecomesthe“PacketReady”PRflagbuswhenthedevice multi-queueflow-controldeviceisconnectedtoasharedbus,anoutputenable,
isconfiguredforpacketmode.ValidpacketsareindicatedwhenbothPRand OEcontrolpinisalsoprovidedtoallowHigh-Impedanceselectionofthedata
OV areasserted.
outputs(Qout).WithreferencetoFigure18whenchangingqueues,apacket
marker(SOPorEOP)shouldnotbereadoncycle(“E”or“L”).ReadingaSOP
WRITEQUEUESELECTIONANDWRITEOPERATION(PACKETMODE) orEOPshouldnotoccurduringthe cycles requiredfora queue change. Itis
Itisrequiredthatafullpacketbewrittentoaqueuebeforemovingtoadifferent alsorecommendedthataqueuechangeshouldnotoccuroncethereadingof
queue.Thedevicerequiresthreecyclestochangequeues.Packetmode,has the packethas commenced, The EOPmarkerofthe packetpriortoa queue
2restrictions:<1>Anextraword(orfillerword)is requiredtobewrittenafter changeshouldbereadonorbeforethequeuechange.IftheEOPwordisread
eachpacketonthecyclefollowingthequeuechangetoensuretheRSOPin beforeaqueuechange,RENcanbepulledhightodisablefurtherreads.When
theoldqueueisnotreadoutonaqueuechangebecauseofthefirstwordfall thequeuechangeisinitiated,thefillerwordwrittenintothecurrentqueueafter
through.<2>NoSOP/EOPis allowedtoread/writtenatcycle(“D”or“K”)the theEOPwordwillfallthroughfollowedbyandthefirstwordfromthenewqueue.
secondcycleafteraqueuechange.Inthismode,thewriteportmaynotobtain
100%busutilization.
Refer to Figure 18, Reading in Packet Mode during a Queue Change as
wellasFigures13,15,and16fortimingdiagramsandTable2,forReadAddress
Changingqueues requires aminimumof3WCLKcycles onthewriteport busarrangement.
(see Figure 17, Writing in Packet Mode during a Queue Change). WADEN
Note,thealmostemptyflagbusbecomesthe“PacketReady”flagbuswhen
goes high signaling a change of queue (clock cycle “B” or “I”). The address the device is configuredforpacketreadymode..
on WRADD at the rising edge of WCLK determines the next queue. Data
presented on Din during that cycle (“B” or “I”) and the next cycle (“C” or “J”) PACKETREADYFLAG
can continue to be written to the active (old) queue (QA or QB respectively),
The36-bitmulti-queueflow-controldeviceprovidestheuserwithaPacket
providedWENisLOW(active).IfWENisHIGH(inactive)forthesetwoclock Readyfeature. Duringa MasterResetthe logic“1”(HIGH)onthe PKTinput
cycles (H), datawillnotbewrittenintotheprevious queue(QA).Thesecond signal (packet mode select), configures the device in packet mode. The PR
cyclefollowingarequestforqueuechange(“D”or“K”)willrequirea“filler”word discreteflag,providesapacketreadystatusoftheactivequeueselectedonthe
tobewrittentothedevice.ThiscanbedonebyclockingtheTEOPtwiceorby read port. A packet ready status is individually maintained on all queues;
writinga“filler”word.Inpacketmode,themulti-queueis designedunderthe howeveronlythequeueselectedonthereadporthasitspacketreadystatus
2restrictionslistedpreviously.Note,anerroneousPacketReadyflagmayoccur indicatedonthePRoutputflag.Apacketisavailableontheoutputforreading
iftheEOPorSOPmarkershowsupatthesecondcycleafteraqueuechange. whenbothPRandOVareassertedLOW.Iflessthanafullpacketisavailable,
TopreventanerroneousPacketReadyflagfromoccurringafillerwordshould thePRflagwillbeHIGH(packetnotready).Inpacketmode,nowordscanbe
bewrittenintotheoldqueueatthelastclockcycleofwriting.Itisimportanttoknow readfroma queue untila complete packethas beenwrittenintothatqueue,
thatnoSOPorEOPmaybewrittenintothedeviceduringthiscycle(“D”or“K”). regardless ofREN.
Thewriteportdiscretefullflagwillupdatetoshowthefullstatus ofthenewly
WhenpacketmodeisselectedtheProgrammableAlmostEmptybus,PAEn,
selected queue (QB) at this last cycle’s rising edge (“D” or “K”). Data values becomes thePacketReadybus,PRn.WhenconfiguredinDirectBus (FM=
presentedonthedatainputbus (Din),canbewrittenintothenewlyselected LOW during a master reset), the PRn bus provides packet ready status in 8
queue(QX)ontherisingedgeofWCLKonthethirdcycle(“E”)followingarequest queue increments. The PRn bus supports either Polled or Direct modes of
forchangeofqueue,providedWENisLOW(active)andthenewqueueisnot operation. The PRnmode ofoperationis configuredthroughthe FlagMode
full. If a selected queue is full (FF is LOW), then writes to that queue will be (FM) bit during a Master Reset.
prevented.Note,datacannotbewrittenintoafullqueue.
Whenthemulti-queueisconfiguredforpacketmodeoperation,thedevice
Refer to Figure 17, Writing in Packet Mode during a Queue Change and mustalsobeconfiguredfor36bitwritedatabusand36bitreaddatabus.The
Figure19,DataInput(Transit)PacketModeofOperationfortimingdiagrams. twomostsignificantbitsofthe36-bitdatabusareusedas“packetmarkers”.On
thewriteportthesearebitsD34(TransmitStartofPacket,)D35(TransmitEnd
READ QUEUE SELECTION AND READ OPERATION (PACKET MODE) ofPacket)andonthereadportQ34,Q35.Allfourbitsaremonitoredbythepacket
InpacketMode itis requiredthata fullpacketis readfroma queue before controllogicasdataiswrittenintoandreadoutfromthequeues.Thepacket
movingtoadifferentqueue.Thedevicerequiresthreecyclestochangequeues. readystatusforindividualqueuesisthendeterminedbythepacketreadylogic.
InPacketMode,thereare2restrictions<1>Anextraword(orfillerword)should
OnthewriteportD34is usedto“mark”thefirstwordbeingwrittenintothe
havebeeninsertedintothedatastreamaftereachpackettoinsuretheRSOP selectedqueueasthe“TransmitStartofPacket”,TSOP.Tofurtherclarify,when
inthe oldqueue is notreadoutona queue change because ofthe firstword theuserrequiresawordbeingwrittentobemarkedasthestartofapacket,the
fallthroughandthiswordshouldbediscarded.<2>NoEOP/SOPisallowed TSOPinput(D34)mustbeHIGHforthesameWCLKrisingedgeastheword
toberead/writtenatcycle(“D”or“K”)thesecondcycleafteraqueuechange). thatiswritten.TheTSOPmarkerisstoredinthequeuealongwiththedataitwas
Inthis mode,thereadportmaynotobtain100%bus utilization.
written in until the word is read out of the queue via the read port.
Changingqueuesrequiresaminimumof3RCLKcyclesonthereadport(see
OnthewriteportD35isusedto“mark”thelastwordofthepacketcurrently
Figure18,ReadinginPacketModeduringaQueueChange).RADENgoes beingwrittenintotheselectedqueueasthe“TransmitEndofPacket”TEOP.
high signaling a change of queue (clock cycle “B” or “I”). The address on Whentheuserrequiresawordbeingwrittentobemarkedastheendofapacket,
RDADDattherisingedgeofRCLKdeterminesthequeue.AsillustratedinFigure theTEOPinputmustbeHIGHforthesameWCLKrisingedgeasthewordthat
18 during cycle (“B” or “I”), and the next cycle (“C” or “J”) data can continue iswrittenin.TheTEOPmarkerisstoredinthequeuealongwiththedataitwas
tobe readfromthe active (old)queue (QA orQBrespectively), providedboth written in until the word is read out of the queue via the read port.
RENandOEareLOW(active)simultaneouslywithchangingqueues.REOP
Thepacketreadylogicmonitorsallstartandendofpacketmarkersbothas
for packet located in queue (QA) must be read on or before a queue change theyenterrespectivequeuesviathewriteportandastheyexitqueuesviathe
22
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 5 — PACKET MODE VALID BYTE
BYTE A
BYTE D
BYTE C
BYTE B
TMOD1 (D33)
RMOD1 (Q33)
TMOD2 (D32)
RMOD2 (Q32)
VALID BYTES
0
0
1
1
0
1
0
1
A, B, C, D
A
A, B
A, B, C
5998 drw07
NOTE:
Packet Mode is only available when the Input Port and Output Port are 36 bits wide.
of packet. This is a useful feature when due to latencies within the system,
monitoringtheREOPmarkeralonedoesnotprevent“overreading”ofthedata
fromthequeueselected.Forexample,anAEOPmarkerset4writesbeforethe
TEOPmarkerprovidesthedeviceconnectedtothereadportwithand“almost
endofpacket”indication4cyclesbeforetheendofpacket.
The AEOP can be set any number of words before the end of packet
determinedbyuserrequirementsorlatenciesinvolvedinthesystem.
See Figure 18, Reading in Packet Mode during a Queue Change, Figure
19, Data Input (Transmit) Packet Mode of Operation and Figure 20, Data
Output (Receive) Packet Mode of Operation.
readport.Themulti-queueinternallogicincrementsanddecrementsapacket
counter,whichisprovidedforeachqueue.Thefunctionalityofthepacketready
logicprovidesstatusastowhetheratleastonefullpacketofdataisavailable
withintheselectedqueue.Apartialpacketinaqueueisregardedasapacket
notreadyandPR (activeLOW)willbeHIGH.InPacketmode,nowords can
bereadfromaqueueuntilatleastonecompletepackethasbeenwritteninto
thequeue,regardless ofREN.Forexample,ifaTSOPhas beenwrittenand
somenumberofwordslateraTEOPiswrittenafullpacketofdataisdeemed
tobeavailable,andthePRflagandOVwillgoactiveLOW.Consequentlyifreads
beginfromaqueuethathasonlyonecompletepacketandtheRSOPisdetected
ontheoutputportasdataisbeingreadout,PRwillgoinactiveHIGH.OVwill
remainLOWindicatingthereisstillvaliddatabeingreadoutofthatqueueuntil
theREOPisread.Theusermayproceedwiththereadingoperationuntilthe
currentpackethasbeenreadoutandnofurthercompletepacketsareavailable.
Ifduringthattimeanothercompletepackethasbeenwrittenintothequeueand
thePRflagwillagaingoneactive,thenreadsfromthenewpacketmayfollow
afterthecurrentpackethasbeencompletelyreadout.
PACKETMODE–MODULOOPERATION
The internal packet ready control logic performs no operation on these
modulobits,theyareonlyinformationalbitsthatarepassedthroughwiththe
respectivedatabyte(s).
Whenutilizingthemulti-queueflow-controldeviceinpacketmode,theuser
mayalsowanttoconsidertheimplementationof“Modulo”operationor“valid
byte marking”. Modulo operation may be useful when the packets being
transferredthroughaqueueareinaspecificbytearrangementeventhough
thedatabuswidthis36bits.InModulooperationtheusercanconcatenatebytes
toformaspecificdatastringthroughthemulti-queuedevice.Apossiblescenario
is where a limited number of bytes are extracted from the packet for either
analysisorfilteredforsecurityprotection.Thiswillonlyoccurwhenthefirst36
bitwordofapacketiswritteninandthelast36bitwordofpacketiswrittenin.
Themodulooperationisameansbywhichtheusercanmarkandidentifyspecific
datawithintheQueue.
Onthewriteportdatainputbits,D32(transmitmodulobit2,TMOD2)andD33
(transmitmodulobit1,TMOD1)canbeusedasdatamarkers.Anexampleof
thiscouldbetouseD32andD33tocodewhichbytesofawordarepartofthe
packetthatis alsobeingmarkedas the “StartofMarker”or“EndofMarker”.
Conversely on the read port when reading out these marked words, data
outputs Q32(receive modulobit2, RMOD2)andQ33(receive modulobit1,
RMOD1)willpassonthebytevalidityinformationforthatword.RefertoTable
5foroneexampleofhowthemodulobitsmaybesetupandused.SeeFigure
19, Data Input (Transmit) Packet Mode of Operation and Figure 20, Data
Output (Receive) Packet Mode of Operation.
Thepacketcountersthereforelookforstartofpacketmarkersfollowedbyend
ofpacketmarkers andregarddatainbetweentheTSOPandTEOPas afull
packetofdata.Thepacketmonitoringhasnolimitationastohowmanypackets
arewrittenintoaqueue,theonlyconstraintisthedepthofthequeue.Note,there
isaminimumallowablepacketsizeoffourwords,inclusiveoftheTSOPmarker
andTEOPmarker.
The packet logic does expect a TSOP marker to be followed by a TEOP
marker.
If a second TSOP marker is written after a first, it is ignored and the logic
regardsdatabetweenthefirstTSOPandthefirstsubsequentTEOPasthefull
packet.ThesameistrueforTEOP;asecondconsecutiveTEOPmarkisignored.
On the read side the user should regard a packet as being between the first
RSOP and the first subsequent REOP and disregard consecutive RSOP
markersand/orREOPmarkers.ThisiswhyaTEOPmaybewrittentwice,using
the secondTEOPas the “filler”word.
Asanexample,theusermayalsowishtoimplementtheuseofan“Almost
EndofPacket”(AEOP)marker. Forexample, the AEOPcanbe assignedto
datainputbitD33.ThepurposeofthisAEOPmarkeristoprovideanindicator
thatthe endofpacketis a fixed(known)numberofreads awayfromthe end
23
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NULL QUEUE OPERATION (OF THE READ PORT)
Pipeliningofdatatotheoutputportenablesthedevicetoprovide100%bus busstrobe),toaddressthealmostfullflagbusduringdirectmodeofoperation.
utilizationinstandardmode.Datacanbereadoutofthemulti-queueflow-control RefertoTable1,forWriteAddressbusarrangement.Also,refertoFigure
Note:TheWRADDbusisalsousedinconjunctionwithFSTR(almostfullflag
deviceoneveryRCLKcycleregardlessofqueueswitchesorotheroperations. 12,FullFlagTimingExpansionMode,Figure14,OutputValidFlagTiming(In
Thedevicearchitectureissuchthatthepipelineisconstantlyfilledwiththenext ExpansionMode),andFigure35,Multi-QueueExpansionDiagram,fortiming
wordsinaselectedqueuetobereadout,againproviding100%busutilization. diagrams.
This type of architecture does assume that the user is constantly switching
queuessuchthatduringaqueueswitch,thelastdatawordrequiredfromthe BUS MATCHING OPERATION
previousqueuewillfallthroughthepipelinetotheoutput.
Note,thatifreadsceaseattheemptyboundaryofaqueue,thenthelastword Duringamasterresetofthemulti-queuethestateofthethreesetuppins,BM
willautomaticallyflowthroughthepipelinetotheoutput. (BusMatching),IW(InputWidth)andOW(OutputWidth)determinetheinputand
BusMatchingoperationbetweentheinputportandoutputportisavailable.
The NullQoperationis achievedbysettingthe NullQsignalHIGHduring outputportbuswidthsaspertheselectionsshowninTable3,“BusMatching
aqueueselect.NotethatthereadaddressbusRDADD[7:0]isadon'tcare.The Set-Up”.9bitbytes,18bitwordsand36bitlongwordscanbewrittenintoand
NullQueueisaseparatequeuewithinthedeviceandthusthemaximumnumber read from the Queues provided that at least one of the ports is setup for x36
ofqueuesandmemoryisalwaysavailableregardlessofwhetherornottheNull operation.Whenwritingtoorreadingfromthemulti-queueinabusmatching
queue is used. Also note that in expansion mode a user may want to use a mode, the device orders data in a “Little Endian” format. See Figure 4, Bus
dedicatednullqueueforeachdevice.Anullqueuecanbeselectedwhenno MatchingByteArrangementfordetails.
furtherreadsarerequiredfromapreviouslyselectedqueue.Changingtoanull
TheFullflagandAlmostFullflagoperationis always basedonwrites and
queuewillcontinuetopropagatedatainthepipelinetothepreviousqueue's readsofdatawidthsdeterminedbythewriteportwidth.Forexample,iftheinput
output.TheNullQcanremainselecteduntiladatabecomesavailableinanother portisx36andtheoutputportisx9,thenfourdatareadsfromafullqueuewill
queueforreading.TheNull-Qcanbeutilizedineitherstandardorpacketmode. berequiredtocausethefullflagtogoHIGH(queuenotfull).Conversely,the
Note:Iftheuserswitchesthereadporttothenullqueue,thisqueueisseen OutputValidflagandAlmostEmptyflagoperationsarealwaysbasedonwrites
asandtreatedasanemptyqueue,thereforeafterswitchingtothenullqueue andreadsofdatawidthsdeterminedbythereadport.Forexample,iftheinput
thelastwordfromthepreviousqueuewillremainintheoutputregisterandthe portis x18andthe outputportis x36, twowrite operations willbe requiredto
OVflagwillgoHIGH,indicatingdatais notvalid.
causetheoutputvalidflagofanemptyqueuetogoLOW,outputvalid(queue
TheNullqueueoperationonlyhassignificancetothereadportofthemulti- isnotempty).
queue, it is a means to force data through the pipeline to the output. Null Q
Note,thattheinputportservesallqueueswithinadevice,asdoestheoutput
selectionandoperationhasnomeaningonthewriteportofthedevice.Also, port,thereforetheinputbuswidthtoallqueuesisequal(determinedbytheinput
refer to Figure 21, Read Operation and Null Queue Select for diagram.
portsize)andtheoutputbuswidthfromallqueuesisequal(determinedbythe
outputportsize).
PAFn FLAG BUS OPERATION
The IDT72T51546/72T51556 multi-queue flow-control device can be
configuredforupto32queues,eachqueuehavingitsownalmostfullstatus.
Anactivequeuehasitsflagstatusoutputtothediscreteflags,FFandPAF,on
thewriteport.Queuesthatarenotselectedforawriteoperationcanhavetheir
PAFstatus monitoredviathe PAFnbus.ThePAFnflagbus is 8bits wide,so
that8queuesatatimecanhavetheirstatusoutputtothebus.If9ormorequeues
aresetupwithinadevicethenthereare2methodsbywhichthedevicecanshare
thebusbetweenqueues,“Direct”modeand“Polled”modedependingonthe
state ofthe FM(FlagMode)inputduringa MasterReset. If8orless queues
aresetupwithinadevicetheneachwillhaveitsowndedicatedoutputfromthe
bus.If8orlessqueuesaresetupinsingledevicemode,itisrecommendedto
configure the PAFnbus topolledmode as itdoes notrequire usingthe write
address(WRADD).
TABLE 3 — BUS-MATCHING SET-UP
x36 DEVICE
BM
IW
OW
Write Port Read Port
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
x36
x36
x36
x18
x9
x36
x18
x9
x36
x36
FULL FLAG OPERATION
Themulti-queueflow-controldeviceprovidesasingleFullFlagoutput,FF.
TheFFflagoutputprovidesafullstatusofthequeuecurrentlyselectedonthe
writeportforwriteoperations.Internallythemulti-queueflow-controldevice
monitorsandmaintainsastatusofthefullconditionofallqueueswithinit,however
onlythequeuethatisselectedforwriteoperationshasitsfullstatusoutputtothe
FF flag.This dedicatedflagis oftenreferredtoas the“activequeuefullflag”.
Whenqueueswitchesarebeingmadeonthewriteport,theFFflagoutput
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
onthecycleafteranewqueueselectionismade.Theuserthenhasafullstatus
forthenewqueueonecycleaheadoftheWCLKrisingedgethatdatacanbe
writtenintothenewqueue.Thatis,anewqueuecanbeselectedonthewrite
portviatheWRADDbus,WADENenableandarisingedgeofWCLK.Onthe
secondrisingedgeofWCLK,theFFflagoutputwillshowthefullstatusofthe
newlyselectedqueue.OnthethirdrisingedgeofWCLKfollowingthequeue
selection,datacanbewrittenintothenewlyselectedqueueprovidedthatdata
andenablesetup&holdtimesaremet.
EXPANDING UP TO 256 QUEUES OR PROVIDING DEEPER QUEUES
Expansioncantakeplaceusingeitherthestandardmodeorthepacketmode.
Inthe32queuemulti-queuedevice, theWRADDaddress bus is 8bits wide.
The5LeastSignificantbits(LSbs)areusedtoaddressoneofthe32available
queueswithinasinglemulti-queuedevice.The3MostSignificantbits(MSbs)
areusedwhenadeviceisconnectedinexpansionmodewithupto8devices
connectedinwidthexpansion,eachdevicehavingitsown3-bitaddress.When
logically expanded with multiple parts, each device is statically setup with a
uniquechipIDcodeontheIDpins,ID0,ID1,andID2.Adeviceisselectedwhen
the3MostSignificantbitsoftheWRADDaddressbusmatchesa3-bitIDcode.
Themaximumlogicalexpansionis 256queues (32queues x8devices)ora
minimumof8queues(1queueperdevicex8devices),eachofthemaximum
sizeoftheindividualmemorydevice.
24
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Note,theFFflagwillprovidestatusofanewlyselectedqueuetwoWCLKcycle Whenaqueueselectionismadethefirstdatafromthatqueuewillappearon
afterqueueselection,whichisonecyclebeforedatacanbewrittentothatqueue. theQoutdataoutputs3RCLKcycleslater,theOVwillchangestatetoindicate
Thispreventstheuserfromwritingdatatoaqueuethatisfull,(assumingthat validityofthedatafromthenewlyselectedqueueonthis3rd RCLKcyclealso.
a queue switchhas beenmade toa queue thatis actuallyfull).
Thepreviouscycleswillcontinuetooutputdatafromthepreviousqueueand
TheFFflagissynchronoustotheWCLKandalltransitionsoftheFFflagoccur theOVflagwillindicatethestatusofthoseoutputs.Again,theOVflagalways
basedonarisingedgeofWCLK.Internallythemulti-queuedevicemonitorsand indicatesstatusforthedatacurrentlypresentontheoutputregister.
keepsarecordofthefullstatusforallqueues.Itispossiblethatthestatusofa
TheOVflagissynchronoustotheRCLKandalltransitionsoftheOVflagoccur
FFflagmaybechanginginternallyeventhoughthatflagisnottheactivequeue basedonarisingedgeofRCLK.Internallythemulti-queuedevicemonitorsand
flag (selected on the write port). A queue selected on the read port may keepsarecordoftheoutputvalid(empty)statusforallqueues.Itispossiblethat
experienceachangeofitsinternalfullflagstatusbasedonreadoperations. thestatusofanOVflagmaybechanginginternallyeventhoughthatrespective
See Figure 10, Write Queue Select, Write Operation and Full Flag flagisnottheactivequeueflag(selectedonthereadport).Aqueueselected
Operation and Figure 12, Full Flag Timing in Expansion Mode for timing onthewriteportmayexperienceachangeofitsinternalOVflagstatusbased
information.
on write operations, that is, data may be written into that queue causing it to
become“notempty”.
EXPANSION MODE - FULL FLAG OPERATION
SeeFigure13,ReadQueueSelect,ReadOperationandFigure14,Output
Whenmulti-queuedevicesareconnectedinExpansionmodetheFFflags ValidFlagTimingfordetailsofthetiming.
of all devices should be connected together, such that a system controller
monitoring and managing the multi-queue devices write port only looks at a EXPANSION MODE – OUTPUT VALID FLAG OPERATION
singleFFflag(asopposedtoadiscreteFFflagforeachdevice).ThisFFflag
Whenmulti-queuedevicesareconnectedinExpansionmode,theOVflags
isonlypertinenttothequeuebeingselectedforwriteoperationsatthattime. of all devices should be connected together, such that a system controller
Remember,thatwheninexpansionmodeonlyonemulti-queuedevicecanbe monitoring and managing the multi-queue devices read port only looks at a
writtentoatanymomentintime,thustheFFflagprovidesstatusoftheactive singleOVflag(asopposedtoadiscreteOVflagforeachdevice).ThisOVflag
queue on the write port.
is onlypertinenttothequeuebeingselectedforreadoperations atthattime.
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheFFflag Remember,thatwheninexpansionmodeonlyonemulti-queuedevicecanbe
outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis readfromatanymomentintime,thustheOVflagprovidesstatusoftheactive
madeonlyasingledevicedrivestheFFflagbusandallotherFFflagoutputs queue on the read port.
connectedtotheFFflagbusareplacedintoHigh-Impedance.Theuserdoes
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheOVflag
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis
devicewillautomaticallyplaceitsFFflagoutputintoHigh-Impedancewhennone madeonlyasingledevicedrivestheOVflagbusandallotherOVflagoutputs
ofitsqueuesareselectedforwriteoperations.
connectedtotheOVflagbusareplacedintoHigh-Impedance.Theuserdoes
Whenqueueswithinasingledeviceareselectedforwriteoperations,theFF nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control
flagoutputofthatdevicewillmaintaincontroloftheFFflagbus.Its FF flagwill devicewillautomaticallyplaceitsOVflagoutputintoHigh-Impedancewhennone
simplyupdate betweenqueue switches toshowthe respective queue full ofitsqueuesareselectedforreadoperations.
status.
Whenqueueswithinasingledeviceareselectedforreadoperations,theOV
Themulti-queuedeviceplacesitsFFflagoutputintoHigh-Impedancebased flagoutputofthatdevicewillmaintaincontroloftheOVflagbus.ItsOVflagwill
onthe3bitIDcodefoundinthe3mostsignificantbitsofthewritequeueaddress simplyupdatebetweenqueueswitchestoshowtherespectivequeueoutput
bus,WRADD.Ifthe3mostsignificantbitsofWRADDmatchthe3bitIDcodesetup validstatus.
onthestaticinputs,ID0,ID1andID2thentheFFflagoutputoftherespective
Themulti-queuedeviceplacesitsOVflagoutputintoHigh-Impedancebased
devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheFFflag onthe3bitIDcodefoundinthe3mostsignificantbitsofthereadqueueaddress
outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure bus,RDADD.Ifthe3mostsignificantbitsofRDADDmatchthe3bitIDcodesetup
12,FullFlagTiminginExpansionModefordetailsofflagoperation,including onthestaticinputs,ID0,ID1andID2thentheOVflagoutputoftherespective
when more than one device is connected in expansion.
devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheOVflag
outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure
14,OutputValidFlagTimingfordetailsofflagoperation,includingwhenmore
OUTPUTVALIDFLAGOPERATION
The multi-queue flow-control device provides a single Output Valid flag thanone device is connectedinexpansion.
output,OV.TheOVprovidesanemptystatusordataoutputvalidstatusforthe
datawordcurrentlyavailableontheoutputregisterofthereadport.Therising ALMOST FULL FLAG
edgeofanRCLKcyclethatplacesnewdataontotheoutputregisteroftheread
As previously mentioned the multi-queue flow-control device provides a
port, also updates the OV flag to show whether or not that new data word is singleProgrammableAlmostFullflagoutput,PAF.ThePAFflagoutputprovides
actually valid. Internally the multi-queue flow-control device monitors and astatusofthealmostfullconditionfortheactivequeuecurrentlyselectedonthe
maintainsastatusoftheemptyconditionofallqueueswithinit,howeveronly writeportforwriteoperations.Internallythemulti-queueflow-controldevice
thequeuethatisselectedforreadoperationshasitsoutputvalid(empty)status monitorsandmaintainsastatusofthealmostfullconditionofallqueueswithin
outputtotheOVflag,givingavalidstatusforthewordbeingreadatthattime. it,howeveronlythequeuethatisselectedforwriteoperationshasitsfullstatus
Thenatureofthefirstwordfallthroughoperationmeansthatwhenthelast outputtothePAFflag.Thisdedicatedflagisoftenreferredtoasthe“activequeue
datawordisreadfromaselectedqueue,theOVflagwillgoHIGHonthenext almostfullflag”.ThepositionofthePAFflagboundarywithinaqueuecanbe
enabled read, that is, on the next rising edge of RCLK while REN is LOW.
atanypointwithinthatqueuesdepth.Thislocationcanbeuserprogrammed
Whenqueueswitchesarebeingmadeonthereadport,theOVflagwillswitch viatheserialportoroneofthedefaultvalues(8or128)canbeselectedifthe
toshowstatusofthenewqueueinlinewiththedataoutputfromthenewqueue. userhasperformeddefaultprogramming.
25
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost is,anewqueuecanbeselectedonthereadportviatheRDADDbus,RADEN
fullstatus,whenaqueueisselectedonthewriteport,thisstatusisoutputviathe enableandarisingedgeofRCLK.OnthethirdrisingedgeofRCLKfollowing
PAFflag.ThePAFflagvalueforeachqueueisprogrammedduringmulti-queue a queue selection, the data wordfromthe newqueue willbe available atthe
device programming (along with the number of queues, queue depths and outputregisterandthePAEflagoutputwillshowtheemptystatusofthenewly
almostemptyvalues).ThePAFoffsetvalue,m,forarespectivequeuecanbe selectedqueue.ThePAEisflagoutputistripleregisterbuffered,sowhenaread
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory operationoccurs atthealmostemptyboundarycausingtheselectedqueue
depthforthatqueue.ThePAFvalueofdifferentqueueswithinthesamedevice statustogoalmostemptythePAEwillgoLOW3RCLKcyclesaftertheread.
canbedifferentvalues.
Thesameistruewhenawriteoccurs,therewillbea3RCLKcycledelayafter
Whenqueueswitchesarebeingmadeonthewriteport,thePAFflagoutput thewriteoperation.
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
onthethirdcycleafteranewqueueselectionismade,onthesameWCLKcycle
thatdata canactuallybe writtentothe newqueue. Thatis, a newqueue can
beselectedonthewriteportviatheWRADDbus,WADENenableandarising
edgeofWCLK.OnthethirdrisingedgeofWCLKfollowingaqueueselection,
So the PAE flag delays are:
from a read operation toPAE flag LOW is 2 RCLK + tRAE
ThedelayfromawriteoperationtoPAEflagHIGHistSKEW2+RCLK+tRAE
Note, if tSKEW is violated there will be one added RCLK cycle delay.
ThePAEflagissynchronoustotheRCLKandalltransitionsofthePAEflag
thePAFflagoutputwillshowthefullstatusofthenewlyselectedqueue.ThePAF occur based on a rising edge of RCLK. Internally the multi-queue device
isflagoutputistripleregisterbuffered,sowhenawriteoperationoccursatthe monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible
almostfullboundarycausingtheselectedqueuestatustogoalmostfullthePAF thatthestatusofaPAEflagmaybechanginginternallyeventhoughthatflagis
willgoLOW3WCLKcyclesafterthewrite.Thesameistruewhenareadoccurs, nottheactivequeueflag(selectedonthereadport).Aqueueselectedonthe
there will be a 3 WCLK cycle delay after the read operation.
So the PAF flag delays are:
writeportmayexperienceachangeofitsinternalalmostemptyflagstatusbased
on write operations. The multi-queue flow-control device also provides a
duplicateofthePAEflagonthePAE[7:0]flagbus,thiswillbediscussedindetail
froma write operationtoPAF flagLOWis 2WCLK+tWAF
ThedelayfromareadoperationtoPAFflagHIGHistSKEW2+WCLK+tWAF inalatersectionofthedatasheet.
Note, if tSKEW is violated there will be one added WCLK cycle delay.
SeeFigures25and26forAlmostEmptyflagtimingandqueueswitching.
ThePAFflagissynchronoustotheWCLKandalltransitionsofthePAFflag
occur based on a rising edge of WCLK. Internally the multi-queue device POWER DOWN (PD)
monitorsandkeepsarecordofthealmostfullstatusforallqueues.Itispossible
This device has a power down feature intended for reducing power
thatthestatusofaPAFflagmaybechanginginternallyeventhoughthatflagis consumptionforHSTL/eHSTLconfiguredinputswhenthedeviceisidlefora
nottheactivequeueflag(selectedonthewriteport).Aqueueselectedonthe long period of time. By entering the power down state certain inputs can be
readportmayexperienceachangeofitsinternalalmostfullflagstatusbased disabled,therebysignificantlyreducingthepowerconsumptionofthepart.All
on read operations. The multi-queue flow-control device also provides a WENandRENsignalsmustbedisabledforaminimumoffourWCLKandRCLK
duplicateofthePAFflagonthePAF[7:0]flagbus,thiswillbediscussedindetail cycles before activating the power down signal. The power down signal is
inalatersectionofthedatasheet.
SeeFigures 23and24forAlmostFullflagtimingandqueueswitching.
asynchronousandneedstobeheldLOWthroughoutthedesiredpowerdowntime.
Duringpowerdown,thefollowingconditionsfortheinputs/outputssignalsare:
• Alldata inQueue(s)memoryare retained.
ALMOSTEMPTYFLAG
• Alldatainputsbecomeinactive.
As previously mentioned the multi-queue flow-control device provides a
single Programmable Almost Empty flag output, PAE. The PAE flag output
providesastatusofthealmostemptyconditionfortheactivequeuecurrently
selectedonthereadportforreadoperations.Internallythemulti-queueflow-
controldevicemonitorsandmaintainsastatusofthealmostemptyconditionof
allqueueswithinit,howeveronlythequeuethatisselectedforreadoperations
hasitsemptystatusoutputtothePAEflag.Thisdedicatedflagisoftenreferred
toasthe“activequeuealmostemptyflag”.ThepositionofthePAEflagboundary
withinaqueuecanbeatanypointwithinthatqueuesdepth.Thislocationcan
beuserprogrammedviatheserialportoroneofthedefaultvalues(8or128)
canbeselectediftheuserhasperformeddefaultprogramming.
• Allwrite andreadpointers maintaintheirlastvalue before powerdown.
• Allenables,chipselects,andclockinputpinsbecomeinactive.
• Alldataoutputsbecomeinactiveandenterhigh-impedancestate.
• Allflagoutputswillmaintaintheircurrentstatesbeforepowerdown.
• Allprogrammableflagoffsetsmaintaintheirvalues.
• Allechoclocks andenables willbecomeinactiveandenterhigh-
impedancestate.
• TheserialprogrammingandJTAGportwillbecomeinactiveandenter
high-impedancestate.
• AllsetupandconfigurationCMOSstaticinputsarenotaffected,asthese
pins are tied to a known value and do not toggle during operation.
Allinternalcounters,registers,andflagswillremainunchangedandmaintain
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost
emptystatus,whenaqueueisselectedonthereadport,thisstatusisoutputvia theircurrentstatepriortopowerdown.Clockinputscanbecontinuousandfree-
thePAEflag.ThePAEflagvalueforeachqueueisprogrammedduringmulti- runningduringpowerdown,butwillhavenoaffectonthepart.However,itis
queuedeviceprogramming(alongwiththenumberofqueues,queuedepths recommendedthattheclockinputsbelowwhenthepowerdownisactive.To
andalmostfullvalues).ThePAEoffsetvalue,n,forarespectivequeuecanbe exitpowerdownstateandresumenormaloperations,disablethepowerdown
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory signalbybringingitHIGH.Theremustbeaminimumof1µswaitingperiodbefore
depthforthatqueue.ThePAEvalueofdifferentqueueswithinthesamedevice readandwriteoperationscanresume.Thedevicewillcontinuefromwhereit
canbedifferentvalues.
hadstoppedandnoformofresetisrequiredafterexitingpowerdownstate.The
Whenqueueswitchesarebeingmadeonthereadport,thePAEflagoutput powerdownfeaturedoesnotprovideanypowersavingswhentheinputsare
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus, configuredforLVTTLoperation.However,itwillreducethecurrentforI/Osthat
onthethirdcycleafteranewqueueselectionismade,onthesameRCLKcycle are not tied directly to VCC or GND. See Figure 34, Power Down Operation,
thatdataactuallyfallsthroughtotheoutputregisterfromthenewqueue.That fortheassociatedtimingdiagram.
26
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING
Output Valid, OV Flag Boundary
Full Flag, FF Boundary
I/O Set-Up
OV Boundary Condition
OV Goes LOW after 1st Write
(seenote1belowfortiming)
I/O Set-Up
In36 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Boundary Condition
In36 to out36 (Almost Empty Mode)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after D+1 Writes
(seenotebelowfortiming)
OV Goes LOW after 1st Write
(seenote2belowfortiming)
In36 to out36
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after D Writes
(seenotebelowfortiming)
In36toout36(PacketMode)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenote1belowfortiming)
In36 to out18
FF Goes LOW after D Writes
(seenotebelowfortiming)
In36 to out18
(Bothportsselectedforsamequeue
when the 1st Word is written in)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenote1belowfortiming)
In36 to out18
FF Goes LOW after D Writes
(seenotebelowfortiming)
In36 to out9
(Writeportonlyselectedforqueue
(Bothportsselectedforsamequeue
when the 1st Word is written in)
when the 1st Word is written in)
In36 to out9
FF Goes LOW after D Writes
(seenotebelowfortiming)
In18 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenote1belowfortiming)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
In36 to out9
FF Goes LOW after D Writes
In9 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenote1belowfortiming)
(Writeportonlyselectedforqueue
(seenotebelowfortiming)
when the 1st Word is written in)
In18 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after ([D+1] x 2) Writes
(seenotebelowfortiming)
NOTE:
1. OV Timing
Assertion:
Write to OV LOW: tSKEW1 + RCLK + tROV
If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tROV
De-assertion:
In18 to out36
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after (D x 2) Writes
(seenotebelowfortiming)
Read Operation to OV HIGH: tROV
In9 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after ([D+1] x 4) Writes
(seenotebelowfortiming)
2. OV Timing when in Packet Mode (36 in to 36 out only)
Assertion:
Write to OV LOW: tSKEW4 + RCLK + tROV
If tSKEW4 is violated there may be 1 added clock: tSKEW4 + 2 RCLK + tROV
De-assertion:
In9 to out36
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after (D x 4) Writes
(seenotebelowfortiming)
Read Operation to OV HIGH: tROV
NOTE:
D = Queue Depth
FF Timing
Assertion:
Write Operation to FF LOW: tWFF
De-assertion:
Read to FF HIGH: tSKEW1 + tWFF
If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
I/O Set-Up
PAF & PAFn Boundary
in36 to out36
PAF/PAFn Goes LOW after
(Bothportsselectedforsamequeuewhenthe1st D+1-mWrites
Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)
in36 to out36
PAF/PAFn Goes LOW after
NOTE:
D = Queue Depth
m = Almost Full Offset value.
(Writeportonlyselectedforsamequeuewhenthe D-mWrites
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
Default values: if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
PAF Timing
in36 to out18
in36 to out9
in18 to out36
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
Assertion:
Write Operation to PAF LOW: 2 WCLK + tWAF
De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF
PAFn Timing
PAF/PAFn Goes LOW after
([D+1-m] x 2) Writes
(seenotebelowfortiming)
Assertion:
Write Operation to PAFn LOW: 2 WCLK* + tPAF
De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
in9 to out36
PAF/PAFn Goes LOW after
([D+1-m] x 4) Writes
(seenotebelowfortiming)
27
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Programmable Almost Empty Flag, PAE Boundary
I/O Set-Up PAE Assertion
PAE Goes HIGH after n+2
(Bothportsselectedforsamequeuewhenthe1st Writes
Programmable Almost Empty Flag Bus, PAEn Boundary
I/O Set-Up PAEn Boundary Condition
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st n+2Writes
in36 to out36
in36 to out36
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
in36 to out36
PAEn Goes HIGH after
in36 to out18
PAE Goes HIGH after n+1
(Bothportsselectedforsamequeuewhenthe1st Writes
(Writeportonlyselectedforsamequeuewhenthe n+1Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
in36 to out18
in36 to out9
in18 to out36
PAEn Goes HIGH after n+1
in36 to out9
PAE Goes HIGH after n+1
Writes (seebelowfortiming)
(Bothportsselectedforsamequeuewhenthe1st Writes
PAEn Goes HIGH after n+1
Writes(seebelowfortiming)
Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)
in18 to out36
PAE Goes HIGH after
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
PAE Goes HIGH after
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
in9 to out36
in18 to out36
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 4) Writes
(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 2) Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
NOTE:
in9 to out36
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 4) Writes
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
PAEn Goes HIGH after
in9 to out36
PAE Timing
(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 4) Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
NOTE:
Assertion:
Read Operation to PAE LOW: 2 RCLK + tRAE
De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAEn Timing
Assertion:
De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE
Read Operation to PAEn LOW: 2 RCLK* + tPAE
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
PACKET READY FLAG BUS, PRn BOUNDARY
Assertion:
PACKETREADYFLAG,PRBOUNDARY
Assertion:
Both the rising and falling edges of PRn are synchronous to RCLK.
PRn Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assumingaTSOPmarker,oninputD34has previouslybeenwritten).i.e.a
completepacketisavailablewithinaqueue.
Both the rising and falling edges of PR are synchronous to RCLK.
PR Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assumingaTSOPmarker,oninputD34has previouslybeenwritten).i.e.a
completepacketisavailablewithinaqueue.
Timing:
Timing:
FromWCLKrisingedgewritingtheTEOPwordPRgoes LOWafter:tSKEW4
+ 2 RCLK* + tPAE
FromWCLKrisingedgewritingtheTEOPwordPRgoes LOWafter:tSKEW4
+ 2 RCLK + tPR
If tSKEW4 is violated PRn goes LOW after tSKEW4 + 3 RCLK* + tPAE
*Ifaqueueswitchisoccurringonthereadportatthepointofflagassertionthere
may be one additional RCLK clock cycle delay.
De-assertion:
IftSKEW4isviolated:
PR goes LOW after tSKEW4 + 3 RCLK + tPR
(PleaserefertoFigure19,DataInput(Transmit)PacketModeofOperation,
fortimingdiagram).
PRRisingEdgeoccursuponreadingthelastRSOPmarker,fromoutputQ34.
i.e.therearenomorecompletepacketsavailablewithinthequeue.
Timing:
From RCLK rising edge Reading the RSOP word the PR goes HIGH after:
3 RCLK* + tPAE
De-assertion:
PRRisingEdgeoccursuponreadingthelastRSOPmarker,fromoutputQ34.
i.e.therearenomorecompletepacketsavailablewithinthequeue.
Timing:
From RCLK rising edge Reading the RSOP word the PR goes HIGH after:
3 RCLK + tPR
*Ifaqueueswitchisoccurringonthereadportatthepointofflagassertionor
de-assertionthere maybe one additionalRCLKclockcycle delay.
(PleaserefertoFigure20,DataOutput(Receive)PacketModeofOperation
fortimingdiagram).
28
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PAFn - DIRECT BUS
devicesholdtheirPAFnoutputsinHigh-Impedance.Whenthemasterdevice
If FM is LOW at master reset then the PAFn bus operates in Direct hascycledallofitsquadrantsitpassesatokentothenextdeviceinthechain
(addressed) mode. In direct mode the user can address the quadrant of andthatdeviceassumescontrolofthePAFnbusandthencyclesitsquadrants
queuestheyrequiretobeplacedontothePAFnbus.Forexample,consider andsoon,thePAFnbuscontroltokenbeingpassedonfromdevicetodevice.
the operationofthePAFnbus when26queues havebeensetup.Tooutput ThistokenpassingisdoneviatheFXOoutputsandFXIinputsofthedevices
statusofthefirstquadrant,Queue[0:7]theWRADDbusisusedinconjunction (“PAFExpansionOut”and“PAFExpansionIn”).TheFXOoutputofthemaster
withtheFSTR(PAFflagstrobe)inputandWCLK.Theaddresspresentonthe deviceconnects totheFXIoftheseconddeviceinthechainandtheFXOof
2leastsignificantbitsoftheWRADDbuswithFSTRHIGHwillbeselectedas thesecondconnectstotheFXIofthethirdandsoon.Thefinaldeviceinachain
the quadrantaddress ona risingedge ofWCLK. Sotoaddress quadrant1, hasitsFXOconnectedtotheFXIofthefirstdevice,sothatoncethePAFnbus
Queue[0:7]theWRADDbusshouldbeloadedwith“xxxxxx00”,thePAFnbus hascycledthroughallquadrantsofalldevices,controlofthePAFnwillpass
will change status to show the new quadrant selected 1 WCLK cycle after tothemasterdeviceagainandsoon.TheFSYNCofeachrespectivedevice
quadrantselection.PAFn[0:7]getsstatusofqueues,Queue[0:7]respectively. willoperateindependentlyandsimplyindicatewhenthatrespectivedevicehas
To address the second quadrant, Queue[8:15], the WRADD address is takencontrolofthebus andis placingits firstquadrantontothePAFnbus.
“xxxxxx01”.PAFn[0:7]getsstatusofqueues,Queue[8:15]respectively.To
WhenoperatinginsingledevicemodetheFXIinputmustbeconnectedto
addressthethirdquadrant,Queue[16:23],theWRADDaddressis“xxxxxx10”. theFXOoutputofthesamedevice.Insingledevicemodeatokenisstillrequired
PAF[0:7]getsstatusofqueues,Queue[16:23]respectively.Toaddressthe tobe passedintothe device foraccessingthe PAFnbus.
fourthquadrant,Queue[24:31],theWRADDaddressis“xxxxxx11”.PAF[0:1]
getsstatusofqueues,Queue[24:25]respectively.Remember,only26queues
PleaserefertoFigure32,PAFnBus–PolledModefortiminginformation.
weresetup,sowhenquadrant4isselectedtheunusedoutputsPAF[2:7]will PAEn/PRn FLAG BUS OPERATION
bedon'tcarestates.
The IDT72T51546/72T51556 multi-queue flow-control device can be
Note,thatifareadorwriteoperationis occurringtoaspecificqueue,say configured for up to 32 queues, each queue having its own almost empty/
queue‘x’onthesamecycleasaquadrantswitchwhichwillincludethequeue packetreadystatus.Anactivequeuehasitsflagstatusoutputtothediscrete
‘x’,thentheremaybeanextraWCLKcycledelaybeforethatqueues status flags,OV,PAE andPR,onthereadport.Queues thatarenotselectedfora
is correctly shown on the respective output of the PAFn bus. However, the readoperationcanhavetheirPAE/PRstatusmonitoredviathePAEn/PRnbus.
activePAFflagwillshowcorrectstatusatalltimes.
ThePAEn/PRnflagbusis8bitswide,sothat8queuesatatimecanhavetheir
Quadrantscanbeselectedonconsecutiveclockcycles,thatisthequadrant statusoutputtothebus.If9ormorequeuesaresetupwithinadevicethenthere
on the PAFn bus can change every WCLK cycle. Also, data present on the are2methodsbywhichthedevicecansharethebusbetweenqueues,"Direct"
inputbus,Din,canbewrittenintoaQueueonthesameWCLKrisingedgethat modeand"Polled"modedependingonthestateoftheFM(FlagMode)input
a quadrant is being selected, the only restriction being that a write queue duringaMasterReset.If8orlessqueuesaresetupwithinadevicetheneach
selectionandPAFnquadrantselectioncannotbemadeonthesamecycle. willhaveitsowndedicatedoutputfromthebus.If8orlessqueuesaresetup
If8orlessqueuesaresetupthenqueues,Queue[0:7]havetheirPAFstatus insingledevicemode,itisrecommendedtoconfigurethePAFnbustopolled
outputonPAF[0:7]constantly.
Whenthemulti-queuedevicesareconnectedinexpansionofmorethanone
mode as it does not require using the write address (WRADD).
devicethePAFnbussesofalldevicesareconnectedtogether,whenswitching PAEn/PRn - DIRECT BUS
betweenquadrantsofdifferentdevicestheusermustutilizethe3mostsignificant
If FM is LOW at master reset then the PAEn/PRn bus operates in Direct
bits of the WRADD address bus (as well as the 2 LSB’s). These 3 MSB’s (addressed) mode. In direct mode the user can address the quadrant of
correspondtothedeviceIDinputs,whicharethestaticinputs,ID0,ID1&ID2. queues they require to be placed on to the PAEn/PRn bus. For example,
PleaserefertoFigure29PAFn-DirectModeQuadrantSelectionfortiming consider the operation of the PAEn/PRn bus when 26 queues have been
information. AlsorefertoTable 1, Write Address Bus, WRADD.
setup.Tooutputstatusofthefirstquadrant,Queue[0:7]theRDADDbusisused
in conjunction with the ESTR (PAE/PR flag strobe) input and RCLK. The
addresspresentonthe2leastsignificantbitsoftheRDADDbuswithESTR
PAFn – POLLED BUS
IfFMisHIGHatmasterresetthenthePAFnbusoperatesinPolled(looped) HIGHwillbeselectedasthequadrantaddressonarisingedgeofRCLK.So
mode. In polled mode the PAFn bus automatically cycles through the 4 to address quadrant 1, Queue[0:7] the RDADD bus should be loaded with
quadrantswithinthedeviceregardlessofhowmanyqueueshavebeensetup “xxxxxx00”,thePAEn/PRnbuswillchangestatustoshowthenewquadrant
in the part. Every rising edge of the WCLK causes the next quadrant to be selected 1 RCLK cycle after quadrant selection. PAEn[0:7] gets status of
loadedonthe PAFnbus.Thedeviceconfiguredas themaster(MASTinput queues,Queue[0:7]respectively.
tiedHIGH),willtakecontrolofthePAFnafterMRSgoesLOW.Forthewhole
To address the second quadrant, Queue[8:15], the RDADD address is
WCLKcycle thatthe firstquadrantis onPAFnthe FSYNC(PAFnbus sync) “xxxxxx01”.PAEn[0:7]getsstatusofqueues,Queue[8:15]respectively.To
outputwillbeHIGH,forallotherquadrants,thisFSYNCoutputwillbeLOW. addressthethirdquadrant,Queue[16:23],theRDADDaddressis“xxxxxx10”.
This FSYNC output provides the user with a mark with which they can PAE[0:7]getsstatusofqueues,Queue[16:23]respectively.Toaddressthe
synchronizetothePAFnbus,FSYNCisalwaysHIGHfortheWCLKcyclethat fourthquadrant,Queue[24:31],theRDADDaddressis“xxxxxx11”.PAE[0:1]
the firstquadrantofa device is presentonthe PAFnbus.
getsstatusofqueues,Queue[24:25]respectively.Remember,only26queues
Whendevices areconnectedinexpansionmode,onlyonedevicewillbe weresetup,sowhenquadrant4isselectedtheunusedoutputsPAE[2:7]will
setas the Master, MASTinputtied HIGH, allotherdevices willhave MAST bedon'tcarestates.
tiedLOW.ThemasterdeviceisthefirstdevicetotakecontrolofthePAFnbus
Note,thatifareadorwriteoperationis occurringtoaspecificqueue,say
andwillplaceitsfirstquadrantonthebusontherisingedgeofWCLKafterthe queue‘x’onthesamecycleasaquadrantswitchwhichwillincludethequeue
MRS input goes HIGH. For the next 3 WCLK cycles the master device will ‘x’, thenthere maybe anextra RCLKcycle delaybefore thatqueues status
maintaincontrolofthePAFnbusandcycleitsquadrantsthroughit,allother is correctlyshownontherespectiveoutputofthe PAEn/PRnbus.
29
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Quadrantscanbeselectedonconsecutiveclockcycles,thatisthequadrant cansynchronizetothePAEn/PRnbus,ESYNCisalwaysHIGHfortheRCLK
onthePAEn/PRnbuscanchangeeveryRCLKcycle.Also,datacanberead cyclethatthefirstquadrantofadeviceis presentonthePAEn/PRnbus.
outofaQueueonthesameRCLKrisingedgethataquadrantisbeingselected,
theonlyrestrictionbeingthatareadqueueselectionandPAEn/PRnquadrant setastheMaster,MASTinputtiedHIGH,allotherdeviceswillhaveMASTtied
selectioncannotbemadeonthesameRCLKcycle. LOW.ThemasterdeviceisthefirstdevicetotakecontrolofthePAEn/PRnbus
If8orless queues aresetupthenqueues,Queue[0:7]havetheirPAE/PR andwillplaceitsfirstquadrantonthebusontherisingedgeofRCLKafterthe
statusoutputonPAE[0:7]constantly. MRSinputgoesLOW.Forthenext3RCLKcyclesthemasterdevicewillmaintain
When devices are connected in expansion mode, only one device will be
Whenthemulti-queuedevicesareconnectedinexpansionofmorethanone controlofthePAEn/PRnbusandcycleitsquadrantsthroughit,allotherdevices
device the PAEn/PRn busses of all devices are connected together, when holdtheirPAEn/PRnoutputsinHigh-Impedance.Whenthemasterdevicehas
switchingbetweenquadrantsofdifferentdevicestheusermustutilizethe3most cycledallofitsquadrantsitpassesatokentothenextdeviceinthechainand
significant bits of the RDADD address bus (as well as the 2 LSB’s). These 3 thatdeviceassumescontrolofthePAEn/PRnbusandthencyclesitsquadrants
MSB’scorrespondtothedeviceIDinputs,whicharethestaticinputs,ID0,ID1 andsoon, the PAEn/PRnbus controltokenbeingpassedonfromdevice to
& ID2.
device.ThistokenpassingisdoneviatheEXOoutputsandEXIinputsofthe
PleaserefertoFigure28,PAEn/PRn-DirectModeQuadrantSelectionfor devices(“PAEExpansionOut”and“PAEExpansionIn”).TheEXOoutputof
timinginformation.AlsorefertoTable2,ReadAddressBus,RDADD.
PAEn – POLLED BUS
themasterdeviceconnectstotheEXIoftheseconddeviceinthechainandthe
EXOofthesecondconnectstotheEXIofthethirdandsoon.Thefinaldevice
inachainhasitsEXOconnectedtotheEXIofthefirstdevice,sothatoncethe
If FM is HIGH at master reset then the PAEn/PRn bus operates in Polled PAEn/PRnbushascycledthroughallquadrantsofalldevices,controlofthe
(looped)mode.InpolledmodethePAEn/PRnbusautomaticallycyclesthrough PAEn/PRnwillpasstothemasterdeviceagainandsoon.TheESYNCofeach
the4quadrantswithinthedeviceregardlessofhowmanyqueueshavebeen respective device will operate independently and simply indicate when that
setupinthepart.EveryrisingedgeoftheRCLKcauses thenextquadrantto respectivedevicehastakencontrolofthebusandisplacingitsfirstquadrant
beloadedonthePAEn/PRnbus.Thedeviceconfiguredasthemaster(MAST ontothe PAEn/PRnbus.
inputtiedHIGH),willtakecontrolofthePAEn/PRnafterMRSgoesLOW.For
WhenoperatinginsingledevicemodetheEXIinputmustbeconnectedto
thewholeRCLKcyclethatthefirstquadrantisonPAEn/PRntheESYNC(PAEn/ theEXOoutputofthesamedevice.Insingledevicemodeatokenisstillrequired
PRnbussync)outputwillbeHIGH,forallotherquadrants,thisESYNCoutput tobepassedintothedeviceforaccessingthePAEnbus.
willbeLOW.ThisESYNCoutputprovidestheuserwithamarkwithwhichthey
PleaserefertoFigure33,PAEn/PRnBus–PolledModefortiminginformation.
30
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ECHO READ CLOCK (ERCLK)
slowerthantheslowestQn,dataoutput.RefertoFigure3,EchoReadClock
TheEchoReadClockoutputisprovidedinbothHSTLandLVTTLmode, and Data Output Relationship and Figure 27, Echo RCLK & Echo REN
selectableviaIOSEL.TheERCLKisafree-runningclockoutput,itwillalways Operationfortiminginformation.
follow the RCLK input regardless of REN and RADEN.
TheERCLKoutputfollowstheRCLKinputwithanassociateddelay.This ECHO READ ENABLE (EREN)
delayprovidestheuserwithamoreeffectivereadclocksourcewhenreading
TheEchoReadEnableoutputisprovidedinbothHSTLandLVTTLmode,
data from the Qn outputs. This is especially helpful at high speeds when selectableviaIOSEL.
variableswithinthedevicemaycausechangesinthedataaccesstimes.These
The EREN output is provided to be used in conjunction with the ERCLK
variations in access time maybe caused by ambient temperature, supply outputandprovidesthereadingdevicewithamoreeffectiveschemeforreading
voltage,devicecharacteristics.TheERCLKoutputalsocompensatesforany datafromtheQnoutputportathighspeeds.TheERENoutputiscontrolledby
tracelengthdelaysbetweentheQndataoutputsandreceivingdevicesinputs. internallogicthatbehavesasfollows:TheERENoutputisactiveLOWforthe
Anyvariationseffectingthedataaccesstimewillalsohaveacorresponding RCLK cycle that a new word is read out of the Queue. That is, a rising edge
effect on the ERCLK output produced by the Queue device, therefore the ofRCLKwillcauseERENtogoactive(LOW)ifRENis activeandtheQueue
ERCLKoutputleveltransitionsshouldalwaysbeatthesamepositionintime isNOTempty.
relativetothedataoutputs.Note,thatERCLKisguaranteedbydesigntobe
RCLK
tERCLK
tERCLK
ERCLK
tD
tA
Q
SLOWEST(3)
5998 drw08
NOTES:
1. REN is LOW. OE is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
Figure 3. Echo Read Clock and Data Output Relationship
31
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
Write to Queue
A
B
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BM
L
IW OW
A
B
C
D
Read from Queue
L
L
(a) x36 INPUT to x36 OUTPUT
Q35-Q27
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BM
H
IW OW
1st: Read from Queue
2nd: Read from Queue
C
D
L
L
Q26-Q18
Q17-Q9
Q8-Q0
A
B
(b) x36 INPUT to x18 OUTPUT
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BM
H
IW OW
D
1st: Read from Queue
2nd: Read from Queue
L
H
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q17-Q9
Q8-Q0
C
Q8-Q0
B
3rd: Read from Queue
4th: Read from Queue
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
A
(c) x36 INPUT to x9 OUTPUT
D35-D27
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
A
1st: Write to Queue
2nd: Write to Queue
B
D26-D18
D17-D9
D8-D0
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BM
H
IW OW
D
B
C
A
Read from Queue
H
L
(d) x18 INPUT to x36 OUTPUT
BYTE ORDER ON INPUT PORT:
D35-D27
D35-D27
D35-D27
D35-D27
D26-D18
D26-D18
D26-D18
D26-D18
D17-D9
D17-D9
D17-D9
D17-D9
D8-D0
A
1st: Write to Queue
2nd: Write to Queue
D8-D0
B
D8-D0
C
3rd: Write to Queue
4th: Write to Queue
D8-D0
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BM
H
IW OW
D
C
B
A
Read from Queue
5998 drw09
H
H
(e) x9 INPUT to x36 OUTPUT
Figure 4. Bus-Matching Byte Arrangement
32
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
MRS
t
RSS
RSS
WEN
REN
t
tRSR
SENI
tRSS
FSTR,
ESTR
tRSS
WADEN,
RADEN
t
RSS
RSS
RSS
ID0, ID1,
ID2
t
OW, IW,
BM
t
HIGH = Looped
LOW = Strobed (Direct)
FM
MAST
PKT
t
RSS
HIGH = Master Device
LOW = Slave Device
tRSS
HIGH = Packet Ready Mode
LOW = Almost Empty
t
RSS
RSS
HIGH = Default Programming
LOW = Serial Programming
DFM
t
HIGH = Offset Value is 128
LOW = Offset value is 8
DF
t
t
t
t
RSF
HIGH-Z if Slave Device
FF
LOGIC "0" if Master Device
RSF
RSF
RSF
LOGIC "1" if Master Device
OV
PAF
PAE
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
HIGH-Z if Slave Device
LOGIC "0" if Master Device
tRSF
tRSF
tRSF
tRSF
tRSF
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PAFn
PAEn
PR
HIGH-Z if Slave Device
LOGIC "0" if Master Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PRn
LOGIC "1" if OE is LOW and device is Master
Qn
HIGH-Z if OE is HIGH or Device is Slave
5998 drw10
NOTES:
1. OE can toggle during this period.
2. PRS should be HIGH during a MRS.
Figure 5. Master Reset
33
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
w-3
w-2
w-1
w
w+1
w+2
w+3
WCLK
tQH
tQS
WADEN
WEN
tENS
tENS
tAS
tAH
WRADD
Qx
tWFF
FF
tWAF
PAF
tPAF
Active Bus
PAF-Qx(5)
tPRSS
tPRSH
PRS
tPRSH
tPRSS
RCLK
tENS
tENS
REN
tQS
tQH
RADEN
tAS
tAH
RDADD
Qx
tROV
OV
tRAE
PAE
tPAE
Active Bus
PAE-Qx(6)
r-2
r-1
r
r+1
r+2
r+3
r+4
5998 drw11
NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 3 clock cycles before the Partial Reset takes place, on both the write and read ports.
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
Figure 6. Partial Reset
Master Reset
Default Mode
DFM = 0
MRS
MRS
MRS
DFM
DFM
DFM
MQ2
MQn
MQ1
Serial Loading
Complete
SENI
SENO
SO
SENI
SENI
SENO
SO
SENO
SO
Serial Enable
Serial Input
SI
SI
SI
SCLK
SCLK
SCLK
5998 drw12
Serial Clock
Figure 7. Serial Port Connection for Serial Programming
34
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
35
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
36
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
37
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
tENH
tENS
WEN
tDS
tDH
tDS
tDH
tDS
tDH
W3
W1
W2
Dn
tSKEW1
1
2
RCLK
REN
Qout
tENS
tA
tA
tA
Last Word Read Out of Queue
W1 Qy
FWFT
W2 Qy
FWFT
W3 Qy
tROV
tROV
OV
5998 drw16
NOTES:
1. Qy has previously been selected on both the write and read ports.
2. OE is LOW.
3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.
Figure 11. Write Operations & First Word Fall Through
38
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
39
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
40
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
*J*
RCLK
REN
tENS
tAS
tAH
tAS
tAH
RDADD
RADEN
D1
Q30
D1 Q15
tQS
tQH
tQH
tQS
t
A
tA
t
A
t
A
t
tOLZ
Qout
(Device 1)
D
1
Q
30
WD
Last Word
D
1
Q
15
D1
Q
15 We Last Word
W0 Q15
PFT We-1
D
1
t
ROV
tROV
tROV
ROV
t
OVLZ
HIGH-Z
OV
(Device 1)
tOVHZ
OV
(Device 2)
tSKEW1
WCLK
WEN
tENH
tENS
tAS
tAH
WRADD
D1 Q15
tQS
tQ
H
WADEN
Din
tDS
tDH
D
1
W
Q
15
0
5998 drw19
Cycle:
*A* Queue 30 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control
of Qout bus, its Qout outputs are in Low-Impedance. This diagram only shows the Qout outputs of device 1. (Reads are disabled).
*B* Reads are now enabled. A word from the previously selected queue of Device 2 will be read out.
*C* After a queue switch, there is a 3 RCLK latency for output data.
*D* The Qout of Device 1 goes to Low-Impedance and word Wd is read from Q30 of D1. This happens to be the last word of Q30. Device 2 places its Qout outputs into
High-Impedance, device 1 has control of the Qout bus. The OV flag of Device 2 goes to High-Impedance and Device 1 takes control of OV. The OV flag of Device 1 goes LOW
to show that Wd of Q30 is valid.
*E* Queue 15 of device 1 is selected for read operations. The last word of Q30 was read on the previous cycle, therefore OV goes HIGH to indicate that the data on the Qout is
not valid (Q30 was read to empty). Word, Wd remains on the output bus.
*F* The last word of Q30 remains on the Qout bus, OV is HIGH, indicating that this word has been previously read.
*G* The next word (We-1), available from the newly selected queue, Q15 of device 1 is now read out. This will occur regardless of REN, 2 RCLK cycles after queue selection
due to the FWFT operation. The OV flag updates 3 RCLK cycles after a queue selection.
*H* The last word, We is read from Q15, this queue is now empty.
*I* The OV flag goes HIGH to indicate that Q15 was read to empty on the previous cycle.
*J* Due to a write operation the OV flag goes LOW and data word W0 is read from Q15. The latency is: tSKEW1 + 1*RCLK + tROV.
Figure 14. Output Valid Flag Timing (In Expansion Mode)
41
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
42
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
EO
43
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
44
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
45
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
46
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
47
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SELECT
NULL QUEUE
NEW QUEUE
*D*
SELECT
*A*
*B*
*C*
*E*
*F*
*G*
RCLK
tAS
tAH
tAS
tAH
00100000
00000100
RDADD
RADEN
tQS
tQH
tQS
tQH
tAS
tAH
Null-Q
tENS
tENH
REN
tA
tA
tA
tA
t
A
Q4 W0
FWFT
Qout
OV
Q1 Wn-4
Q1 Wn-3
Q1 Wn-2
Q1 Wn-1
Q1 Wn
tROV
tROV
5998 drw26
NOTES:
1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words
from that queue.
2. Please see Figure 22, Null Queue Flow Diagram.
Cycle:
*A* Null Q of device 0 is selected, when word Wn-3 from previously selected Q1 is read.
*C* REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register.
Note: *B* and *C* are a minimum 3 RCLK cycles between queue selects.
*D* The Null Q is seen as an empty Queue on the read side, therefore Wn of Q1 remains in the O/P register and OV goes HIGH. A new queue, Q4 is selected.
*G* 1st word, W0 of Q4 falls through present on the O/P register after 3 RCLK cycles after the queue select.
Figure 21. Read Operation and Null Queue Select
*A*
*B*
*C*
*D*
*E*
*F*
*G*
Null
Queue
Null
Queue
Queue 4
Memory
Queue 4
Memory
Queue 1
Memory
Queue 1
Memory
Null
Queue
Q1
Q1
Q1
Q1
Q1
Q4
Q4
Wn
Wn
Wn
Wn
Wn
W0
W1
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
Qn
Q1
Q1
Q1
Q1
Q1
Q4
Wn-2
Wn-1
Wn
Wn
Wn
Wn
W0
5998 drw27
Figure 22. Null Queue Flow Diagram
48
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
WCLK
WEN
2
1
tENH
tENS
tAS
tAH
tAS
tQS
tAH
WRADD
D1 Q5
D1 Q9
tQS
tQH
tQH
WADEN
Din
tDS
tDH
WD-m
D1 Q5
tWAF
tWAF
tAFLZ
HIGH-Z
PAF
(Device 1)
tFFHZ
PAF
(Device 2)
5998 drw28
Cycle:
*A* Queue 5 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* No write occurs.
*D* Word, Wd-m is written into Q5 causing the PAF flag to go from LOW to HIGH. The flag latency is 3 WCLK cycles + tWAF.
*E* Queue 9 in device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 3 WCLK + tWAF latency.
*F* The PAF flag goes LOW based on the write 2 cycles earlier.
*G* No write occurs.
*H* The PAF flag goes HIGH due to the queue switch to Q9.
Figure 23. Almost Full Flag Timing and Queue Switch
tCLKL
tCLKL
WCLK
WEN
PAF
1
2
1
tENS
tENH
tWAF
tWAF
D - (m+1) words in Queue(2)
D-(m+1) words
in Queue
D - m words in Queue
tSKEW2
RCLK
tENS
tENH
5998 drw29
REN
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + tWAF
De-assertion: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there will be one extra WCLK cycle.
Figure 24. Almost Full Flag Timing
49
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
RCLK
REN
HIGH
AS
t
tAH
tAS
tAH
RDADD
D1
Q30
D1 Q15
tQS
tQH
tQH
tQS
RADEN
Qout
t
A
tA
tA
tA
tOLZ
HIGH-Z
HIGH-Z
D
1
Q30
Wn
D
1
Q30
Wn+1
D1
Q15
W0
D1 Q15 W1
tRAE
t
RAE
tAELZ
PAE
(Device 1)
tAEHZ
PAE
(Device 2)
HIGH-Z
5998 drw30
Cycle:
*A* Queue 30 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* No read occurs.
*D* The PAE flag output now switches to device 1. Word, Wn is read from Q30 due to the FWFT operation. This read operation from Q30 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*E* Q15 of device 1 is selected.
*F* The PAE flag goes LOW due to the read from Q30 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*G* Word, W0 is read from Q15 due to the FWFT operation.
*H* The PAE flag goes HIGH to show that Q15 is not almost empty.
Figure 25. Almost Empty Flag Timing and Queue Switch
tCLKL
tCLKH
WCLK
tENH
tENS
WEN
PAE
n+1 words in Queue
SKEW2
n+2 words in Queue
n+1 words in Queue
tRAE
t
tRAE
RCLK
1
2
tENS
tENH
5998 drw31
REN
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + tRAE
De-assertion: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there will be one extra RCLK cycle.
Figure 26. Almost Empty Flag Timing
50
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ERN
51
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
RCLK
tQS
tQH
t
QS
tQS
Quadrant 0
t
QH
tQH
Device 1
Device 1
Device 1
Quadrant 2
Quadrant 3
001xxx10
001xxx11
001xxx00
RDADD
ESTR
tSTS
tSTH
tSTS
tSTH
tPAE
tPAE
tPAE
PAEn/
PRn
Device 1 Quadrant 2
Device 1 Quadrant 3
Device 1 Quadrant 0
5998 drw33
NOTES:
1. Quadrants can be selected on consecutive cycles.
2. On an RCLK cycle that the ESTR is HIGH, the RADEN input must be LOW.
3. There is a latency of 2 RCLK for the PAEn bus to switch.
Figure 28. PAEn/PRn - Direct Mode - Quadrant Selection
WCLK
tQS
tQH
t
QS
tQS
Quadrant 2
t
QH
tQH
Device 1
Device 1
Device 1
Quadrant 1
Quadrant 3
001xxx01
001xxx11
001xxx10
WRADD
FSTR
tSTS
tSTH
tSTS
tSTH
tPAF
tPAF
tPAF
PAFn
Device 1 Quadrant 1
Device 1 Quadrant 3
Device 1 Quadrant 2
5998 drw34
NOTES:
1. Quadrants can be selected on consecutive cycles.
2. On a WCLK cycle that the FSTR is HIGH, the WADEN input must be LOW.
3. There is a latency of 2 WCLK for the PAFn bus to switch.
Figure 29. PAFn - Direct Mode - Quadrant Selection
52
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
1
*C*
2
*D*
3
*E*
*F*
*G*
*H*
WCLK
WADEN
FSTR
tQS
tQH
tQS
tQH
t
QS
tQH
t
STS
tSTH
tENS
tENS
tENH
tENH
WEN
tAS
tAH
tAH
tAS
tAS
tAH
D4 quad 3
D3Q8
011 01000
WRADD
Dn
D5Q24
100 11000
tDS
tDH
tDS
t
DS
100 xxx10
t
DH
t
DH
Wp
Wp+1
Wp+2
Wn+1
D5Q24
Wn
Wx
D3 Q8
D5 Q24
Writes to Previous Q
t
SKEW3
RCLK
RADEN
ESTR
1
2
3
1
2
3
tQS
tQH
tSTS
t
STH
t
ENS
tENH
REN
tAH
tAS
tAS
tAH
RDADD
D5 quad 4
D5Q24
100 11000
101 xxx11
tA
t
A
tA
t
A
t
A
Wy+1
D5 Q24
Wy
D5 Q24
Wy+2
D5 Q24
Wy+3
D5 Q24
Device 5 -Qn
Wa
D5 Q17
Wa+1
D5 Q17
Previous value loaded on to PAE bus
Prev PAEn
tPAEHZ
tPAE
tPAEZL
xxxx xxx0
D5Quad4
xxxx xxx1
D5Quad 4
Device 5 PAEn
xxxx xxx0
D5Quad4
xxxx xxx1
D5Quad 4
Previous value loaded on to PAE bus
D5 Q17 Status
Bus PAEn
t
RAE
tRAE
tRAE
D5 Q24
status
Device 5 PAE
5998 drw35
*FF*
*AA*
*BB*
*CC*
*DD*
*GG*
*EE*
Cycle:
*A* Queue 24 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA* Queue 24 of Device 5 is selected for read operations.
A quadrant from another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
*B* Word Wp+1 is written into the previously selected queue.
*BB* Current Word is kept on the output bus since REN is HIGH.
*C* Word Wp+2 is written into the previously selected queue.
*CC* Word Wa+1 of D5 Q17 is read due to FWFT.
*D* Word, Wn is written into the newly selected queue, Q24 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added).
*DD* Word, Wy from the newly selected queue, Q24 will be read out due to FWFT operation.
Quadrant 4 of Device 5 is selected on the PAEn bus. Q24 of device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency before
the PAEn bus changes to the new selection.
*E* Queue 8 of Device 3 is selected for write operations.
Word Wn+1 is written into Q24 of D5.
*EE* Word, Wy+1 is read from Q24 of D5.
*F* No writes occur.
*FF* Word, Wy+2 is read from Q24 of D5.
The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and quadrant 4 is placed onto the outputs. The device of the previously selected
quadrant now places its PAEn outputs into High-Impedance to prevent bus contention.
The discrete PAE flag will go HIGH to show that Q24 of D5 is not almost empty. Q24 of device 5 will have its PAE status output on PAE[0].
*G* Quadrant 3 of device 4 is selected on the write port for the PAFn bus.
*GG* The PAEn bus updates to show that Q24 of D5 is almost empty based on the reading out of word, Wy+1.
The discrete PAE flag goes LOW to show that Q24 of D5 is almost empty based on the reading of Wy+1.
*H* Word, Wx is written into Q8 of D3.
Figure 30. PAEn - Direct Mode, Flag Operation
53
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK
tQH
tQS
tQS
tQH
RADEN
tSTH
tSTS
ESTR
REN
tAS
tAH
tAH
tAH
tAS
tAS
D7 quad 1
RDADD
D6Q2
D0Q31
110 00010
111 xxx00
000 11111
OE
t
A
t
A
tA
t
A
tOLZ
Qout
W
X
W
X +1
Prev. Q
W
D0 Q31
D - M + 2
W0
D6 Q2
W
D0 Q31
D-M+1
Prev. Q
t
SKEW3
WCLK
FSTR
1
2
3
tSTS
tSTH
tAS
tAH
tAS
tAH
WRADD
D0 quad4
000 xxx11
D0 Q31
tENS
tENH
WEN
tQS
tQH
WADEN
Din
t
DS
t
DH
tDS
t
DH
tDS
tDH
W
y+1
Wy+2
Word W
y
D0 Q31
D0 Q31
D0 Q31
tPAFLZ
tPAF
tPAF
Device 0 PAFn
0xxx xxxx
0xxx xxxx
1xxx xxxx
1xxx xxxx
0xxx xxxx
0xxx xxxx
D0Quad4
D0Quad4
D0Quad4
D0Quad4
D0Quad4
HIGH-Z
DXQuad y
D0Quad4
Bus PAFn
tPAFHZ
HIGH-Z
D
XQuad y
Prev.
PAFn
tPAFLZ
tWAF
Device 0
HIGH - Z
5998 drw36
PAF
*AA*
*BB*
*CC*
*DD*
*EE*
*FF*
*GG*
Cycle:
*A* Queue 31 of device 0 is selected for read operations.
The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.
*AA* Quadrant 4 of device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected quadrant, Quad Y of device X.
*B* No read operation.
*BB* Queue 31 of device 0 is selected on the write port.
*C* Word, Wx+1 is read out from the previous queue due to the FWFT effect.
*CC* PAFn continues to show status of Quad4 D0.
The PAFn bus is updated with the quadrant selected on the previous cycle, D0 Quad 4. PAF[7] is LOW showing the status of queue 31.
The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
*D* A new quadrant, Quad 1 of Device 7 is selected for the PAFn bus.
Word, Wd-m+1 is read from Q31 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q31. This read will cause the PAF[7] output to go from
LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.
*DD* No write operation.
*E* No read operations occur, REN is HIGH.
*EE* PAF[7] goes HIGH to show that D0 Q31 is not almost empty due to the read on cycle *C*.
The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q31.
*F* Queue 2 of Device 6 is selected for read operations.
*FF* Word, Wy+1 is written into D0 Q31.
*G* Word, Wd-m+2 is read out due to FWFT operation.
*GG* PAF[7] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q31 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q31.
*H* No read operation.
*I* Word, W0 is read from Q0 of D6, selected on cycle *F*, due to FWFT.
Figure 31. PAFn - Direct Mode, Flag Operation
54
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
APF
55
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
P
PAE
56
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
WEN
tDH
tDS
tDH
tDS
tDS
tDH
tDS
WD10
WD11
WD12
WD13
D[39:0]
1ns
(1)
3
1
2
4
RCLK
REN
(7)
PDHZ
(2)
t
tPDLZ
tA
tA
t
A
tA
Hi-Z
WD1
WD2
WD3
WD4
WDH
WDS
Q[39:0]
(2)
PDH
t
(2)
PDH
t
tPDL
PD
tERCLK
Hi-Z
Hi-Z
ERCLK
tEREN
tEREN
EREN
5998 drw39
NOTES:
1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted.
2. When the PD input becomes deasserted, there will be a 1µs waiting period before read and write operations can resume.
All input and output signals will also resume after this time period.
3. Set-up and configuration static inputs are not affected during power down.
4. Serial programming and JTAG programming port are inactive during power down.
5. RCS = 0, WCS = 0 and OE = 0. These signals can toggle during and after power down.
6. All flags remain active and maintain their current states.
7. During power down, all outputs will be in high-impedance.
Figure 34. Power Down Operation
57
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Serial Programming Data Input
Serial Enable
SENI
SI FXI EXI
Output Data Bus
Data Bus
Q -Q
D -D
0
35
0
35
Read Clock
Write Clock
RCLK
WCLK
Write Enable
Read Enable
WEN
REN
RDADD
RADEN
Read Queue Select
Read Address
Write Queue Select
Write Address
WRADD
WADEN
DEVICE
1
Empty Strobe
Full Strobe
ESTR
FSTR
PAFn
Programmable Almost Full
Programmable Almost Empty
PAEn
Empty Sync 1
Output Valid Flag
Almost Empty Flag
Full Sync1
ESYNC
FSYNC
Full Flag
OV
FF
Almost Full Flag
Serial Clock
PAF
PAE
PR
Packet
Reads
SCLK
SENO SO FXO EXO
SENI SI FXI EXI
Q -Q
D -D
0
35
0
35
WCLK
RCLK
WEN
REN
WRADD
WADEN
RDADD
RADEN
DEVICE
2
FSTR
PAFn
ESTR
PAEn
Empty Sync 2
Full Sync2
FSYNC
ESYNC
FF
OV
PAF
PAE
SCLK
PR
SO FXO EXO
SENO
SENI SI FXI EXI
Q -Q
D -D
0
35
0
35
WCLK
RCLK
REN
WEN
WRADD
WADEN
RDADD
RADEN
DEVICE
n
FSTR
PAFn
FSYNC
ESTR
PAEn
Full Sync n
Empty Sync n
ESYNC
FF
OV
PAF
PAE
PR
SCLK
SENO
FXO EXO
DONE
5998 drw40
NOTES:
1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO
outputs are DNC (Do Not Connect).
2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.
Figure 35. Multi-Queue Expansion Diagram
58
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T51546/72T51556
incorporatesthenecessarytapcontrollerandmodifiedpadcellstoimplement
theJTAGfacility.
Thefollowingsections provideabriefdescriptionofeachelement.Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
The Figure belowshows the standardBoundary-ScanArchitecture
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5998 drw41
Figure 36. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor.Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
59
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-IR
Shift-DR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-IR
Pause-DR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-IR
Update-DR
1
0
1
0
5998 drw42
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal Queue operations can begin.
Figure 37. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram.
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overthe Queue andmustbe resetafterpowerupofthe device. See TRST
descriptionformoredetailsonTAPcontrollerreset.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenabling
thenormaloperationoftheIC.TheTAPcontrollerstatemachineisdesigned
insuchawaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-
Logic-ResetstatecanbeenteredbyholdingTMSathighandpulsingTCKfive
times. This is the reasonwhythe TestReset(TRST)pinis optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
60
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
JTAG INSTRUCTION REGISTER
THE INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate.Theinstructionisdecodedto
performthefollowing:
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth.Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current.Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
•
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata.Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions.Instructionsaredecodedasfollows.
TESTDATAREGISTER
Hex
Value
00
01
02
04
0F
Instruction
Function
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
Thefollowingsections provideabriefdescriptionofeachelement.Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
EXTEST
SAMPLE/PRELOAD
IDCODE
HIGH-IMPEDANCE
BYPASS
SelectBoundaryScanRegister
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
JTAG
SelectBypassRegister
JTAG INSTRUCTION REGISTER DECODING
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO.Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
Thefollowingsectionsprovideabriefdescriptionofeachinstruction.For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
EXTEST
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO.Duringthisinstruction,theboundary-scanregisterisaccessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports.TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
THE DEVICE IDENTIFICATION REGISTER
IDCODE
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDTJEDECIDnumberis0xB3.Thistranslatesto0x33whentheparityis
droppedinthe11-bitManufacturerIDfield.
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDI and TDO. The device identification register is a 32-bit shift register
containinginformationregardingtheICmanufacturer,devicetype,andversion
code.Accessingthedeviceidentificationregisterdoesnotinterferewiththe
operationoftheIC.Also,accesstothedeviceidentificationregistershouldbe
immediatelyavailable,viaaTAPdata-scanoperation,afterpower-upofthe
ICoraftertheTAPhasbeenresetusingtheoptionalTRSTpinorbyotherwise
movingtotheTest-Logic-Resetstate.
For the IDT72T51546/72T51556, the Part Number field contains the
followingvalues:
Device
IDT72T51546
IDT72T51556
Part# Field (HEX)
0x48C
0x48D
SAMPLE/PRELOAD
TherequiredSAMPLE/PRELOADinstructionallowstheICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.This instructionis alsousedtopreloadtestdata
intotheboundary-scanregisterbeforeloadinganEXTESTinstruction.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
JTAG DEVICE IDENTIFICATION REGISTER
61
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
toTDOwithoutaffectingtheconditionoftheICoutputs.
theIC.
62
IDT72T51546/72T515562.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5998 drw43
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 38. Standard JTAG Timing
JTAGACELECTRICAL
CHARACTERISTICS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions
Min. Max. Units
SYSTEMINTERFACEPARAMETERS
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
IDT72T51546
IDT72T51556
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
63
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Plastic Ball Grid Array (PBGA, BB256-1)
BB
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
5
6
Commercial Only
Commercial and Industrial
Low Power
L
72T51546 1,179,648 bits 2.5V Multi-Queue Flow-Control Device
72T51556 2,359,296 bits 2.5V Multi-Queue Flow-Control Device
5998 drw44
NOTE:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
DATASHEETDOCUMENTHISTORY
06/06/2003
11/06/2003
pgs. 1 through 64.
pgs. 1, 4, 17 and 18.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1533
email:Flow-Controlhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
64
相关型号：
IDT72T51546L5BB
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT
IDT72T51546L5BBI
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT
IDT72T51546L6BB
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT
IDT72T51546L6BBI
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT
IDT72T51546L7-5BB
FIFO, 32KX36, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT
IDT72T51546L7-5BBI
FIFO, 32KX36, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT
IDT72T51553L5BB8
FIFO, 128KX18, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT
IDT72T51553L6BB8
FIFO, 128KX18, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT
©2020 ICPDF网 联系我们和版权申明