IDT72T51546L7-5BB [IDT]
FIFO, 32KX36, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256;
| 型号： | IDT72T51546L7-5BB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 32KX36, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 先进先出芯片 |
| 文件： | 总13页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V MULTI-QUEUE FIFO (32 QUEUES)
36 BIT WIDE CONFIGURATION
1,179,648 bits
ADVANCE INFORMATION
IDT72T51546
IDT72T51556
2,359,296 bits
•
•
Direct or polled operation of flag status bus
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
– x36in to x36out
– x18in to x36out
– x9in to x36out
– x36in to x18out
– x36in to x9out
FWFT mode of operation on read port
Packet Ready mode of operation
Partial Reset, clears data in single Queue
Expansion of up to 8 Multi-Queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
FEATURES:
•
Choose from among the following memory density options:
IDT72T51546
IDT72T51556
Total Available Memory = 1,179,648 bits
Total Available Memory = 2,359,296 bits
•
•
•
Configurable from 1 to 32 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
Independent Read and Write access per queue
User programmable via serial port
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
Default Multi-Queue device configurations
– IDT72T51546 : 1,024 x 36 x 32Q
•
•
•
•
•
•
•
•
•
– IDT72T51556 : 2,048 x 36 x 32Q
•
•
•
•
•
•
•
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
Individual, Active queue flags (OV, FF, PAE, PAF, PR)
8 bit parallel flag status on both read and write ports
Shows PAE and PAF status of 8 Queues
•
•
•
•
DATA PATH FLOW DIAGRAM
MULTI-QUEUE FIFO
RADEN
ESTR
Q0
Q1
Q2
WADEN
FSTR
RDADD
WRADD
8
8
REN
RCLK
EREN
WEN
WCLK
ERCLK
OE
Q
D
in
out
x36
x36
DATA IN
DATA OUT
OV
PR
FF
PAF
PAE
Qmax
PAFn
PAEn
8
8
PRn
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IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc
OCTOBER 2, 2001
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5998/-
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648 and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Theuserhasfullflexibilityconfiguringqueueswithinthedevice,beingable
toprogramthetotalnumberofqueuesbetween1and32,theindividualqueue
depthsbeingindependentofeachother.Theprogrammableflagpositionsare
alsouserprogrammable.Allprogrammingisdoneviaadedicatedserialport.
IftheuserdoesnotwishtoprogramtheMulti-Queuedevice,adefaultoptionis
availablethatconfiguresthedeviceinapredeterminedmanner.
BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster
Reset latches in all configuration setup pins and must be performed before
programmingofthedevicecantakeplace.APartialResetwillresetthereadand
writepointersofanindividualFIFOqueue,providedthatthequeueisselected
onboththe write portandreadportatthe time ofpartialreset.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided.TheseareoutputsfromthereadportoftheFIFOthatarerequiredfor
highspeeddatacommunication,toprovidetightersynchronizationbetweenthe
databeingtransmittedfromtheQnoutputsandthedatabeingreceivedbythe
input device. Data read from the read port is available on the output bus with
respecttoERENandERCLK,thisisveryusefulwhendataisbeingreadathigh
speed.
The Multi-Queue FIFO has the capability of operating its IO in either 2.5V
LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected via the
IOSELinput.Thecoresupplyvoltage(VCC)totheMulti-Queueisalways2.5V,
howevertheoutputlevelscanbesetindependentlyviaaseparatesupply,VDDQ.
ThedevicesalsoprovideadditionalpowersavingsviaaPowerDownInput.
This input disables the write port data inputs when no write operations are
required.
AJTAGtestportisprovided,heretheMulti-QueueFIFOhasafullyfunctional
BoundaryScanfeature,compliantwithIEEE1449.1StandardTestAccessPort
andBoundaryScanArchitecture.
DESCRIPTION:
The IDT72T51546/72T51556 Multi-Queue FIFO device is a single chip
withinwhichanywherebetween1and32discreteFIFOqueuescanbesetup.
Allqueueswithinthedevicehaveacommondatainputbus,(writeport)and
acommondataoutputbus,(readport).Datawrittenintothewriteportisdirected
toa respective queue via aninternalde-multiplexoperation, addressedby
theuser.Datareadfromthereadportisaccessedfromarespectivequeue
via aninternalmultiplexoperation, addressedbythe user. Data writes and
readscanbeperformedathighspeedsupto200MHz,withaccesstimesof
3.6ns.Datawriteandreadoperationsaretotallyindependentofeachother,
aqueuemaybeselectedonthewriteportandadifferentqueueontheread
portorbothportsmayselectthesamequeuesimultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.
Two8bitprogrammableflagbussesareavailable,providingstatusofqueues
notselectedforwriteorreadoperations.When8orlessqueuesareconfigured
in the device these flag busses provide an individual flag per queue, when
morethan8queuesareused,eitheraPolledorDirectmodeofbusoperation
providestheflagbusseswithallqueuesstatus.
Bus Matchingis availableonthis device,eitherportcanbe9bits,18bits
or36bitswideprovidedthatatleastoneportis36bitswide.WhenBusMatching
is usedthe device ensures the logicaltransferofdata throughputina Little
Endianmanner.
A packet ready mode of operation is also provided when the device is
configuredfor36bitinputand36bitoutputportsizes.ThePacketReadymode
provides the user with a flag output indicating when at least one (or more)
packets of data within a queue is available for reading. The Packet Ready
providestheuserwithameansbywhichtomarkthestartandendofpackets
ofdatabeingpassedthroughtheFIFOqueues.TheMulti-Queuedevicethen
providestheuserwithaninternallygeneratedpacketreadystatusperqueue.
SeeFigure1,Multi-QueueFIFOBlockDiagramforanoutlineofthefunctional
blockswithinthedevice.
2
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D
D
= TEOP
= TSOP
D
in
35
34
x9, x18, x36
2
D
- D
35
0
WCLK
WEN
TMS
TDI
INPUT
DEMUX
JTAG
TDO
TCK
Logic
8
WRADD
WADEN
Write Control
Logic
TRST
Write Pointers
PR
Packet Mode
Logic
8
PAF
General Flag
Monitor
PRn/PAEn
FSTR
PAFn
8
FSYNC
Upto 32
FIFO
Queues
FXO
FXI
OV
Active Q
Flags
PAE
2.3 Mbit
Dual Port
Memory
Active Q
Flags
FF
PAF
PAE
SI
SO
SCLK
General Flag
Monitor
Serial
Multi-Queue
Programming
ESTR
ESYNC
EXI
SENI
SENO
EXO
Read Pointers
FM
IW
OW
BM
8
Reset
Logic
RDADD
RADEN
NULL-Q
Read Control
Logic
MAST
PKT
REN
RCLK
ID0
ID1
ID2
DF
Device ID
3 Bit
OUTPUT
MUX
PAE/ PAF
2
Offset
Q
Q
= REOP
= RSOP
DFM
35
34
OUTPUT
REGISTER
EREN
PRS
MRS
ERCLK
5998 drw02
IOSEL
Vref
IO Level Control
&
Power Down
OE
Q
- Q
0
35
PD
Q
x9, x18, x36
out
Figure 1. Multi-Queue Block Diagram
3
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648 and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINCONFIGURATION
A1 BALL PAD CORNER
A
D14
D15
D17
D20
D23
D26
D29
D32
GND
PD
D13
D16
D12
D11
D19
D22
D25
D28
D31
D34
D35
VREF
D10
D9
D7
D6
D5
D4
D3
D2
D1
TCK
TMS
TDO
TDI
ID1
ID0
Q0
Q3
Q2
Q6
Q5
Q4
Q9
Q8
Q12
Q11
Q10
Q16
Q24
Q14
Q13
Q17
Q21
Q23
Q15
Q19
B
C
D
E
F
D0
TRST
D18
D8
IOSEL
VDD
ID2
Q1
Q7
Q18
Q20
Q22
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDQ
D21
VDDQ VDDQ
VDD
VDD
VDD
GND
VDD
VDD
VDDQ
VDD
GND
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDD
GND
D24
VDDQ
VDD
GND
GND
D27
GND
GND
GND
VDD
Q27
Q30
Q26
Q29
Q25
Q28
G
H
J
D30
VDD
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GND
GND
VDD
VDD
GND
GND
VDD
D33
GND
GND
VDD
Q33
PKT
GND
Q32
Q35
Q31
Q34
FM
NULL-Q
GND
K
L
MAST
SI
DFM
DF
SO
VDD
VDD
BM
IW
OW
M
N
P
R
SENO
SENI
OE
VDDQ
VDDQ
VDDQ
RDADD0 RDADD1
PRELIMINARY
WRADD1 WRADD0
SCLK
VDDQ
VDDQ VDDQ
VDD
PAF7
PAF4
WCLK
7
VDD
VDD
VDD
VDDQ
PAE7
EREN
REN
VDDQ
PAE6
PAE5
PAE4
VDDQ RDADD2 RDADD3 RDADD4
WRADD4 WRADD3 WRADD2 WADEN
RDADD5 RDADD6 RDADD7
FF
OV
PAE
PAF3
PAF2
PAF1
5
PAF6
PAF5
WEN
PAE3
WRADD6 WRADD5 FSYNC
FSTR
PAF0
4
ESTR
ESYNC
EXI
PAF
PR
ERCLK
PAE2
PAE1
13
RADEN
T
WRADD7
FXI
FXO
RCLK
PAE0
EXO
PRS
MRS
1
2
3
6
8
9
10
11
12
14
15
16
5998 drw03
PBGA (BB256-1, order code: BB)
TOP VIEW
NOTE:
1. DNC - Do Not Connect.
4
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
arespectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus
for that queue. Conversely, the read port has an output valid flag, providing
statusofthedatabeingreadfromthequeueselectedonthereadport.Aswell
astheoutputvalidflagthedeviceprovidesadedicatedalmostemptyflag.This
almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.
Thedeviceprovides auserprogrammablealmostemptyflagforall32FIFO
queuesandwhenarespectivequeueisselectedonthereadport,thealmost
emptyflagprovidesstatusforthatqueue.
DETAILEDDESCRIPTION
MULTI-QUEUE STRUCTURE
TheIDTMulti-QueueFIFOhasasingledatainputportandsingledataoutput
portwithupto32FIFOqueuesinparallelbufferingbetweenthetwoports.The
user can setup between 1 and 32 FIFO Queues within the device. These
queuescanbeconfiguredtoutilizethetotalavailablememory,providingtheuser
with full flexibility and ability to configure the queues to be various depths,
independentofoneanother.
PROGRAMMABLE FLAG BUSSES
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost
fullflagstatusbusisprovided,thisbusis8bitswide.Also,analmostemptyflag
statusbusisprovided,againthisbusis8bitswide.Thepurposeoftheseflag
bussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels
within FIFO queues that may not be selected on the write or read port. As
mentioned,thedeviceprovidesalmostfullandalmostemptyregisters(program-
mable by the user) for each of the 32 FIFO queues in the device.
IntheIDT72T51546/72T51556Multi-QueueFIFOdevicetheuserhasthe
optionofutilizinganywhere between1and32FIFOqueues, therefore the 8
bitflagstatusbussesaremultiplexedbetweenthe32queues,aflagbuscanonly
provide status for 8 of the 32 queues at any moment, this is referred to as a
“Quadrant”,suchthatwhenthebusisprovidingstatusofqueues1through8,
thisisquadrant1,whenitisqueues9through16,thisisquadrant2andsoon
uptoquadrant4.Iflessthan32queuesaresetupinthedevice,therearestill
4quadrants,suchthatin“Polled”modeofoperationtheflagbuswillstillcycle
through4quadrants.Ifforexampleonly22 queuesaresetup,quadrants1and
2 will reflect status of queues 1 through 8 and 9 through 16 respectively.
Quadrant3willreflectthestatusofqueues17through22ontheleastsignificant
6bits,themostsignificant2bitsoftheflagbusaredon’tcareandthe4thquadrant
outputswillbedon’tcarealso.
MEMORYORGANIZATION/ALLOCATION
Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing
256x36bits.Whentheuserisconfiguringthenumberofqueuesandindividual
queuesizestheusermustallocatethememorytorespectivequeues,inunits
ofblocks,thatis,asinglequeuecanbemadeupfrom0tomblocks,wherem
isthetotalnumberofblocksavailablewithinadevice.Alsothetotalsizeofany
given queue must be in increments of 256 x36. For the IDT72T51546 and
IDT72T51556theTotalAvailableMemoryis128and256blocksrespectively
(a blockbeing256x36). Queues canbe builtfromthese blocks tomake any
size queue desired and any number of queues desired.
BUS WIDTHS
TheinputportiscommontoallFIFOqueueswithinthedevice,asistheoutput
port.ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinput
portandoutputportcanbeeitherx9,x18orx36bitswideprovidedthatatleast
one of the ports is x36 bits wide, the read and write port widths being set
independentlyofoneanother.Becausetheportsarecommontoallqueuesthe
widthofthequeuesisnotindividuallyset,sothattheinputwidthofallqueues
are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
The flag busses are available in two user selectable modes of operation,
“Polled”or“Direct”.Whenoperatinginpolledmodeaflagbusprovidesstatus
ofeachquadrantsequentially,thatis,oneachrisingedgeofaclocktheflagbus
isupdatedtoshowthestatusofeachquadrantinorder.Therisingedgeofthe
writeclockwillupdatethealmostfullbusandarisingedgeonthereadclockwill
updatethealmostemptybus.Themodeofoperationisalwaysthesameforboth
thealmostfullandalmostemptyflagbusses.Whenoperatingindirectmode,the
quadrantontheflagbusisselectedbytheuser.Sotheusercanactuallyaddress
thequadranttobeplacedontheflagstatusbusses,theseflagbussesoperate
independentlyofoneanother.Addressingofthealmostfullflagbusisdonevia
thewriteportandaddressingofthealmostemptyflagbusisdoneviatheread
port.
Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete
FIFOqueueviathewritequeueselectaddressinputs.Conversely,databeing
readfromthedevicereadportisreadfromaqueueselectedviathereadqueue
selectaddressinputs.Datacanbesimultaneouslywrittenintoandreadfromthe
sameFIFOqueueordifferentFIFOqueues.Onceaqueueisselectedfordata
writes or reads, the writing and reading operation is performed in the same
manner as a conventional IDT synchronous FIFO’s, utilizing clocks and
enables,thereisasingleclockandenableperport.Whenaspecificqueueis
addressedonthewriteport,dataplacedonthedatainputsiswrittentothatqueue
sequentiallybasedontherisingedgeofawriteclockprovidedsetupandhold
timesaremet.Conversely,dataisreadontotheoutputportafteranaccesstime
from a rising edge on a read clock.
Theoperationofthewriteportiscomparabletothefunctionofaconventional
FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput
provides status of the selected queue. The operation of the read port is
comparabletothefunctionofaconventionalFIFOoperatinginFWFTmode.
WhenaFIFOqueueisselectedontheoutputport,thenextwordinthatqueue
willautomaticallyfallthroughtotheoutputregister.Allsubsequentwordsfrom
thatqueuerequireanenabledreadcycle.Datacannotbereadfromaselected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
whendata readoutis valid. Ifthe userswitches toa queue thatis empty, the
lastwordfromtheprevious queuewillremainontheoutputregister.
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost
fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice
providesauserprogrammablealmostfullflagforall32FIFOqueuesandwhen
PACKETREADY
The36bitMulti-QueueFIFOalsooffersa”PacketReady”modeofoperation,
thisisuserselectableandrequiresthatthedevicebeconfiguredwithbothwrite
and read ports as 36 bits wide. The packet mode of operation provides
monitoringof“usermarked”locations,whentheuseriswritingdataintoaFIFO
queueawordbeingwrittenincanbemarkedasa“StartofPacket”or“Endof
Packet”. Internally as words are being written into the device with markers
attached,thedevicemonitorsthesemarkersandprovidesapacketreadystatus
flag,whichindicateswhenatleastonefullpacketisavailableinaqueue.The
readportthereforeincludesanadditionalstatusflag,“PacketReady”,thisflag
providingpacketreadystatusforthequeuecurrentlyselectedonthereadport
forreadoperations,indicatingwhenatleastone(ormore)packetsofdataare
availabletoberead.Wheninpacketreadymodethealmostemptyflagstatus
busnolongerprovidesalmostemptystatusforindividualquadrants,butinstead
5
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648 and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
providespacketreadyflagstatusforindividualquadrants.(Apacketisregarded memoryblockswithinaMulti-Queuedevicecanbeallocatedtoincreasethe
as anynumberofwords writtenbetweena startofpacketandendofpacket depth of a queue. For example, depth expansion of 8 devices provides the
marker,packetsizesareuserdefinedandsizesarenotcontrolledorlimitedby possibilityof8queuesof64Kx36deep,eachqueuebeingsetupwithinasingle
thedevice).
deviceutilizingallmemoryblocksavailabletoproduceasinglequeue.Thisis
thedeepestFIFOqueuethatcansetupwithinadevice.
EXPANSION
Forqueue expansiona maximumnumberof256(8x32)queues maybe
ExpansionofMulti-Queuedevicesisalsopossible,upto8devicescanbe setup, each queue being 2K x36 deep, if less queues are setup, then more
connectedinaparallelfashionprovidingthepossibilityofbothdepthexpansion memory blocks will be available to increase queue depths if desired. When
or queue expansion. Depth Expansion means expanding the depths of connectingMulti-Queuedevicesinexpansionmodeallrespectiveinputpins
individual queues. Queue expansion means increasing the total number of (data&control)andoutputpins(data& flags),shouldbe“connected”together
queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore betweenindividualdevices.
6
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS
Symbol
Name
I/OTYPE
Description
BM
BusMatching
LVTTL
INPUT
ThispinissetupbeforeMasterResetandmustnottoggleduringanydeviceoperation.Thispinisused
alongwithIWandOWtosetupthe FIFObus width. Please refertoTable 3fordetails.
D[35:0]
Din
DataInputBus
LVTTL
INPUT
These are the 36data inputpins. Data is writtenintothe device via these inputpins onthe risingedge
ofWCLKprovidedthatWENisLOW.Note,thatinPacketReadymodeD32-D35maybeusedaspacket
markers,pleaseseepacketreadyfunctionaldiscussionformoredetail.Duetobusmatchingnotallinputs
maybe used, anyunusedinputs shouldbe tiedLOW.
DF(1)
DefaultFlag
DefaultMode
LVTTL
INPUT
IftheuserrequiresdefaultprogrammingoftheMulti-Queuedevice,thispinmustbesetupbeforeMaster
Resetandmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
(1)
DFM
LVTTL
INPUT
TheMulti-Queuedevicerequiresprogrammingaftermasterreset.Theusercandothisseriallyviathe
serialport,ortheusercanusethedefaultmethod.IfDFMisLOWatmasterresetthenserialmodewillbe
selected,ifHIGHthendefaultmodeisselected.
ERCLK
EREN
ESTR
RCLK Echo
HSTL-LVTTL ReadClockEchooutput,thisoutputgeneratesaclockbasedonthereadclockinput,thisisusedforSource
OUTPUT SynchronousclockingwherethereceivingdevicesutilizestheERCLKtoclockdataoutputfromtheFIFO.
REN Echo
HSTL-LVTTL ReadEnableEchooutput,canbeusedinconjunctionwiththeERCLKoutputtoloaddataoutputfromthe
OUTPUT FIFOintothe receivingdevice.
PAEn Flag Bus
Strobe
LVTTL
INPUT
IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK
andtheRDADDbustoselectaquadrantofqueuestobeplacedontothe PAEnbusoutputs.Aquadrant
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polledoperationshasbeenselected,ESTRshouldbetiedinactive,LOW.
ESYNC
PAEnBus Sync
LVTTL
ESYNCisanoutputfromtheMulti-QueuedevicethatprovidesasynchronizingpulseforthePAEnbus
OUTPUT duringPolledoperationofthePAEnbus.DuringPolledoperationeachquadrantofqueuestatusflagsis
loadedontothe PAEnbus outputs sequentiallybasedonRCLK. The firstRCLKrisingedge loads
quadrant1ontoPAEn,thesecondRCLKrisingedgeloadsquadrant2andsoon.ThefifthRCLKrising
edge will again load quadrant 1. During the RCLK cycle that quadrant 1 of a selected device is placed
ontothePAEnbus,theESYNCoutputwillbeHIGH.Forallotherquadrantsofthatdevice,theESYNC
outputwillbeLOW.
EXI
PAEnBus
ExpansionIn
LVTTL
INPUT
The EXIinputis usedwhenMulti-Queue devices are connectedinexpansionmode andPolledPAEn
bus operationhas beenselected. EXIofdevice ‘N’connects directlytoEXOofdevice ‘N-1’. The EXI
receivesatokenfromthepreviousdeviceinachain.InsingledevicemodetheEXIinputshouldbetied
LOWifthePAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheEXIinput
shouldbeconnectedtotheEXOoutputofthesamedevice.InexpansionmodetheEXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
EXO
PAEnBus
ExpansionOut
LVTTL
EXOisanoutputthatisusedwhenMulti-QueuedevicesareconnectedinexpansionmodeandPolled
OUTPUT PAEnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.This
pinpulses whendevice Nhas placedits final(4th)quadrantontothePAEnbus withrespecttoRCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising
edgethefirstquadrantofdeviceN+1willbeloadedontothePAEnbus.Thiscontinuesthroughthechain
andEXOofthelastdeviceisthenloopedbacktoEXIofthefirstdevice.TheESYNCoutputofeachdevice
inthechainprovides synchronizationtotheuserofthis loopingevent.
FF
Full Flag
LVTTL
This pinprovides thefullflagoutputfortheactiveFIFOqueue,thatis,thequeueselectedontheinput
OUTPUT portforwrite operations, (selectedvia WCLK, WRADDbus andWADEN). Onthe WCLKcycle aftera
queueselection,thisflagwillshowthestatusofthenewlyselectedqueue.Datacanbewrittentothisqueue
onthenextcycleprovidedFFisHIGH.ThisflaghasHigh-Impedancecapability,thisisimportantduring
expansionofdevices,whentheFFflagoutputofupto8devicesmaybeconnectedtogetheronacommon
line.ThedevicewithaqueueselectedtakescontroloftheFFbus,allotherdevicesplacetheirFFoutput
intoHigh-Impedance.Whenaqueueselectionismadeonthewriteportthisoutputwillswitchfrom
High-ImpedancecontrolonthenextWCLKcycle.ThisflagissynchronizedtoWCLK.
(1)
FM
Flag Mode
LVTTL
INPUT
Thispinissetupbeforeamasterresetandmustnottoggleduringanydeviceoperation.Thestateofthe
FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbussesoperateineitherPolled
orDirectmode.Ifthis pinis HIGHthemodeis Polled,ifLOWthenitwillbeDirect.
7
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648 and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
FSTR
PAFn Flag Bus
Strobe
LVTTL
INPUT
IfdirectoperationofthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK
andtheWRADDbustoselectaquadrantofqueuestobeplacedontothePAFnbusoutputs.Aquadrant
addressedviatheWRADDbus is selectedontherisingedgeofWCLKprovidedthatFSTRis HIGH.If
Polledoperationshasbeenselected,FSTRshouldbetiedinactive,LOW.
FSYNC
PAFn Bus Sync
LVTTL
FSYNCisanoutputfromtheMulti-QueuedevicethatprovidesasynchronizingpulseforthePAFnbus
OUTPUT duringPolledoperationofthePAFnbus.DuringPolledoperationeachquadrantofqueuestatusflags
is loadedontothePAFnbus outputs sequentiallybasedonWCLK.ThefirstWCLKrisingedgeloads
quadrant1ontoPAFn,thesecondWCLKrisingedgeloadsquadrant2andsoon.ThefifthWCLKrising
edgewillagainloadquadrant1.DuringtheWCLKcyclethatquadrant1ofaselecteddeviceis placed
ontothePAFnbus,theFSYNCoutputwillbeHIGH.Forallotherquadrantsofthatdevice,theFSYNC
outputwillbeLOW.
FXI
PAFnBus
ExpansionIn
LVTTL
INPUT
The FXIinputis usedwhenMulti-Queue devices are connectedinexpansionmode andPolled PAFn
bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receivesatokenfromthepreviousdeviceinachain.InsingledevicemodetheFXIinputshouldbetied
LOWifthePAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheFXIinput
shouldbeconnectedtotheFXOoutputofthesamedevice.InexpansionmodetheFXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
FXO
PAFnBus
ExpansionOut
LVTTL
FXOisanoutputthatisusedwhenMulti-QueuedevicesareconnectedinexpansionmodeandPolled
OUTPUT PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This
pinpulseswhendeviceNhasplaceditsfinal(4th)quadrantontothePAFnbuswithrespecttoWCLK.
This pulse (token)is thenpassedontothe nextdevice inthe chain‘N+1’andonthe nextWCLKrising
edgethefirstquadrantofdeviceN+1willbeloadedontothePAFnbus.Thiscontinuesthroughthechain
andFXOofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdevice
inthechainprovides synchronizationtotheuserofthis loopingevent.
(1)
ID[2:0]
Device ID Pins
LVTTL
INPUT
Forthe32QMulti-QueuedevicetheWRADDandRDADDaddressbussesare8bitswide.Whenaqueue
selectiontakesplacethe3MSB’softhis8bitaddressbusareusedtoaddressthespecificdevice(the
5LSB’s are usedtoaddress the queue withinthatdevice). Duringwrite/readoperations the 3MSB’s
oftheaddressarecomparedtothedeviceIDpins.ThefirstdeviceinachainofMulti-Queue’s(connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which
is‘111’,howevertheIDdoesnothavetomatchthedeviceorder.Insingledevicemodethesepinsshould
besetupas‘000’andthe3MSB’softheWRADDandRDADDaddressbussesshouldbetiedLOW.The
ID[2:0]inputs setupa respective devices IDduring masterreset.TheseIDpinsmustnottoggleduring
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
IOSEL
IOSelect
LVTTL
INPUT
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
required then IOSEL should be tied LOW. If LVTTL I/O are required then it should be tied HIGH.
(1)
IW
InputWidth
MasterDevice
LVTTL
INPUT
ThispinisusedinconjunctionwithOWandBMtosetuptheinputandoutputbuswidthstobeacombination
of x9, x18 or x36, (providing that one port is x36).
(1)
MAST
LVTTL
INPUT
ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe
Masterdevice ora Slave. Ifthis pinis HIGH, the device is the masterifitis LOWthenitis a Slave. The
masterdeviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgotoHigh-
Impedance,preventingbuscontention.IfaMulti-Queuedeviceisbeingusedinsingledevicemode,this
pinmustbesetHIGH.
MRS
MasterReset
LVTTL
INPUT
AmasterresetisperformedbytakingMRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired
aftermasterreset.
NULL-Q
OE
NullQueueSelect HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD
INPUT
address bus toaddress the Null-Q.
OutputEnable
LVTTL
INPUT
TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontroloftheMulti-Queue
dataoutputbus,Qout.Ifadevicehasbeenconfiguredasa“Master”device,theQoutdataoutputswillbe
inaLowImpedanceconditioniftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbein
HighImpedance.Ifadeviceisconfigureda“Slave”device,thentheQoutdataoutputswillalwaysbein
HighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpointOEprovidesthree-
stateofthatrespectivedevice.
8
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol
OV
Name
I/OTYPE
Description
OutputValidFlag
LVTTL ThisoutputflagprovidesoutputvalidstatusforthedatawordpresentontheMulti-QueueFIFOdataoutput
OUTPUT port,Qout.Thisflagistherefore,2-stagedelayedtomatchthedataoutputpathdelay.Thatis,thereis
a2RCLKcycledelayfromthetimeagivenqueueisselectedforreads,tothetimetheOVflagrepresents
thedatainthatrespectivequeue.Whenaselectedqueueonthereadportisreadtoempty,theOVflag
willgoHIGH,indicatingthatdataontheoutputbus is notvalid.The OVflagalsohas High-Impedance
capability,requiredwhenmultipledevices areusedandtheOVflags aretiedtogether.
(1)
OW
OutputWidth
LVTTL ThispinissetupduringMasterResetandmustnottoggleduringanydeviceoperation.Thispinisused
INPUT inconjunctionwithIWandBMtosetupthedatainputandoutputbuswidthstobeacombinationofx9,
x18 or x36, (providing that one port is x36).
PAE
Programmable
Almost-EmptyFlag
LVTTL ThispinprovidestheAlmost-EmptyflagstatusfortheFIFOqueuethathasbeenselectedontheoutput
OUTPUT portforreadoperations,(selectedviaRCLK,RDADDandRADEN).ThispinisLOWwhentheselected
FIFOqueuealmost-empty.This flagoutputmaybeduplicatedononeofthe PAEnbus lines.This flag
is synchronizedtoRCLK.
PAEn/PRn Programmable
Almost-EmptyFlag
Bus/PacketReady
FlagBus
LVTTL Onthe32Qdevicethe PAEn/PRnbus is 8bits wide.DuringaMasterResetthis bus is setupforeither
OUTPUT AlmostEmptymodeorPacketReadymode.AtanyonetimethisoutputbusprovidesPAE/PRnstatus
of8queues(1quadrant),withinaselecteddevice,havingatotalof4quadrants.DuringFIFOread/write
operationstheseoutputsprovideprogrammableemptyflagstatusorpacketreadystatus,ineitherdirect
orpolledmode.ThemodeofflagoperationisdeterminedduringmasterresetviathestateoftheFMinput.
ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansionofMulti-Queuedevices.
DuringdirectoperationthePAEn/PRnbusisupdatedtoshowthePAE/PRstatusofaquadrantofqueues
withina selecteddevice. Selectionis made usingRCLK, ESTRandRDADD. DuringPolledoperation
thePAEn/PRnbusisloadedwiththePAE/PRnstatusofMulti-QueueFIFOquadrantssequentiallybased
ontherisingedgeofRCLK.PAEorPRoperationisdeterminedbythestateofPKTduringmasterreset.
PAF
Programmable
Almost-FullFlag
LVTTL ThispinprovidestheAlmost-FullflagstatusfortheFIFOqueuethathasbeenselectedontheinput
OUTPUT portforwriteoperations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselected
FIFOqueueisalmost-full.Thisflagoutputmaybeduplicatedononeofthe PAFnbuslines.Thisflagis
synchronizedtoWCLK.
PAFn
Programmable
LVTTL Onthe 32Qdevice the PAFnbus is 8bits wide. Atanyone time this outputbus provides PAFstatus of
Almost-FullFlagBus OUTPUT 8queues (1quadrant),withinaselecteddevice,havingatotalof4quadrants.DuringFIFOread/write
operationstheseoutputsprovideprogrammablefullflagstatus,ineitherdirectorpolledmode.Themode
offlagoperationisdeterminedduringmasterresetviathestateoftheFMinput.Thisflagbusiscapable
ofHigh-Impedancestate,thisisimportantduringexpansionofMulti-Queuedevices.Duringdirect
operationthePAFnbusisupdatedtoshowthePAFstatusofaquadrantofqueueswithinaselecteddevice.
SelectionismadeusingWCLK,FSTR,WRADDandWADEN.DuringPolledoperationthePAFnbusis
loadedwiththePAFstatusofMulti-QueueFIFOquadrantssequentiallybasedontherisingedgeofWCLK.
PD
Power Down
HSTL This inputis usedtoprovide additionalpowersavings. Whenthe device I/Ois setupforHSTL/eHSTL
INPUT modeaHIGHonthePDinputdisablesthedatainputsonthewriteportonly,providingsignificantpower
savings. In LVTTL mode this pin has no operation
(1)
PKT
PacketMode
LVTTL ThestateofthispinduringaMasterResetwilldeterminewhetherthepartisoperatinginPacketReady
INPUT modeprovidingbothaPacketReady(PR)outputandaProgrammableAlmostEmpty(PAE)discrete
output,orstandardmode,providinga(PAE)outputonly.IfthispinisHIGHduringMasterResetthepart
willoperateinpacketreadymode,ifitisLOWthenalmostemptymode.Ifpacketmodehasbeenselected
the readportflagbus becomes packetreadyflagbus, PRnandthe discrete packetreadyflag, PRis
functional.Ifalmostemptyoperationhasbeenselectedthentheflagbusprovidesalmostemptystatus,PAEn
andthediscretealmostemptyflag,PAEisfunctional,thePRflagisinactiveandshouldnotbeconnected.
PacketReadyutilizesusermarkedlocationstoidentifystartandendofpacketsbeingwrittenintothedevice.
PacketModecanonlybeselectedifboththeinputportwidthandoutputportwidthare36bits.
PR
PacketReadyFlag
LVTTL IfpacketreadymodehasbeenselectedthisflagoutputprovidesPacketReadystatusoftheFIFOqueue
OUTPUT selectedforreadoperations.DuringamasterresetthestateofthePKTinputdetermineswhetherPacket
modeofoperationwillbeused.IfPacketmodeisselected,thenthePRflagbecomesavalidoutput,from
whichtheusercandetermineifaselectedFIFOqueuehasa“complete”packetofdataavailableforreading.
Theusermustmarkthestartofapacketandtheendofapacketwhenwritingdataintoaqueue.Using
9
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648 and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
PR
(Continued)
PacketReadyFlag
LVTTL theseStartOfPacket(SOP)andEndOfPacket(EOP)markers,theMulti-Queuedevicesets PRLOW
OUTPUT ifone ormore “complete”packets are available inthe queue.
PRS
PartialReset
LVTTL APartialResetcanbeperformedonasinglequeueselectedwithintheMulti-Queuedevice.BeforeaPartial
INPUT Resetcanbe performedona queue, thatqueue mustbe selectedonboththe write portandreadport
2clockcycles beforetheresetis performed.APartialResetis thenperformedbytakingPRSLOWfor
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
thefirstmemorylocation,noneofthedevicesconfigurationwillbechanged.
Q[35:0]
Qout
DataOutputBus
LVTTL Thesearethe36dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge
OUTPUT ofRCLKprovidedthatRENisLOW,OEisLOWandtheFIFOqueueisselected.Note,thatinPacketReady
modeQ32-Q35maybeusedaspacketmarkers,pleaseseepacketreadyfunctionaldiscussionformore
detail.Duetobusmatchingnotalloutputsmaybeused,anyunusedoutputsshouldnotbeconnected.
RADEN
RCLK
ReadAddress Enable LVTTL The RADENinputis usedinconjunctionwithRCLKandthe RDADDaddress bus toselecta queue to
INPUT be read from. A FIFO queue addressed via the RDADD bus is selected on the rising edge of RCLK
provided that RADEN is HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR.
ReadClock
LVTTL WhenenabledbyREN,therisingedgeofRCLKreadsdatafromtheselectedFIFOqueueviatheoutput
INPUT busQout.TheFIFOqueuetobereadisselectedviatheRDADDaddressbusandarisingedgeofRCLK
whileRADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthe
PAEn/PRnflagquadranttobeplacedonthePAEn/PRnbusduringdirectflagoperation.Duringpolled
flagoperationthePAEn/PRnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronized
toRCLK.ThePAE,PRandOVoutputsareallsynchronizedtoRCLK.DuringdeviceexpansiontheEXO
and EXI signals are based on RCLK. RCLK must be continuous and free-running.
RDADD Read Address Bus
[7:0]
LVTTL For the 32Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The
INPUT firstfunctionofRDADDistoselectaFIFOqueuetobereadfrom.Theleastsignificant5bitsofthebus,
RDADD[4:0]areusedtoaddress1of32possiblequeueswithinaMulti-Queuedevice.Themostsignificant
3bits, RDADD[7:5]are usedtoselect1of8possible Multi-Queue devices thatmaybe connectedin
expansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent
ontheRDADDbuswillbeselectedonarisingedgeofRCLKprovidedthatRADENisHIGH,(note,that
datacanbeplacedontotheQoutbus,readfromthepreviouslyselectedFIFOqueueonthisRCLKedge).
On the next rising RCLK edge after a read queue select, a data word from the previous queue will be
placedontotheoutputs,Qout,regardlessoftheRENinput.TwoRCLKrisingedgesafterreadqueueselect,
datawillbeplacedontotheQoutoutputsfromthenewlyselectedqueue,regardlessofRENduetothe
firstwordfallthrougheffect.
ThesecondfunctionoftheRDADDbusistoselectthequadrantofFIFOqueuestobeloadedontothe
PAEn/PRnbusduringstrobedflagmode.Theleastsignificant2bits,RDADD[1:0]areusedtoselectthe
quadrantofadevicetobeplacedonthePAEnbus.Themostsignificant3bits,RDADD[7:5]areagain
usedtoselect1of8possibleMulti-Queuedevicesthatmaybeconnectedinexpansionmode.Address
bitsRDADD[4:2]aredon’tcareduringquadrantselection.ThequadrantaddresspresentontheRDADD
buswillbeselectedontherisingedgeofRCLKprovidedthatESTRisHIGH,(note,thatdatacanbeplaced
ontotheQoutbus,readfromthepreviouslyselectedFIFOQonthisRCLKedge).PleaserefertoTable2
for details on RDADD bus.
REN
ReadEnable
LVTTL The RENinputenables readoperations fromaselectedFIFOqueuebasedonarisingedgeofRCLK.
INPUT Aqueue tobe readfromcanbe selectedvia RCLK, RADENandthe RDADDaddress bus regardless
ofthestateofREN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond
RCLKcycle afterqueue selectionregardless ofRENdue tothe FWFToperation. Areadenable is not
requiredtocyclethePAEn/PRnbus(inpolledmode)ortoselectthePAEnquadrant,(indirectmode).
SCLK
SerialClock
LVTTL IfserialprogrammingoftheMulti-Queuedevicehasbeenselectedduringmasterreset,theSCLKinput
INPUT clockstheserialdatathroughtheMulti-Queuedevice.DatasetupontheSIinputisloadedintothedevice
ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed
theSCLKofalldevices shouldbeconnectedtothesamesource.
SENI
SerialInputEnable
LVTTL DuringserialprogrammingofaMulti-Queuedevice,dataloadedontotheSIinputwillbeclockedintothe
INPUT part(via a risingedge ofSCLK), providedthe SENIinputofthatdevice is LOW. Ifmultiple devices are
cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
10
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
SENI
(Continued)
SerialInputEnable
LVTTL loadingofagivendeviceiscomplete,itsSENOoutputgoesLOW,allowingthenextdeviceinthechain
INPUT tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.
SENO
SerialOutputEnable LVTTL ThisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingoftheMulti-Queuedevice
OUTPUT hasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO
willgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENOwillalso
goHIGH.WhentheSENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.
Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENOoutputshould
beconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogrammingofthefirstdevice
iscomplete,SENOwillgoLOW,therebytakingtheSENIinputofthenextdeviceLOWandsoonthroughout
thechain.WhenagivendeviceinthechainisfullyprogrammedtheSENOoutputessentiallyfollowsthe
SENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.Whenthisoutputgoes
LOW,serialloadingofalldeviceshasbeencompleted.
SI
SerialIn
LVTTL DuringserialprogrammingthispinisloadedwiththeserialdatathatwillconfiguretheMulti-Queuedevices.
INPUT Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO
hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connectstotheSIpinofthesecondandsoon.TheMulti-Queuedevicesetupregistersareshiftregisters.
SO
SerialOut
LVTTL Thisoutputisusedinexpansionmodeandallowsserialdatatobepassedthroughdevicesinthechain
OUTPUT tocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdeviceinthe
chain. The SOofthe finaldevice ina chainshouldnotbe connected.
TCK
TDI
JTAGClock
LVTTL ClockinputforJTAGfunction. TMSandTDIare sampledonthe risingedge ofTCK. TDOis outputon
INPUT thefallingedgeofTCK.
TestDataInput
TestDataOutput
LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK.
INPUT This is alsothedatafortheInstructionRegister,JTAGIDRegisterandBypass Register.
TDO
LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK.
INPUT ThisoutputisinHigh-ImpedanceexceptwhenshiftingdatawhileinSHIFT-DRandSHIFT-IRcontroller
states.
TMS
JTAGModeSelect
JTAGReset
LVTTL TMSis a serialinputpin. Bits are seriallyloadedonthe risingedge ofTCK, whichselects 1of5modes
INPUT ofoperationforthe JTAGboundaryscan.
TRST
LVTTL TRSTistheasynchronousresetpinfortheJTAGcontroller.IftheJTAGportisnot utilized,TRSTshould
INPUT be tiedtoGND.
WADEN WriteAddressEnable LVTTL TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto
INPUT be written in to. A FIFO queue addressed via the WRADD bus is selected on the rising edge of WCLK
providedthatWADENis HIGH. WADENcannotbe HIGHforthe same WCLKcycle as FSTR.
WCLK
WriteClock
LVTTL WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheselectedFIFOqueueviatheinput
INPUT bus, Din. The FIFO queue to be written to is selected via the WRADD address bus and a rising edge
ofWCLKwhileWADENisHIGH.ArisingedgeofWCLKinconjunctionwithFSTRandWRADDwillalso
selectthe flagquadranttobe placedonthe PAFnbus duringdirectflagoperation. Duringpolledflag
operationthePAFnbusiscycledwithrespecttoWCLKandtheFSYNCsignalissynchronizedtoWCLK.
The PAFn, PAFandFF outputs are allsynchronizedtoWCLK. Duringdevice expansionthe FXOand
FXIsignals are basedonWCLK. The WCLKmustbe continuous andfree-running.
WEN
WriteEnable
LVTTL The WEN input enables write operations to a selected FIFO queue based on a rising edge of WCLK.
INPUT AqueuetobewrittentocanbeselectedviaWCLK,WADENandtheWRADDaddress bus regardless
ofthestateofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLK
cycleafterqueueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFn
bus (in polled mode) or to select the PAFn quadrant , (in direct mode).
WRADD WriteAddressBus
[7:0]
LVTTL Forthe32QdevicetheWRADDbusis8bits.TheWRADDbusisadualpurposeaddressbus.Thefirst
INPUT functionofWRADDistoselectaFIFOqueuetobewrittento.Theleastsignificant5bitsofthebus,
WRADD[4:0]areusedtoaddress1of32possiblequeueswithinaMulti-Queuedevice.Themostsignificant
3bits,WRADD[7:5]areusedtoselect1of8possibleMulti-Queuedevices thatmaybeconnectedin
11
IDT72T51546/72T515562.5V,MULTI-QUEUEFIFO(32QUEUES)
36BITWIDECONFIGURATION1,179,648 and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
WRADD WriteAddressBus
[7:0]
(Continued)
LVTTL expansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent
INPUT ontheWRADDbuswillbeselectedonarisingedgeofWCLKprovidedthatWADENisHIGH,(note,that
datapresentontheDinbuscanbewrittenintothepreviouslyselectedFIFOqueueonthisWCLKedge
andonthenextrisingWCLKalso,providingthatWENisLOW).TwoWCLKrisingedgesafterwritequeue
select,datacanbewrittenintothenewlyselectedqueue.
ThesecondfunctionoftheWRADDbusistoselectthequadrantofFIFOqueuestobeloadedontothe
PAFnbusduringstrobedflagmode.Theleastsignificant2bits,WRADD[1:0]areusedtoselectthequadrant
ofadevicetobeplacedonthePAFnbus.Themostsignificant3bits,WRADD[7:5]areagainusedtoselect
1of8possibleMulti-Queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsWRADD[4:2]
aredon’tcareduringquadrantselection.ThequadrantaddresspresentontheWRADDbuswillbeselected
ontherisingedgeofWCLKprovidedthatFSTRisHIGH,(note,thatdatacanbewrittenintothepreviously
selectedFIFO queue on this WCLKedge). Please refertoTable 1 for details onthe WRADD bus.
VCC
+2.5VSupply
Power These are VCC power supply pins and must all be connected to a +2.5V supply rail.
VDDQ
O/PRailVoltage
Power Thesepinsmustbetiedtothedesiredoutputrailvoltage.ForLVTTLI/Othesepinsmustbeconnected
to+2.5V,forHSTLthesepinsmustbeconnectedto+1.5VandforeHSTLthesepinsmustbeconnected
to+1.8V.
GND
Vref
GroundPin
Power These are Ground pins and must all be connected to the GND supply rail.
ReferenceVoltage
HSTL ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable
INPUT "RecommendedDCOperatingConditions". The inputprovides the reference levelforHSTL/eHSTL
inputs. ForLVTTLI/Omode this inputshouldbe tiedtoGND.
NOTE:
1. Inputs should not change after Master Reset.
12
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BB
Plastic Ball Grid Array (PBGA, BB256-1)
5
6
7-5
Commercial Only
Commercial and Industrial
Commercial and Industrial
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Low Power
L
72T51546 1,179,648 bits 2.5V Multi-Queue FIFO
72T51556 2,359,296 bits 2.5V Multi-Queue FIFO
5998 drw37
NOTE:
1. Industrial temperature range products for 6ns and 7-5ns speed grades are available as a standard device. All other speed grades are available by special order.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
13
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