IDT72T51553L5BBI [IDT]
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION; 2.5V多队列流量控制的设备（ 32队列） 18位宽的配置
| 型号： | IDT72T51553L5BBI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| 文件： | 总57页 (文件大小：539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION
1,179,648 bits and 2,359,296 bits
IDT72T51543
IDT72T51553
•
•
•
Shows PAE and PAF status of 8 Queues
Direct or polled operation of flag status bus
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
– x18in to x18out
– x9in to x18out
FEATURES:
•
Choose from among the following memory density options:
IDT72T51543
IDT72T51553
Configurable from 1 to 32 Queues
Total Available Memory = 1,179,648 bits
Total Available Memory = 2,359,296 bits
•
•
•
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 512 x 18 or 1,024 x 9
Independent Read and Write access per queue
User programmable via serial port
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
Default multi-queue device configurations
– IDT72T51543 : 2,048 x 18 x 32Q
– x18in to x9out
– x9in to x9out
•
•
•
•
•
•
•
•
FWFT mode of operation on read port
Partial Reset, clears data in single Queue
Expansion of up to 8 multi-queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
– IDT72T51553 : 4,096 x 18 x 32Q
•
•
•
•
•
•
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
Individual, Active queue flags (OV, FF, PAE, PAF)
8 bit parallel flag status on both read and write ports
•
•
•
•
FUNCTIONALBLOCKDIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
RADEN
ESTR
Q0
WADEN
FSTR
RDADD
8
WRADD
REN
Q1
Q2
8
RCLK
WEN
EREN
WCLK
ERCLK
OE
Q
out
x9, x18
D
in
x9, x18
DATA IN
DATA OUT
OV
FF
PAF
PAFn
PAE
PAEn
Q31
8
8
5999 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc
NOVEMBER 2003
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5999/3
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Iftheuserdoesnotwishtoprogramthemulti-queuedevice,adefaultoptionis
availablethatconfiguresthedeviceinapredeterminedmanner.
BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster
Reset latches in all configuration setup pins and must be performed before
programmingofthedevicecantakeplace.APartialResetwillresetthereadand
writepointersofanindividualqueue,providedthatthequeueisselectedonboth
thewriteportandreadportatthetimeofpartialreset.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided.Theseareoutputs fromthereadportofthequeuethatarerequired
forhighspeeddatacommunication,toprovidetightersynchronizationbetween
thedatabeingtransmittedfromtheQnoutputsandthedatabeingreceivedby
theinputdevice.Datareadfromthereadportisavailableontheoutputbuswith
respecttoERENandERCLK,thisisveryusefulwhendataisbeingreadathigh
speed.
Themulti-queueflow-controldevicehasthecapabilityofoperatingitsIOin
either2.5VLVTTL,1.5VHSTLor1.8VeHSTLmode.ThetypeofIOisselected
viatheIOSELinput.Thecoresupplyvoltage(VCC)tothemulti-queueisalways
2.5V,howevertheoutputlevelscanbesetindependentlyviaaseparatesupply,
VDDQ.
ThedevicesalsoprovideadditionalpowersavingsviaaPowerDownInput.
This input disables the write port data inputs when no write operations are
required.
DESCRIPTION:
TheIDT72T51543/72T51553multi-queueflow-controldevicesaresingle
chipwithinwhichanywherebetween1and32discreteFIFOqueuescanbe
setup.Allqueueswithinthedevicehaveacommondatainputbus,(writeport)
andacommondataoutputbus,(readport).Datawrittenintothewriteportis
directed to a respective queue via an internal de-multiplex operation, ad-
dressedbytheuser.Datareadfromthereadportisaccessedfromarespective
queueviaaninternalmultiplexoperation,addressedbytheuser.Datawrites
andreadscanbeperformedathighspeedsupto200MHz,withaccesstimes
of3.6ns.Datawriteandreadoperationsaretotallyindependentofeachother,
aqueuemaybeselectedonthewriteportandadifferentqueueontheread
portorbothportsmayselectthesamequeuesimultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.
Two8bitprogrammableflagbussesareavailable,providingstatusofqueues
notselectedforwriteorreadoperations.When8orlessqueuesareconfigured
in the device these flag busses provide an individual flag per queue, when
morethan8queuesareused,eitheraPolledorDirectmodeofbusoperation
providestheflagbusseswithallqueuesstatus.
BusMatchingisavailableonthisdevice,eitherportcanbe9bitsor18bits
wide.WhenBusMatchingisusedthedeviceensuresthelogicaltransferof
datathroughputinaLittleEndianmanner.
Theuserhasfullflexibilityconfiguringqueueswithinthedevice,beingable
toprogramthetotalnumberofqueuesbetween1and32,theindividualqueue
depthsbeingindependentofeachother.Theprogrammableflagpositionsare
alsouserprogrammable.Allprogrammingisdoneviaadedicatedserialport.
AJTAGtestportisprovided,herethemulti-queuedevicehasafullyfunctional
BoundaryScanfeature,compliantwithIEEE1149.1StandardTestAccessPort
andBoundaryScanArchitecture.
SeeFigure1,Multi-QueueFlow-ControlDeviceBlockDiagramforanoutline
ofthefunctionalblockswithinthedevice.
2
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D
in
x9, x18
- D
D
0
17
WCLK
WEN
INPUT
DEMUX
TMS
8
WRADD
WADEN
Write Control
Logic
TDI
JTAG
Logic
TDO
TCK
TRST
Write Pointers
PAF
General Flag
Monitor
FSTR
PAFn
8
FSYNC
Upto 32
FIFO
Queues
FXO
FXI
OV
Active Q
Flags
PAE
2.3 Mbit
Dual Port
Memory
Active Q
Flags
FF
PAF
PAE
General Flag
Monitor
8
SI
SO
PAEn
Serial
ESTR
ESYNC
SCLK
Multi-Queue
Programming
SENI
EXI
SENO
EXO
Read Pointers
FM
IW
8
Reset
Logic
RDADD
Read Control
Logic
OW
RADEN
NULL-Q
MAST
REN
RCLK
ID0
ID1
ID2
DF
Device ID
3 Bit
OUTPUT
MUX
PAE/ PAF
Offset
DFM
OUTPUT
REGISTER
EREN
PRS
MRS
ERCLK
5999 drw02
IOSEL
Vref
IO Level Control
&
Power Down
OE
Q
- Q
17
0
PD
Q
x9, x18
out
Figure 1. Multi-Queue Flow-Control Device Block Diagram
3
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINCONFIGURATION
A1 BALL PAD CORNER
A
D14
D15
D17
D13
D16
GND
D12
D11
GND
D10
D9
Q9
Q8
Q7
Q15
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
FM
D7
D6
D5
D4
D3
D2
D1
D0
TCK
TMS
TDO
TDI
ID2
ID1
ID0
Q3
Q2
Q1
Q6
Q5
Q4
Q12
Q11
Q14
Q13
B
C
D
E
F
D8
TRST
IOSEL
Q0
Q10
Q16
DNC
Q17
DNC
DNC
VDDQ
VCC
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDQ
VDDQ
VCC
VCC
VDDQ
VDDQ
VCC
V
CC
GND
GND
GND
GND
GND
VCC
GND
GND
GND
GND
GND
GND
VCC
VDDQ
VDDQ
GND
GND
VDDQ
VCC
VDDQ
VCC
GND
VCC
VDDQ
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
DNC
DNC
DNC
DNC
DNC
MAST
G
H
J
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
PD
GND
NULL-Q
GND
GND
GND
VCC
DNC
GND
GND
GND
GND
GND
VCC
GND
GND
VCC
VCC
K
L
VREF
VCC
VCC
VCC
VCC
GND
ADVANCE
SI
VDDQ
GND
GND
GND
GND
VCC
DFM
DF
VCC
GND
VDDQ
IW
OW
GND
GND
M
N
P
R
T
SENO
SENI
OE
SO
VDDQ
VDDQ
VCC
VCC
GND
VCC
VDDQ
VDDQ
RDADD0 RDADD1
VCC
VDDQ
WRADD1 WRADD0 SCLK
RDADD2 RDADD3 RDADD4
RDADD5 RDADD6 RDADD7
VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
VCC
V
DDQ
V
DDQ
WRADD4 WRADD3 WRADD2 WADEN
FF
OV
PAF3
PAF6
PAF7
PAE
PAE6
PAE7
PAE3
INFORMATION
WRADD6 WRADD5 FSYNC
ESTR ESYNC
FSTR
PAF
EREN
REN
PAE2
PAE1
RADEN
PAF2
PAF5
PAE5
ERCLK
PAF4
DNC
EXO
EXI
WRADD7 FXI
FXO
WEN
PRS
MRS
RCLK
PAE4
PAE0
PAF0
PAF1
WCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
5999 drw03
NOTE:
1. DNC - Do Not Connect.
PBGA (BB256-1, order code: BB)
TOP VIEW
4
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice
provides a user programmable almost full flag for all 32 queues and when a
respectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus
for that queue. Conversely, the read port has an output valid flag, providing
statusofthedatabeingreadfromthequeueselectedonthereadport.Aswell
astheoutputvalidflagthedeviceprovidesadedicatedalmostemptyflag.This
almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.
Thedeviceprovidesauserprogrammablealmostemptyflagforall32queues
andwhenarespectivequeueisselectedonthereadport,thealmostemptyflag
providesstatusforthatqueue.
DETAILEDDESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
singledataoutputportwithupto32FIFOqueuesinparallelbufferingbetween
thetwoports.Theusercansetupbetween1and32queueswithinthedevice.
Thesequeuescanbeconfiguredtoutilizethetotalavailablememory,providing
theuserwithfullflexibilityandabilitytoconfigurethequeuestobevariousdepths,
independentofoneanother.
MEMORYORGANIZATION/ALLOCATION
Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing
512x18or1,024x9bits.Whentheuserisconfiguringthenumberofqueues
andindividualqueue sizes the usermustallocate the memorytorespective
queues,inunitsofblocks,thatis,asinglequeuecanbemadeupfrom0tom
blocks,wheremisthetotalnumberofblocksavailablewithinadevice.Alsothe
totalsize of anygiven queue mustbe in increments of 512 x 18or1,024 x 9.
Forthe IDT72T51543andIDT72T51553the TotalAvailable Memoryis 128
and256blocks respectively(a blockbeing512x18or1,024x9). Ifanyport
is configured for x18 bus width, a block size is 512 x 18. If both the write and
readports are configuredforx9bus width, a blocksize is 1,024x9. Queues
canbebuiltfromtheseblockstomakeanysizequeuedesiredandanynumber
ofqueuesdesired.
PROGRAMMABLE FLAG BUSSES
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost
fullflagstatusbusisprovided,thisbusis8bitswide.Also,analmostemptyflag
statusbusisprovided,againthisbusis8bitswide.Thepurposeoftheseflag
bussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels
withinqueuesthatmaynotbeselectedonthewriteorreadport.Asmentioned,
thedeviceprovidesalmostfullandalmostemptyregisters(programmableby
the user) for each of the 32 queues in the device.
IntheIDT72T51543/72T51553multi-queueflow-controldevicestheuser
has theoptionofutilizinganywherebetween1and32queues,thereforethe
8bitflagstatusbussesaremultiplexedbetweenthe32queues,aflagbuscan
onlyprovidestatusfor8ofthe32queuesatanymoment,thisisreferredtoas
a“Quadrant”,suchthatwhenthebusisprovidingstatusofqueues1through
8,thisisquadrant1,whenitisqueues9through16,thisisquadrant2andso
onuptoquadrant4. Ifless than32queues are setupinthe device, there are
still4quadrants,suchthatin“Polled”modeofoperationtheflagbuswillstillcycle
through4quadrants.Ifforexampleonly22 queuesaresetup,quadrants1and
2 will reflect status of queues 1 through 8 and 9 through 16 respectively.
Quadrant3willreflectthestatusofqueues17through22ontheleastsignificant
6bits,themostsignificant2bitsoftheflagbusaredon’tcareandthe4thquadrant
outputswillbedon’tcarealso.
BUS WIDTHS
Theinputportiscommontoallqueueswithinthedevice,asistheoutputport.
ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinputport
andoutputportcanbeeitherx9orx18bitswide,thereadandwriteportwidths
beingsetindependentlyofoneanother.Becausetheportsarecommontoall
queuesthewidthofthequeuesisnotindividuallyset,sothattheinputwidthof
all queues are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete
queueviathewritequeueselectaddressinputs.Conversely,databeingread
fromthedevicereadportisreadfromaqueueselectedviathereadqueueselect
addressinputs.Datacanbesimultaneouslywrittenintoandreadfromthesame
queueordifferentqueues.Onceaqueueisselectedfordatawritesorreads,
the writing and reading operation is performed in the same manner as a
conventionalIDTsynchronous FIFO,utilizingclocks andenables,thereis a
singleclockandenableperport.Whenaspecificqueueisaddressedonthe
writeport,dataplacedonthedatainputsiswrittentothatqueuesequentially
basedontherisingedgeofawriteclockprovidedsetupandholdtimesaremet.
Conversely,dataisreadontotheoutputportafteranaccesstimefromarising
edge on a read clock.
The flag busses are available in two user selectable modes of operation,
“Polled”or“Direct”.Whenoperatinginpolledmodeaflagbusprovidesstatus
ofeachquadrantsequentially,thatis,oneachrisingedgeofaclocktheflagbus
isupdatedtoshowthestatusofeachquadrantinorder.Therisingedgeofthe
writeclockwillupdatethealmostfullbusandarisingedgeonthereadclockwill
updatethealmostemptybus.Themodeofoperationisalwaysthesameforboth
thealmostfullandalmostemptyflagbusses.Whenoperatingindirectmode,the
quadrantontheflagbusisselectedbytheuser.Sotheusercanactuallyaddress
thequadranttobeplacedontheflagstatusbusses,theseflagbussesoperate
independentlyofoneanother.Addressingofthealmostfullflagbusisdonevia
thewriteportandaddressingofthealmostemptyflagbusisdoneviathereadport.
Theoperationofthewriteportiscomparabletothefunctionofaconventional
FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput
provides status of the selected queue. The operation of the read port is
comparabletothefunctionofaconventionalFIFOoperatinginFWFTmode.
Whenaqueueis selectedontheoutputport,thenextwordinthatqueuewill
automaticallyfallthroughtotheoutputregister.Allsubsequentwordsfromthat
queue require an enabled read cycle. Data cannot be read from a selected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
whendata readoutis valid. Ifthe userswitches toa queue thatis empty, the
lastwordfromtheprevious queuewillremainontheoutputregister.
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost
EXPANSION
Expansionofmulti-queuedevicesisalsopossible,upto8devicescanbe
connectedinaparallelfashionprovidingthepossibilityofbothdepthexpansion
or queue expansion. Depth Expansion means expanding the depths of
individual queues. Queue expansion means increasing the total number of
queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore
memoryblocks withinamulti-queuedevicecanbeallocatedtoincreasethe
depth of a queue. For example, depth expansion of 8 devices provides the
possibilityof8queuesof64Kx18deepwithintheIDT72T51543,and128kx
18deepwithintheIDT72T51553,eachqueuebeingsetupwithinasingledevice
utilizing all memory blocks available to produce a single queue. This is the
deepestqueuethatcansetupwithinadevice.
5
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Forqueue expansiona maximumnumberof256(8x32)queues maybe connectingmulti-queuedevicesinexpansionmodeallrespectiveinputpins
setup,eachqueuebeing4Kx18or8Kx9deep,iflessqueuesaresetup,then (data&control)andoutputpins(data& flags),shouldbe“connected”together
morememoryblockswillbeavailabletoincreasequeuedepthsifdesired.When betweenindividualdevices.
6
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS
Symbol &
Pin No.
Name
I/OTYPE
Description
D[17:0]
Din (See Pin
tablefordetails)
DataInputBus
LVTTL
INPUT
Thesearethe18datainputpins.Datais writtenintothedeviceviatheseinputpins ontherisingedge
ofWCLKprovidedthatWENisLOW.Duetobusmatchingnotallinputsmaybeused,anyunusedinputs
shouldbetiedLOW.
DF(1)
(L3)
DefaultFlag
DefaultMode
RCLK Echo
REN Echo
LVTTL
INPUT
Iftheuserrequiresdefaultprogrammingofthemulti-queuedevice,thispinmustbesetupbeforeMaster
Resetandmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
(1)
DFM
(L2)
LVTTL
INPUT
Themulti-queuedevicerequiresprogrammingaftermasterreset.Theusercandothisseriallyviathe
serialport,ortheusercanusethedefaultmethod.IfDFMisLOWatmasterresetthenserialmodewill
beselected,ifHIGHthendefaultmodeisselected.
ERCLK
(R10)
HSTL-LVTTL ReadClockEchooutput,this outputgenerates aclockbasedonthereadclockinput,this is usedfor
OUTPUT SourceSynchronousclockingwherethereceivingdevicesutilizestheERCLKtoclockdataoutputfrom
thequeue.
EREN
(R11)
HSTL-LVTTL ReadEnableEchooutput,canbeusedinconjunctionwiththeERCLKoutputtoloaddataoutputfrom
OUTPUT the queue intothe receivingdevice.
ESTR
(R15)
PAEn Flag Bus
Strobe
LVTTL
INPUT
IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK
andtheRDADDbustoselectaquadrantofqueuestobeplacedontothePAEnbusoutputs.Aquadrant
addressedviatheRDADDbus is selectedontherisingedgeofRCLKprovidedthatESTRis HIGH.If
Polledoperationshasbeenselected,ESTRshouldbetiedinactive,LOW.
ESYNC
(R16)
PAEnBus Sync
LVTTL
ESYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAEnbus
OUTPUT duringPolledoperationofthePAEnbus.DuringPolledoperationeachquadrantofqueuestatusflags
is loadedontothe PAEnbus outputs sequentiallybasedonRCLK. The firstRCLKrisingedge loads
quadrant1ontoPAEn,thesecondRCLKrisingedgeloadsquadrant2andsoon.ThefifthRCLKrising
edgewillagainloadquadrant1.DuringtheRCLKcyclethatquadrant1ofaselecteddeviceis placed
ontothePAEnbus,theESYNCoutputwillbeHIGH.Forallotherquadrantsofthatdevice,theESYNC
outputwillbeLOW.
EXI
(T16)
PAEnBus
ExpansionIn
LVTTL
INPUT
The EXIinputis usedwhenmulti-queue devices are connectedinexpansionmode andPolledPAEn
bus operationhas beenselected. EXIofdevice ‘N’connects directlytoEXOofdevice ‘N-1’. The EXI
receives atokenfromtheprevious deviceinachain.InsingledevicemodetheEXIinputmustbetied
LOWifthePAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheEXIinput
mustbeconnectedtotheEXOoutputofthesamedevice.InexpansionmodetheEXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
EXO
(T15)
PAEnBus
ExpansionOut
LVTTL
EXOisanoutputthatisusedwhenmulti-queuedevicesareconnectedinexpansionmodeandPolled
OUTPUT PAEnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.This
pinpulseswhendeviceNhasplaceditsfinal(4th)quadrantontothePAEnbuswithrespecttoRCLK.
This pulse (token)is thenpassedontothe nextdevice inthe chain‘N+1’andonthe nextRCLKrising
edgethefirstquadrantofdeviceN+1willbeloadedontothePAEnbus.Thiscontinuesthroughthechain
andEXOofthelastdeviceisthenloopedbacktoEXIofthefirstdevice.TheESYNCoutputofeachdevice
inthechainprovides synchronizationtotheuserofthis loopingevent.
FF
(P8)
Full Flag
LVTTL
This pinprovides thefullflagoutputfortheactivequeue,thatis,thequeueselectedontheinputport
OUTPUT forwriteoperations,(selectedviaWCLK,WRADDbus andWADEN).OntheWCLKcycleaftera
queueselection,thisflagwillshowthestatusofthenewlyselectedqueue.Datacanbewrittentothisqueue
onthenextcycleprovidedFFisHIGH.ThisflaghasHigh-Impedancecapability,thisisimportantduring
expansionofdevices,whentheFFflagoutputofupto8devicesmaybeconnectedtogetheronacommon
line.ThedevicewithaqueueselectedtakescontroloftheFFbus,allotherdevicesplacetheirFFoutput
intoHigh-Impedance.Whenaqueueselectionismadeonthewriteportthisoutputwillswitchfrom
High-ImpedancecontrolonthenextWCLKcycle.ThisflagissynchronizedtoWCLK.
(1)
FM
Flag Mode
LVTTL
INPUT
Thispinissetupbeforeamasterresetandmustnottoggleduringanydeviceoperation.Thestateofthe
FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbusses operateineither
PolledorDirectmode.Ifthis pinis HIGHthemodeis Polled,ifLOWthenitwillbeDirect.
(K16)
7
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
FSTR
(R4)
PAFn Flag Bus
Strobe
LVTTL
INPUT
IfdirectoperationofthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK
andtheWRADDbustoselectaquadrantofqueuestobeplacedontothePAFnbusoutputs.Aquadrant
addressedviatheWRADDbusisselectedontherisingedgeofWCLKprovidedthatFSTRisHIGH.If
Polledoperationshasbeenselected,FSTRshouldbetiedinactive,LOW.
FSYNC
(R3)
PAFn Bus Sync
LVTTL
FSYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAFnbus
OUTPUT duringPolledoperationofthePAFnbus.DuringPolledoperationeachquadrantofqueuestatusflags
is loadedontothePAFnbus outputs sequentiallybasedonWCLK.ThefirstWCLKrisingedgeloads
quadrant1ontoPAFn,thesecondWCLKrisingedgeloadsquadrant2andsoon.ThefifthWCLKrising
edgewillagainloadquadrant1.DuringtheWCLKcyclethatquadrant1ofaselecteddeviceisplaced
ontothePAFnbus,theFSYNCoutputwillbeHIGH.Forallotherquadrantsofthatdevice,theFSYNC
outputwillbeLOW.
FXI
(T2)
PAFnBus
ExpansionIn
LVTTL
INPUT
The FXIinputis usedwhenmulti-queue devices are connectedinexpansionmode andPolledPAFn
bus operation has been selected. FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receives atokenfromtheprevious deviceinachain.InsingledevicemodetheFXIinputmustbetied
LOWifthePAFnbusisoperatedindirectmode.IfthePAFnbusisoperatedinpolledmodetheFXIinput
mustbeconnectedtotheFXOoutputofthesamedevice.InexpansionmodetheFXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
FXO
(T3)
PAFnBus
ExpansionOut
LVTTL
FXOisanoutputthatisusedwhenmulti-queuedevicesareconnectedinexpansionmodeandPolled
OUTPUT PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This
pinpulseswhendeviceNhasplaceditsfinal(4th)quadrantontothePAFnbuswithrespecttoWCLK.
This pulse(token)is thenpassedontothenextdeviceinthechain‘N+1’andonthenextWCLKrising
edgethefirstquadrantofdeviceN+1willbeloadedontothePAFnbus.Thiscontinuesthroughthechain
andFXOofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdevice
inthechainprovides synchronizationtotheuserofthis loopingevent.
(1)
ID[2:0]
Device ID Pins
LVTTL
INPUT
Forthe32Qmulti-queuedevicetheWRADDandRDADDaddressbussesare8bitswide.Whenaqueue
selectiontakesplacethe3MSb’softhis8bitaddressbusareusedtoaddressthespecificdevice(the
5 LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s
oftheaddressarecomparedtothedeviceIDpins.Thefirstdeviceinachainofmulti-queue’s(connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which
is‘111’,howevertheIDdoesnothavetomatchthedeviceorder.Insingledevicemodethesepinsshould
besetupas‘000’andthe3MSb’softheWRADDandRDADDaddressbussesshouldbetiedLOW.The
ID[2:0]inputssetuparespectivedevicesIDduringmasterreset.TheseIDpinsmustnottoggleduring
anydevice operation. Note, the device selectedas the ‘Master’does nothave tohave the IDof‘000’.
(ID2-C9
ID1-A10
ID0-B10)
IOSEL
(C8)
IOSelect
LVTTL
INPUT
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
required then IOSEL should be tied LOW. If LVTTL I/O are required then it should be tied HIGH.
(1)
IW
InputWidth
MasterDevice
LVTTL
INPUT
IWselectsthebuswidthforthedatainputbus.IfIWisLOWduringaMasterResetthenthebuswidth
is x18, if HIGH then it is x9.
(L15)
(1)
MAST
(K15)
LVTTL
INPUT
ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe
MasterdeviceoraSlave.IfthispinisHIGH,thedeviceisthemasterifitisLOWthenitisaSlave.Themaster
deviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgotoHigh-Impedance,
preventingbuscontention.Ifamulti-queuedeviceisbeingusedinsingledevicemode,thispinmust
be setHIGH.
MRS
(T9)
MasterReset
LVTTL
INPUT
AmasterresetisperformedbytakingMRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired
aftermasterreset.
NULL-Q
(J2)
NullQueue
Select
HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD
INPUT
address bus toaddress the Null-Q.
OE
(M14)
OutputEnable
LVTTL
INPUT
TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontrolofthemulti-queue
dataoutputbus,Qout.Ifadevicehasbeenconfiguredasa“Master”device,theQoutdataoutputswill
beinaLowImpedanceconditioniftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbe
inHighImpedance.Ifadeviceisconfigureda“Slave”device,thentheQoutdataoutputswillalwaysbe
8
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
OE
(Continued)
OutputEnable
LVTTL
inHighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpointOEprovidesthree-
OUTPUT stateofthatrespectivedevice.
OV
OutputValidFlag LVTTL Thisoutputflagprovidesoutputvalidstatusforthedatawordpresentonthemulti-queueflow-control
(P9)
OUTPUT devicedataoutputport,Qout.Thisflagistherefore,2-stagedelayedtomatchthedataoutputpathdelay.
Thatis,thereisa2RCLKcycledelayfromthetimeagivenqueueisselectedforreads,tothetimethe
OV flagrepresents thedatainthatrespectivequeue.Whenaselectedqueueonthereadportis read
toempty,theOVflagwillgoHIGH,indicatingthatdataontheoutputbusisnotvalid.TheOVflagalsohas
High-Impedancecapability,requiredwhenmultipledevicesareusedandtheOVflagsaretiedtogether.
(1)
OW
(L16)
OutputWidth
LVTTL
INPUT
OWselectsthebuswidthforthedataoutputbus.IfOWisLOWduringaMasterResetthenthebuswidth
is x18, if HIGH then it is x9.
PAE
(P10)
Programmable
Almost-Empty
Flag
LVTTL
ThispinprovidestheAlmost-Emptyflagstatusforthequeuethathasbeenselectedontheoutputport
OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queueisalmost-empty.ThisflagoutputmaybeduplicatedononeofthePAEnbuslines.Thisflagis
synchronizedtoRCLK.
PAEn
Programmable
Almost-Empty
FlagBus
LVTTL
Onthe 32Qdevice the PAEnbus is 8bits wide. This outputbus provides PAE status of8queues
(PAE7-P11
PAE6-P12
PAE5-R12
PAE4-T12
PAE3-P13
PAE2-R13
PAE1-T13
PAE0-T14)
OUTPUT (1quadrant),withinaselecteddevice,havingatotalof4quadrants.Duringqueueread/writeoperations
theseoutputsprovideprogrammableemptyflagstatus,ineitherdirectorpolledmode.Themodeofflag
operationisdeterminedduringmasterresetviathestateoftheFMinput.Thisflagbusiscapableof
High-Impedancestate,thisisimportantduringexpansionofmulti-queuedevices.Duringdirectoperation
the PAEnbus is updatedtoshowthe PAEstatus ofa quadrantofqueues withina selecteddevice.
SelectionismadeusingRCLK,ESTRandRDADD.DuringPolledoperationthePAEnbusisloadedwith
thePAEstatusofmulti-queueflow-controlquadrantssequentiallybasedontherisingedgeofRCLK.
PAF
(R8)
Programmable
LVTTL
ThispinprovidestheAlmost-Fullflagstatusforthequeuethathasbeenselectedontheinputportfor
Almost-FullFlag OUTPUT writeoperations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselected
queueis almost-full.This flagoutputmaybeduplicatedononeofthePAFnbuslines.Thisflagis
synchronizedtoWCLK.
PAFn
Programmable
LVTTL
Onthe32Qdevicethe PAFnbus is 8bits wide.Atanyonetimethis outputbus providesPAFstatus of
(PAF7-P7
PAF6-P6
PAF5-R6
PAF4-R7
PAF3-P5
PAF2-R5
PAF1-T5
PAF0-T4)
Almost-FullFlag OUTPUT 8queues(1quadrant),withinaselecteddevice,havingatotalof4quadrants.Duringqueueread/write
Bus
operationstheseoutputsprovideprogrammablefullflagstatus,ineitherdirectorpolledmode.Themode
offlagoperationisdeterminedduringmasterresetviathestateoftheFMinput.Thisflagbusiscapable
ofHigh-Impedancestate,thisisimportantduringexpansionofmulti-queuedevices.Duringdirect
operationthePAFnbusisupdatedtoshowthePAFstatusofaquadrantofqueueswithinaselecteddevice.
Selectionis madeusingWCLK,FSTR,WRADDandWADEN.DuringPolledoperationthePAFnbus
isloadedwiththePAFstatusofmulti-queueflow-controlquadrantssequentiallybasedontherisingof
edgeWCLK.
PD
(K1)
Power Down
PartialReset
HSTL
INPUT
This inputis usedtoprovideadditionalpowersavings.WhenthedeviceI/Ois setupforHSTL/eHSTL
modeaHIGHonthePDinputdisablesthedatainputsonthewriteportonly,providingsignificantpower
savings. In LVTTL mode this pin has no operation
PRS
(T8)
LVTTL
INPUT
APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.Beforea
PartialResetcanbeperformedonaqueue,thatqueuemustbeselectedonboththewriteportandread
port2clockcyclesbeforetheresetisperformed.APartialResetisthenperformedbytakingPRSLOW
foroneWCLKcycleandoneRCLKcycle.ThePartialResetwillonlyresetthereadandwritepointers
tothefirstmemorylocation,noneofthedevicesconfigurationwillbechanged.
Q[17:0]
DataOutputBus
LVTTL
Thesearethe18dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge
Qout(SeePin
tablefordetails)
OUTPUT ofRCLKprovidedthat REN is LOW, OE is LOWandthe queue is selected. Due tobus matchingnot
alloutputs maybeused,anyunusedoutputs shouldnotbeconnected.
RADEN
(R14)
ReadAddress
Enable
LVTTL
INPUT
TheRADENinputis usedinconjunctionwithRCLKandtheRDADDaddress bus toselectaqueueto
bereadfrom.AqueueaddressedviatheRDADDbusisselectedontherisingedgeofRCLKprovided
thatRADENisHIGH.RADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).RADEN
shouldnotbepermanentlytiedHIGH.RADENcannotbeHIGHforthesameRCLKcycleasESTR.Note,
9
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
RADEN
(Continued)
ReadAddress
Enable
LVTTL
INPUT
thatareadqueueselectioncannotbemade,(RADENmustNOTgoactive)untilprogrammingofthepart
has beencompletedandSENO has goneLOW.
RCLK
(T10)
ReadClock
LVTTL
INPUT
Whenenabledby REN, the risingedge ofRCLKreads data fromthe selectedqueue via the output
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
whileRADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthe
PAEnflagquadranttobeplacedonthePAEnbusduringdirectflagoperation.Duringpolledflagoperation
thePAEnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronizedtoRCLK.ThePAE
andOVoutputs areallsynchronizedtoRCLK.DuringdeviceexpansiontheEXOandEXIsignals are
basedonRCLK. RCLKmustbe continuous andfree-running.
RDADD
[7:0]
ReadAddress
Bus
LVTTL
INPUT
For the 32Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The
firstfunctionofRDADDistoselectaqueuetobereadfrom.Theleastsignificant5bitsofthebus,
RDADD[4:0]areusedtoaddress1of32possiblequeueswithinamulti-queuedevice.Themostsignificant
3bits,RDADD[7:5]areusedtoselect1of8possiblemulti-queuedevices thatmaybeconnectedin
expansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent
ontheRDADDbuswillbeselectedonarisingedgeofRCLKprovidedthatRADENisHIGH,(note,that
data canbe placedontothe Qoutbus, readfromthe previouslyselectedqueue onthis RCLKedge).
On the next rising RCLK edge after a read queue select, a data word from the previous queue will be
placedontotheoutputs,Qout,regardless oftheRENinput.TwoRCLKrisingedges afterreadqueue
select,datawillbeplacedontotheQoutoutputsfromthenewlyselectedqueue,regardlessofRENdue
tothefirstwordfallthrougheffect.
(RDADD7-P16
RDADD6-P15
RDADD5-P14
RDADD4-N16
RDADD3-N15
RDADD2-N14
RDADD1-M16
RDADD0-M15)
The secondfunctionofthe RDADDbus is toselectthe quadrantofqueues tobe loadedontothe
PAEnbusduringstrobedflagmode.Theleastsignificant2bits,RDADD[1:0]areusedtoselectthe
quadrantofadevicetobeplacedonthePAEnbus.Themostsignificant3bits,RDADD[7:5]areagain
usedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansionmode.Address
bitsRDADD[4:2]aredon’tcareduringquadrantselection.ThequadrantaddresspresentontheRDADD
buswillbeselectedontherisingedgeofRCLKprovidedthatESTRisHIGH,(note,thatdatacanbeplaced
ontotheQoutbus,readfromthepreviouslyselectedqueueonthisRCLKedge).PleaserefertoTable2
fordetails onRDADDbus.
REN
ReadEnable
SerialClock
LVTTL
INPUT
The REN input enables read operations from a selected queue based on a rising edge of RCLK.
AqueuetobereadfromcanbeselectedviaRCLK,RADENandtheRDADDaddress bus regardless
ofthestateofREN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond
RCLKcycleafterqueueselectionregardlessofRENduetotheFWFToperation.Areadenableisnot
required to cycle the PAEn bus (in polled mode) or to select the PAEn quadrant , (in direct mode).
(T11)
SCLK
(N3)
LVTTL
INPUT
Ifserialprogrammingofthemulti-queuedevicehasbeenselectedduringmasterreset,theSCLKinput
clockstheserialdatathroughthemulti-queuedevice.DatasetupontheSIinputisloadedintothedevice
ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed
theSCLKofalldevices shouldbeconnectedtothesamesource.
SENI
(M2)
SerialInput
Enable
LVTTL
INPUT
Duringserialprogrammingofamulti-queuedevice,dataloadedontotheSIinputwillbeclockedintothe
part(viaarisingedgeofSCLK),providedtheSENIinputofthatdeviceis LOW.Ifmultipledevices are
cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
loadingofagivendeviceiscomplete,itsSENOoutputgoesLOW,allowingthenextdeviceinthechain
tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.
SENO
(M1)
SerialOutput
Enable
LVTTL
Thisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingofthemulti-queuedevice
OUTPUT hasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO
willgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENOwillalso
goHIGH.WhentheSENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.
Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENOoutput
shouldbeconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogrammingofthe
firstdeviceiscomplete,SENOwillgoLOW,therebytakingtheSENIinputofthenextdeviceLOWand
soonthroughoutthe chain. Whena givendevice inthe chainis fullyprogrammedtheSENO output
10
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
SENO
(Continued)
SerialOutput
Enable
LVTTL
essentiallyfollowstheSENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.
OUTPUT WhenthisoutputgoesLOW,serialloadingofalldeviceshasbeencompleted.
SI
(L1)
SerialIn
LVTTL
INPUT
Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.
Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO
hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connectstotheSIpinofthesecondandsoon.Themulti-queuedevicesetupregistersareshiftregisters.
SO
SerialOut
LVTTL
Thisoutputisusedinexpansionmodeandallowsserialdatatobepassedthroughdevicesinthechain
(M3)
OUTPUT tocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdeviceinthe
chain. The SOofthe finaldevice ina chainshouldnotbe connected.
(2)
TCK
(A8)
JTAGClock
LVTTL
INPUT
ClockinputforJTAGfunction.Oneoffourterminals requiredbyIEEEStandard1149.1-1990.Test
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising
edgeofTCKandoutputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignal
needs tobe tiedtoGND.
(2)
TDI
JTAGTestData
Input
LVTTL
INPUT
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
operation,testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,
IDRegisterandBypass Register.Aninternalpull-upresistorforces TDIHIGHifleftunconnected.
(B9)
(2)
TDO
(A9)
JTAGTestData
Output
LVTTL
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
OUTPUT operation,testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstruction
Register,IDRegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,while
in SHIFT-DR and SHIFT-IR controller states.
TMS(2)
(B8)
JTAGMode
Select
LVTTL
INPUT
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthe
devicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST
(C7)
JTAGReset
LVTTL
INPUT
TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
resetuponpower-up, thus itmustbe resetbyeitherthis signalorbysettingTMS=HIGHforfive TCK
cycles.IftheTAPcontrollerisnotproperlyresetthentheoutputswillalwaysbeinhigh-impedance.Ifthe
JTAGfunctionisusedbuttheuserdoesnotwanttouseTRST,thenTRSTcanbetiedwithMRStoensure
properqueue operation. Ifthe JTAGfunctionis notusedthenthis signalneeds tobe tiedtoGND. An
internalpull-upresistorforcesTRSTHIGHifleftunconnected.
WADEN
(P4)
WriteAddress
Enable
LVTTL
INPUT
TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto
bewritteninto.AqueueaddressedviatheWRADDbusisselectedontherisingedgeofWCLKprovided
thatWADENisHIGH.WADENshouldbeasserted(HIGH)onlyduringaqueuecycle(s).WADENshould
notbepermanentlytiedHIGH.WADENcannotbeHIGHforthesameWCLKcycleasFSTR.Note,that
awritequeueselectioncannotbemade,(WADENmustNOTgoactive)untilprogrammingoftheparthas
beencompletedandSENO hasgoneLOW.
WCLK
(T7)
WriteClock
LVTTL
INPUT
WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheselectedqueueviatheinputbus,
Din. The queue to be written to is selected via the WRADD address bus and a rising edge of WCLK
whileWADENis HIGH.ArisingedgeofWCLKinconjunctionwithFSTRandWRADDwillalsoselect
theflagquadranttobeplacedonthePAFnbusduringdirectflagoperation.Duringpolledflagoperation
the PAFnbus is cycledwithrespecttoWCLKandthe FSYNCsignalis synchronizedtoWCLK. The
PAFn,PAFandFFoutputsareallsynchronizedtoWCLK.DuringdeviceexpansiontheFXOandFXI
signals are basedonWCLK. The WCLKmustbe continuous andfree-running.
WEN
(T6)
WriteEnable
LVTTL
INPUT
TheWENinputenableswriteoperationstoaselectedqueuebasedonarisingedgeofWCLK.Aqueue
tobewrittentocanbeselectedviaWCLK,WADENandtheWRADDaddressbusregardlessofthestate
ofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLKcycleafter
queueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFnbus(inpolled
mode)ortoselectthe PAFnquadrant, (indirectmode).
WRADD
[7:0]
(WRADD7-T1
WriteAddress
Bus
LVTTL
INPUT
Forthe32QdevicetheWRADDbusis8bits.TheWRADDbusisadualpurposeaddressbus.Thefirst
functionofWRADDistoselectaqueuetobewrittento.Theleastsignificant5bitsofthebus,WRADD[4:0]
areusedtoaddress1of32possiblequeueswithinamulti-queuedevice.Themostsignificant3bits,
11
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
WRADD6-R1
WRADD5-R2
WRADD4-P1
WRADD3-P2
WRADD2-P3
WRADD1-N1
WRADD0-N2)
WRADD[7:5]areusedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
WRADDbuswillbeselectedonarisingedgeofWCLKprovidedthatWADENisHIGH,(note,thatdata
presentontheDinbuscanbewrittenintothepreviouslyselectedqueueonthisWCLKedgeandonthe
nextrisingWCLKalso,providingthatWENisLOW).TwoWCLKrisingedgesafterwritequeueselect,
datacanbewrittenintothenewlyselectedqueue.
ThesecondfunctionoftheWRADDbusistoselectthequadrantofqueuestobeloadedontothePAFn
busduringstrobedflagmode.Theleastsignificant2bits,WRADD[1:0]areusedtoselectthequadrant
ofa device tobe placedonthePAFnbus. The mostsignificant3bits, WRADD[7:5]are againused
toselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansionmode.Addressbits
WRADD[4:2]aredon’tcareduringquadrantselection.ThequadrantaddresspresentontheWRADD
buswillbeselectedontherisingedgeofWCLKprovidedthatFSTRisHIGH,(note,thatdatacanbewritten
intothepreviouslyselectedqueueonthisWCLKedge).PleaserefertoTable1fordetailsontheWRADD
bus.
VCC
(See below)
+2.5VSupply
Power
Power
These are VCC power supply pins and must all be connected to a +2.5V supply rail.
VDDQ
(See Pin No.
tablefordetails)
O/PRailVoltage
Thesepinsmustbetiedtothedesiredoutputrailvoltage.ForLVTTLI/Othesepinsmustbeconnected
to+2.5V,forHSTLthesepinsmustbeconnectedto+1.5VandforeHSTLthesepinsmustbeconnected
to+1.8V.
GND
GroundPin
Ground
These are Ground pins and must all be connected to the GND supply rail.
(See below)
Vref
(K3)
Reference
Voltage
HSTL
INPUT
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable
"RecommendedDCOperatingConditions". The inputprovides the reference levelforHSTL/eHSTL
inputs. ForLVTTLI/Omode this inputshouldbe tiedtoGND.
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 52-56 and Figures 32-34.
PIN NUMBER TABLE
Symbol
Name
DataInputBus HSTL-LVTTL D17-C1, D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5, D6-B5, D5-C5,
INPUT D4-A6, D3-B6, D2-C6, D1-A7, D0-B7
I/OTYPE
Pin Number
D[17:0]
Din
Q[17:0]
Qout
DataOutputBus HSTL-LVTTL Q17-C15, Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14, Q11-B14, Q10-C14, Q9-A13, Q8-B13,
OUTPUT Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11, Q(1,0)-C(11,10)
VCC
+2.5VSupply
O/PRailVoltage
GroundPin
Power
Power
Ground
D(7-10),E(6,7,10,11),F(5,12),G(4,5,12,13),H(4,13),J(4,13),K(4,5,12,13),L(5,12),M(6,7,10,11),N(7-10)
D(4-6,11-13), E(4,5,12,13), F(4,13), L(4,13), M(4,5,12,13), N(4-6,11-13)
VDDQ
GND
C(2,3), D(1-3), E(1-3,8-9), F(1-3,6-11), G(1-3,6-11), H(1-3,5-12), J(1,3,5-12,14), K(2,6-11,14),
L(6-11,14), M(8-9)
DNC
DoNotConnect
None
B16, C16, D(15,16), E(14-16), F(14-16), G(14-16), H(14-16), J(15-16), R9
12
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
–0.5to+3.6(2)
Unit
Symbol
Parameter(1)
Conditions
Max.
Unit
VTERM
TerminalVoltage
with respect to GND
V
(2,3)
CIN
Input
Capacitance
VIN = 0V
10(3)
pF
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
(1,2)
COUT
Output
Capacitance
VOUT = 0V
15
pF
NOTES:
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
RECOMMENDEDDCOPERATINGCONDITIONS
Symbol
VCC
Parameter
Min.
2.375
0
Typ.
2.5
0
Max.
2.625
0
Unit
V
SupplyVoltage
SupplyVoltage
GND
V
VIH
InputHighVoltage
LVTTL
eHSTL
HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
3.45
—
—
V
V
V
VIL
InputLowVoltage
LVTTL
eHSTL
HSTL
-0.3
—
—
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
VREF
(HSTL only)
VoltageReferenceInput eHSTL
HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
TA
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
0
—
—
70
85
°C
°C
TA
-40
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
13
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
ILI
Parameter
Min.
–10
–10
Max.
10
Unit
µA
µA
V
V
V
InputLeakageCurrent
OutputLeakageCurrent
ILO
10
(3)
VOH
OutputLogic“1”Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
VDDQ-0.4
VDDQ-0.4
VDDQ-0.4
—
—
—
IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
VOL
OutputLogic“0”Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
—
—
—
0.4V
0.4V
0.4V
V
V
V
IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
ICC1(1,2)
ICC2(1)
ICC3(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
80
150
150
mA
mA
mA
Standby VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
25
100
100
mA
mA
mA
Standby VCC Current in Power Down mode(VCC = 2.5V) I/O = LVTTL
—
—
—
—
50
50
mA
mA
mA
I/O = HSTL
I/O = eHSTL
(1,2)
IDDQ
ActiveVDDQ Current (VDDQ =2.5VLVTTL)
(VDDQ = 1.5V HSTL)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
10
10
10
mA
mA
mA
(VDDQ = 1.8V eHSTL)
NOTES:
1. Both WCLK and RCLK toggling at 20MHz.
2. Data inputs toggling at 10MHz.
3. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)].
4. Outputs are not 3.3V tolerant.
5. The following inputs should be pulled to GND: WRADD, RDADD, WADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.
The following inputs should be pulled to VCC: WEN, REN, SENI, PRS, MRS, TDI, TMS and TRST.
All other inputs are don't care and should be at a known state.
14
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
HSTL
AC TEST LOADS
1.5V AC TEST CONDITIONS
V
DDQ/2
InputPulseLevels
0.25to1.25V
0.4ns
InputRise/FallTimes
50Ω
InputTimingReferenceLevels
OutputReferenceLevels
0.75
Z0 = 50Ω
VDDQ/2
I/O
5999 drw04
NOTE:
1. VDDQ = 1.5V±.
Figure 2a. AC Test Load
EXTENDEDHSTL
1.8V AC TEST CONDITIONS
6
5
4
3
2
1
InputPulseLevels
0.4 to 1.4V
0.4ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.9
VDDQ/2
NOTE:
1. VDDQ = 1.8V±.
20 30 50 80 100
200
Capacitance (pF)
5999 drw04a
2.5VLVTTL
2.5V AC TEST CONDITIONS
Figure 2b. Lumped Capacitive Load, Typical Derating
InputPulseLevels
GND to 2.5V
1ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
VCC/2
VDDQ/2
NOTE:
1. For LVTTL VCC = VDDQ.
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
Output
Normally
LOW
V
CC/2
OL
V
CC/2
100mV
100mV
100mV
V
V
OH
Output
Normally
HIGH
100mV
VCC/2
VCC/2
5999 drw04b
NOTE:
1. REN is HIGH.
15
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72T51543L5
IDT72T51553L5
IDT72T51543L6
IDT72T51553L6
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency (WCLK & RCLK)
DataAccessTime
—
0.6
5
200
3.6
—
—
—
—
—
—
—
—
—
—
—
—
3.6
3.6
3.6
10
—
0.6
6
166
3.7
—
—
—
—
—
—
—
—
—
—
—
—
3.7
3.7
3.7
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock High Time
2.3
2.3
1.5
0.5
1.5
0.5
30
2.7
2.7
2.0
0.5
2.0
0.5
30
Clock Low Time
DataSetupTime
tDH
DataHoldTime
tENS
tENH
tRS
EnableSetupTime
EnableHoldTime
ResetPulseWidth
tRSS
tRSR
tPRSS
tPRSH
ResetSetupTime
15
15
ResetRecoveryTime
10
10
PartialResetSetup
1.5
0.5
0.6
0.6
0.6
—
100
45
2.0
0.5
0.6
0.6
0.6
—
100
45
PartialResetHold
(2)
tOLZ(OE-Qn)
OutputEnabletoOutputinLow-Impedance
OutputEnabletoOutputinHigh-Impedance
OutputEnabletoDataOutputValid
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
(2)
tOHZ
tOE
fC
tSCLK
tSCKH
tSCKL
tSDS
—
—
—
—
—
—
—
20
—
—
—
—
—
—
—
20
Serial Clock High
Serial Clock Low
45
45
SerialDataInSetup
20
20
tSDH
tSENS
tSENH
tSDO
tSENO
tSDOP
tSENOP
tPCWQ
tPCRQ
tAS
Serial Data In Hold
1.2
20
1.2
20
SerialEnableSetup
SerialEnableHold
1.2
—
—
1.5
1.5
20
1.2
—
—
1.5
1.5
20
SCLK to Serial Data Out
SCLK to Serial Enable Out
SerialDataOutPropagationDelay
SerialEnablePropagationDelay
ProgrammingCompletetoWriteQueueSelection
ProgrammingCompletetoReadQueueSelection
AddressSetup
20
20
3.7
3.7
—
—
—
—
3.6
3.6
—
—
—
—
3.6
3.6
3.6
3.6
3.7
3.7
—
—
—
3.7
3.7
—
—
—
—
3.7
3.7
3.7
3.7
20
20
1.5
1.0
—
—
1.5
0.5
1.5
1.0
0.6
0.6
0.6
0.6
2.5
1.5
—
—
2.0
0.5
2.0
0.5
0.6
0.6
0.6
0.6
tAH
Address Hold
tWFF
tROV
tSTS
Write Clock to Full Flag
ReadClocktoOutputValid
PAE/PAF Strobe Setup
PAE/PAF Strobe Hold
QueueSetup
tSTH
tQS
tQH
QueueHold
tWAF
tRAE
tPAF
tPAE
WCLK to PAF flag
RCLK to PAE flag
Write ClocktoSynchronous Almost-FullFlagBus
Read Clock to Synchronous Almost-Empty Flag Bus
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
16
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(CONTINUED)
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72T51543L5
IDT72T51553L5
IDT72T51543L6
IDT72T51553L6
Symbol
Parameter
RCLK to Echo RCLK Output
Min.
Max.
Min.
Max.
Unit
tERCLK
tCLKEN
—
—
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
4
4.0
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
—
—
—
—
—
—
—
—
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
4.5
6
4.2
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RCLK to Echo REN Output
(2)
tPAELZ
RCLK to PAE Flag Bus to Low-Impedance
RCLK to PAE Flag Bus to High-Impedance
WCLK to PAF Flag Bus to Low-Impedance
WCLK to PAF Flag Bus to High-Impedance
WCLKtoFullFlagtoHigh-Impedance
WCLKtoFullFlagtoLow-Impedance
(2)
tPAEHZ
(2)
tPAFLZ
(2)
tPAFHZ
(2)
tFFHZ
(2)
tFFLZ
(2)
tOVLZ
RCLKtoOutputValidFlagtoLow-Impedance
RCLKtoOutputValidFlagtoHigh-Impedance
WCLK to PAF Bus Sync to Output
WCLK to PAF Bus Expansion to Output
RCLK to PAE Bus Sync to Output
RCLK to PAE Bus Expansion to Output
SKEW time between RCLK and WCLK for FF and OV
SKEW time between RCLK and WCLK for PAF and PAE
SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7]
SKEW time between RCLK and WCLK for OV
ExpansionInputSetup
(2)
tOVHZ
tFSYNC
tFXO
tESYNC
tEXO
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tXIS
5
5
6
5
6
1.0
0.5
1.0
0.5
tXIH
ExpansionInputHold
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
17
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
active,LOW.Upondetectionofcompletionofprogramming,theusershould
ceaseallprogrammingandtakeSENIinactive,HIGH.Note,SENOfollowsSENI
onceprogrammingofadeviceiscomplete.Therefore,SENOwillgoLOWafter
programmingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENO
willalsogoHIGH.TheoperationoftheSOoutputissimilar,whenprogramming
ofagivendeviceiscomplete,theSOoutputwillfollowtheSIinput.
Ifdevicesarebeingusedinexpansionmodetheserialportsofdevicesshould
becascaded.Theusercanloadalldevicesviatheserialinputportcontrolpins,
SI & SENI, of the first device in the chain. Again, the user may utilize the ‘C’
programtogeneratetheserialbitstream,theprogrampromptingtheuserfor
the numberofdevices tobe programmed. The SENO andSO(serialout)of
thefirstdeviceshouldbeconnectedtothe SENI andSIinputs ofthesecond
devicerespectivelyandsoon,withtheSENO&SOoutputsconnectingtothe
SENI&SIinputsofalldevicesthroughthechain.Alldevicesinthechainshould
beconnectedtoacommonSCLK.Theserialoutputportofthefinaldeviceshould
be monitored by the user. When SENO of the final device goes LOW, this
indicates thatserialprogrammingofalldevices has beensuccessfullycom-
pleted.Upondetectionofcompletionofprogramming,theusershouldceaseall
programmingandtakeSENIofthefirstdeviceinthechaininactive,HIGH.
Asmentioned,thefirstdeviceinthechainhasitsserialinputportcontrolled
bytheuser,thisisthefirstdevicetohaveitsinternalregistersseriallyloaded
bytheserialbitstream.Whenprogrammingofthisdeviceiscompleteitwilltake
its SENOoutputLOWandbypasstheserialdataloadedontheSIinputtoits
SOoutput.Theserialinputoftheseconddeviceinthechainisnowloadedwith
thedatafromtheSOofthefirstdevice,whiletheseconddevicehasitsSENI
input LOW. This process continues through the chain until all devices are
programmedandtheSENOofthefinaldevicegoesLOW.
FUNCTIONALDESCRIPTION
MASTERRESET
AMasterResetisperformedbytogglingtheMRSinputfromHIGHtoLOW
toHIGH.Duringamasterresetallinternalmulti-queuedevicesetupandcontrol
registersareinitializedandrequireprogrammingeitherseriallybytheuservia
theserialport,orusingthedefaultsettings.Duringamasterresetthestateof
thefollowinginputsdeterminethefunctionalityofthepart,thesepinsshouldbe
held HIGH or LOW.
FM – Flag bus Mode
IW,OW–BusMatchingoptions
MAST – Master Device
ID0, 1, 2 – Device ID
DFM–Programmingmode,serialordefault
DF – Offset value for PAE andPAF
Onceamasterresethastakenplace,thedevicemustbeprogrammedeither
seriallyorviathedefaultmethodbeforeanyread/writeoperationscanbegin.
See Figure 5, Master Reset for relevant timing.
PARTIALRESET
APartialResetisameansbywhichtheusercanresetboththereadandwrite
pointers of a single queue that has been setup within a multi-queue device.
Beforeapartialresetcantakeplaceonaqueue,therespectivequeuemustbe
selectedonboththereadportandwriteportaminimumof2RCLKand2WCLK
cyclesbeforethePRSgoesLOW.Thepartialresetisthenperformedbytoggling
thePRSinputfromHIGHtoLOWtoHIGH,maintainingtheLOWstateforatleast
oneWCLKandoneRCLKcycle.Onceapartialresethastakenplaceaminimum
of3WCLKand3RCLKcyclesmustoccurbeforeenabledwritesorreadscan
occur.
Once all serial programming has been successfully completed, normal
operations,(queueselectionsonthereadandwriteports)maybegin.When
connectedinexpansionmode,theIDT72T51543/72T51553devicesrequire
atotalnumberofseriallyloadedbitsperdevicetocompleteserialprogramming,
(SCLKcycleswithSENIenabled),calculatedby:n[19+(Qx72)]whereQisthe
numberofqueues the userwishes tosetupwithinthe device, where nis the
numberofdevices inthechain.
APartialResetonlyresets thereadandwritepointers ofagivenqueue,a
partialresetwillnoteffecttheoverallconfigurationandsetupofthemulti-queue
deviceandits queues.
See Figure 6, PartialReset for relevant timing.
SeeFigure7,SerialPortConnectionandFigure8,SerialProgrammingfor
connectionandtiminginformation.
SERIAL PROGRAMMING
Themulti-queueflow-controldeviceisafullyprogrammabledevice,provid-
ingtheuserwithflexibilityinhowqueuesareconfiguredintermsofthenumber
of queues, depth of each queue and position of the PAF/PAE flags within
respectivequeues.Alluserprogrammingisdoneviatheserialportafteramaster
resethas takenplace. Internallythe multi-queue device has setupregisters
whichmustbeseriallyloaded,theseregisterscontainvaluesforeveryqueue
within the device, such as the depth and PAE/PAF offset values. The
IDT72T51543/72T51553 devices are capable of up to 32 queues and
thereforecontain32setsofregistersforthesetupofeachqueue.
DuringaMasterResetiftheDFM(DefaultMode)inputisLOW,thenthedevice
willrequire serialprogrammingbythe user. Itis recommendedthatthe user
utilizea‘C’programprovidedbyIDT,thisprogramwillprompttheuserforall
informationregardingthemulti-queuesetup.Theprogramwillthengenerate
aserialbitstreamwhichshouldbeseriallyloadedintothedeviceviatheserial
port. For the IDT72T51543/72T51553 devices the serial programming re-
quiresatotalnumberofseriallyloadedbitsperdevice,(SCLKcycleswithSENI
enabled),calculatedby:19+(Qx72)whereQisthenumberofqueuestheuser
wishestosetupwithinthedevice.
DEFAULTPROGRAMMING
Duringa MasterResetifthe DFM(DefaultMode)inputis HIGHthe multi-
queuedevicewillbeconfiguredfordefaultprogramming,(serialprogramming
is not permitted). Default programming provides the user with a simpler,
howeverlimitedmeansbywhichtosetupthemulti-queueflow-controldevice,
rather than using the serial programming method. The default mode will
configure a multi-queue device such that the maximum number of queues
possiblearesetup,withallofthepartsavailablememoryblocksbeingallocated
equallybetweenthequeues.ThevaluesofthePAE/PAFoffsetsisdetermined
bythe state ofthe DF(default)pinduringa masterreset.
For the IDT72T51543/72T51553 devices the default mode will setup 32
queues,eachqueueconfiguredasfollows:fortheIDT72T51543withx9input
andx9outputports, 4,096x9. Ifone orbothports is x18, then2,048x18for
the IDT72T51553 with x9 input and x9 output ports, 8,192 x 9. If one or both
portsisx18,then4,096x18.ForbothdevicesthevalueofthePAE/PAFoffsets
isdeterminedatmasterresetbythestateoftheDFinput.IfDFisLOWthenboth
the PAE & PAF offset will be 8, if HIGH then the value is 128.
Once the master reset is complete and MRS is HIGH, the device can be
seriallyloaded.DatapresentontheSI(serialin),inputisloadedintotheserial
port on a rising edge of SCLK (serial clock), provided that SENI (serial in
enable),isLOW.Onceserialprogrammingofthedevicehasbeensuccessfully
completedthedevicewillindicatethisviatheSENO(serialoutputenable)going
WhenconfiguringtheIDT72T51543/72T51553devicesindefaultmodethe
usersimplyhastoapplyWCLKcyclesafteramasterreset,untilSENOgoes
LOW,thissignalsthatdefaultprogrammingiscomplete.Theseclockcyclesare
requiredforthedevicetoloaditsinternalsetupregisters.Whenasinglemulti-
18
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
queuedeviceisused,thecompletionofdeviceprogrammingissignaledbythe Allsubsequentwriteswillbewrittentothatqueueuntilanewqueueisselected.
SENO outputofadevicegoingfromHIGHtoLOW.Note,thatSENImustbe Aminimumof3WCLKcyclesmustoccurbetweenqueueselectionsonthewrite
heldLOWwhenadeviceissetupfordefaultprogrammingmode.
port.OnthenextWCLKrisingedgethewriteportdiscretefullflagwillupdate
Whenmulti-queuedevicesareconnectedinexpansionmode,theSENIof toshowthefullstatusofthenewlyselectedqueue.Onthesecondrisingedge
the first device in a chain can be held LOW. The SENO of a device should ofWCLK,datapresentonthedatainputbus,Dincanbewrittenintothenewly
connecttotheSENIofthenextdeviceinthechain.TheSENOofthefinaldevice selectedqueueprovidedthatWENisLOWandthenewqueueisnotfull.The
isusedtoindicatethatdefaultprogrammingofalldevicesiscomplete.Whenthe cycleofthequeueselectionandthenextcyclewillcontinuetowritedatapresent
finalSENOgoesLOWnormaloperationsmaybegin.Again,alldeviceswillbe onthedatainputbus,DinintothepreviousqueueprovidedthatWENisactive
programmedwiththeirmaximumnumberofqueuesandthememorydivided LOW.
equally between them. Please refer to Figure 9, DefaultProgramming.
IfWENisHIGH,inactiveforthese3clockcycles,thendatawillnotbewritten
in to the previous queue.
WRITE QUEUE SELECTION & WRITE OPERATION
Ifthenewlyselectedqueueisfullatthepointofitsselection,thenwritestothat
TheIDT72T51543/72T51553multi-queueflow-controldeviceshaveupto queue willbe prevented, a fullqueue cannotbe writteninto.
32queuesthatdatacanbewrittenintoviaacommonwriteportusingthedata Inthe32queuemulti-queuedevicetheWRADDaddressbusis8bitswide.
inputs, Din, write clock, WCLK and write enable, WEN. The queue address Theleastsignificant5bitsareusedtoaddressoneofthe32availablequeues
presentonthewriteaddressbus,WRADDduringarisingedgeonWCLKwhile withinasinglemulti-queuedevice.Themostsignificant3bitsareusedwhen
write address enable, WADEN is HIGH, is the queue selected for write adeviceis connectedinexpansionmode,upto8devices canbeconnected
operations. The state of WEN is don’t care during the write queue selection inexpansion,eachdevicehavingits own3bitaddress.Theselecteddevice
cycle.ThequeueselectiononlyhastobemadeonasingleWCLKcycle,this istheoneforwhichtheaddressmatchesa3bitIDcode,whichisstaticallysetup
willremainthe selectedqueue untilanotherqueue is selected, the selected on the ID pins, ID0, ID1, and ID2 of each individual device.
queueisalwaysthelastqueueselected.
Note,theWRADDbusisalsousedinconjunctionwithFSTR(almostfullflag
Thewriteportisdesignedsuchthat100%busutilizationcanbeobtained. busstrobe),toaddressthealmostfullflagbusquadrantduringdirectmodeof
ThismeansthatdatacanbewrittenintothedeviceoneveryWCLKrisingedge operation.
includingthecyclethatanewqueueisbeingaddressed.Whenanewqueue
RefertoTable1,forWriteAddressbusarrangement.Also,refertoFigure
isselectedforwriteoperationstheaddressforthatqueuemustbepresenton 10, Write Queue Select, Write OperationandFullflagOperationandFigure
theWRADDbusduringarisingedgeofWCLKprovidedthatWADENisHIGH. 12,FullFlagTimingExpansionMode fortimingdiagrams.
AqueuetobewrittentoneedonlybeselectedonasinglerisingedgeofWCLK.
TABLE 1 — WRITE ADDRESS BUS, WRADD[7:0]
Operation WCLK WADEN FSTR
WRADD[7:0]
7 6 5 4 3 2
1 0
Write
Queue
Select
1
0
Device Select
(Compared to
ID0,1,2)
Write Queue Address
(5 bits = 32 Queues)
7 6 5 4 3 2
1 0
PAFn
Quadrant
Select
0
1
Device Select
(Compared to
ID0,1,2)
X
X
X
Quadrant
Address
Quadrant
Address
Queue Status on PAFn Bus
00
Q0 : Q7 → PAF0 : PAF7
Q8 : Q15 → PAF0 : PAF7
Q16 : Q23 → PAF0 : PAF7
Q24 : Q31 → PAF0 : PAF7
01
10
11
5999 drw05
19
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
READ QUEUE SELECTION & READ OPERATION
registerafter3RCLKcycles.Asmentioned,intheprevious3RCLKcyclesto
Themulti-queueflow-controldevicehasupto32queuesthatdataisread thenewdatabeingavailable,datacanstillbereadfromthepreviousqueue,
fromviaacommonreadportusingthedataoutputs,Qout,readclock,RCLK providedthatthequeueisnotempty.Atthepointofqueueselection,the internal
and read enable, REN. An output enable, OE control pin is also provided to datapipelineisloadedwiththelastwordfromthepreviousqueueandthenext
allow High-Impedance selection of the Qout data outputs. The multi-queue wordfromthenewqueue,boththesewordswillfallthroughtotheoutputregister
device read port operates in a mode similar to “First Word Fall Through” on consecutivelyuponselectionofthenewqueue.Thispipeliningeffectprovides
atraditionalIDTFIFO,butwiththeaddedfeatureofdataoutputpipelining.This theuserwith100%busutilization,andbringsaboutthepossibilitythata“NULL”
datapipeliningontheoutputportallowstheusertoachieve100%busutilization, queue maybe requiredwithina multi-queue device. Nullqueue operationis
which is the ability to read out a data word on every rising edge of RCLK discussedinthenextsectionon.
regardless of whether a new queue is being selected for read operations.
IfanemptyqueueisselectedforreadoperationsontherisingedgeofRCLK,
The queue address present on the read address bus, RDADD during a onthesameRCLKedgeandthefollowingRCLKedge,2finalreadswillbemade
risingedgeonRCLKwhilereadaddressenable,RADENisHIGH,isthequeue fromthepreviousqueue,providedthatRENisactive,LOW.OnthenextRCLK
selectedforreadoperations.Aqueuetobereadfromneedonlybeselected rising edge a read from the new queue will not occur, because the queue is
ona single risingedge ofRCLK. Allsubsequentreads willbe readfromthat empty.Thelastwordinthedataoutputregister(fromthepreviousqueue),will
queueuntilanewqueueisselected.Aminimumof3RCLKcyclesmustoccur remainthere,buttheoutputvalidflag,OVwillgoHIGH,toindicatethatthedata
betweenqueueselectionsonthereadport.Datafromthenewlyselectedqueue present is no longer valid.
willbepresentontheQoutoutputsafter3RCLKcyclesplusanaccesstime,
TheRDADDbusisalsousedinconjunctionwithESTR(almostemptyflag
providedthatOEisactive,LOW.OnthesameRCLKrisingedgethatthenew busstrobe),toaddressthealmostemptyflagbusquadrantduringdirectmode
queueisselected,datacanstillbereadfromthepreviouslyselectedqueue, ofoperation.Inthe32queuemulti-queuedevicetheRDADDaddressbusis
providedthatRENisLOW,activeandthepreviousqueueisnotemptyonthe 8bitswide.Theleastsignificant5bitsareusedtoaddressoneofthe32available
followingrisingedgeofRCLKawordwillbereadfromthepreviouslyselected queueswithinasinglemulti-queuedevice.Themostsignificant3bitsareused
queueregardlessofRENduetothefallthroughoperation,(providedthequeue when a device is connected in expansion mode, up to 8 devices can be
isnotempty). RememberthatOEallowstheusertoplacetheQout,dataoutput connectedinexpansion,eachdevicehavingitsown3bitaddress.Theselected
bus into High-Impedance and the data can be read onto the output register deviceistheoneforwhichtheaddressmatchesa3bitIDcode,whichisstatically
regardlessofOE.
setup on the ID pins, ID0, ID1, and ID2 of each individual device.
RefertoTable2,forReadAddressbusarrangement.Also,refertoFigures
Whenaqueueis selectedonthereadport,thenextwordavailableinthat
queue (provided that the queue is not empty), will fall through to the output 13,15&16forreadqueueselectionandreadportoperationtimingdiagrams.
TABLE 2 — READ ADDRESS BUS, RDADD[7:0]
Operation
RCLK RADEN ESTR
Null-Q
0
RDADD[7:0]
4 3 2
7
6
5
1 0
Read Queue
Select
1
0
1
0
1
0
Device Select
(Compared to
ID0,1,2)
Read Queue Address
(5 bits = 32 Queues)
7
6
5
4 3 2
1 0
Quadrant
Address
PAEn
Quadrant
Select
0
1
Device Select
(Compared to
ID0,1,2)
X
X
X
7
X
6
X
5
X
4 3 2
1 0
Null Queue
Select
X
X
X
X
X
Quadrant
Address
Queue Status on PAEn Bus
00
Q0 : Q7 → PAE0 : PAE7
Q8 : Q15 → PAE0 : PAE7
Q16 : Q23 → PAE0 : PAE7
Q24 : Q31 → PAE0 : PAE7
01
10
11
5999 drw06
20
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NULL QUEUE OPERATION (OF THE READ PORT)
Note,thattheinputportservesallqueueswithinadevice,asdoestheoutput
Pipeliningofdatatotheoutputportenablesthedevicetoprovide100%bus port,thereforetheinputbuswidthtoallqueuesisequal(determinedbytheinput
utilizationinstandardmode.Datacanbereadoutofthemulti-queueflow-control portsize)andtheoutputbuswidthfromallqueuesisequal(determinedbythe
deviceoneveryRCLKcycleregardlessofqueueswitchesorotheroperations. outputportsize).
Thedevicearchitectureissuchthatthepipelineisconstantlyfilledwiththenext
wordsinaselectedqueuetobereadout,againproviding100%busutilization. FULL FLAG OPERATION
This type of architecture does assume that the user is constantly switching
queuessuchthatduringaqueueswitch,thelastdatawordrequiredfromthe TheFFflagoutputprovidesafullstatusofthequeuecurrentlyselectedonthe
previousqueuewillfallthroughthepipelinetotheoutput. writeportforwriteoperations.Internallythemulti-queueflow-controldevice
Note,thatifreadsceaseattheemptyboundaryofaqueue,thenthelastword monitorsandmaintainsastatusofthefullconditionofallqueueswithinit,however
willautomaticallyflowthroughthepipelinetotheoutput. onlythequeuethatisselectedforwriteoperationshasitsfullstatusoutputtothe
The NullQoperationis achievedbysettingthe NullQsignalHIGHduring FF flag.This dedicatedflagis oftenreferredtoas the“activequeuefullflag”.
aqueueselect.NotethatthereadaddressbusRDADD[7:0]isadon'tcare.The Whenqueueswitchesarebeingmadeonthewriteport,theFFflagoutput
Themulti-queueflow-controldeviceprovidesasingleFullFlagoutput,FF.
NullQueueisaseparatequeuewithinthedeviceandthusthemaximumnumber willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
ofqueuesandmemoryisalwaysavailableregardlessofwhetherornottheNull onthecycleafteranewqueueselectionismade.Theuserthenhasafullstatus
queue is used. Also note that in expansion mode a user may want to use a forthenewqueueonecycleaheadoftheWCLKrisingedgethatdatacanbe
dedicatednullqueueforeachdevice.Anullqueuecanbeselectedwhenno writtenintothenewqueue.Thatis,anewqueuecanbeselectedonthewrite
furtherreadsarerequiredfromapreviouslyselectedqueue.Changingtoanull portviatheWRADDbus,WADENenableandarisingedgeofWCLK.Onthe
queuewillcontinuetopropagatedatainthepipelinetothepreviousqueue's secondrisingedgeofWCLK,theFFflagoutputwillshowthefullstatusofthe
output.TheNullQcanremainselecteduntiladatabecomesavailableinanother newlyselectedqueue.OnthethirdrisingedgeofWCLKfollowingthequeue
queueforreading.TheNull-Qcanbeutilizedineitherstandardorpacketmode. selection,datacanbewrittenintothenewlyselectedqueueprovidedthatdata
Note:Iftheuserswitchesthereadporttothenullqueue,thisqueueisseen andenablesetup&holdtimesaremet.
asandtreatedasanemptyqueue,thereforeafterswitchingtothenullqueue
thelastwordfromthepreviousqueuewillremainintheoutputregisterandthe afterqueueselection,whichisonecyclebeforedatacanbewrittentothatqueue.
OVflagwillgoHIGH,indicatingdatais notvalid. Thispreventstheuserfromwritingdatatoaqueuethatisfull,(assumingthat
TheNullqueueoperationonlyhassignificancetothereadportofthemulti- a queue switchhas beenmade toa queue thatis actuallyfull).
queue, it is a means to force data through the pipeline to the output. Null Q TheFFflagissynchronoustotheWCLKandalltransitionsoftheFFflagoccur
selectionandoperationhasnomeaningonthewriteportofthedevice.Also, basedonarisingedgeofWCLK.Internallythemulti-queuedevicemonitorsand
Note,theFFflagwillprovidestatusofanewlyselectedqueuetwoWCLKcycle
refer to Figure 17, Read Operation and Null Queue Select for diagram.
keepsarecordofthefullstatusforallqueues.Itispossiblethatthestatusofa
FFflagmaybechanginginternallyeventhoughthatflagisnottheactivequeue
flag (selected on the write port). A queue selected on the read port may
BUS MATCHING OPERATION
BusMatchingoperationbetweentheinputportandoutputportisavailable. experienceachangeofitsinternalfullflagstatusbasedonreadoperations.
Duringamasterresetofthemulti-queuethestateofthetwosetuppins,IW(Input See Figure 10, Write Queue Select, Write Operation and Full Flag
Width)andOW(OutputWidth)determinetheinputandoutputportbuswidths Operation and Figure 12, Full Flag Timing in Expansion Mode for timing
aspertheselectionsshowninTable3,“BusMatchingSet-Up”.9bitbytesor information.
18bitwordscanbewrittenintoandreadfromthequeues.Whenwritingtoor
readingfromthemulti-queueinabusmatchingmode,thedeviceordersdata EXPANSION MODE - FULL FLAG OPERATION
ina“LittleEndian”format.SeeFigure4,BusMatchingByteArrangementfor
details.
Whenmulti-queuedevicesareconnectedinExpansionmodetheFFflags
of all devices should be connected together, such that a system controller
TheFullflagandAlmostFullflagoperationis always basedonwrites and monitoring and managing the multi-queue devices write port only looks at a
readsofdatawidthsdeterminedbythewriteportwidth.Forexample,iftheinput singleFFflag(asopposedtoadiscreteFFflagforeachdevice).ThisFFflag
portisx18andtheoutputportisx9,thentwodatareadsfromafullqueuewill isonlypertinenttothequeuebeingselectedforwriteoperationsatthattime.
berequiredtocausethefullflagtogoHIGH(queuenotfull).Conversely,the Remember,thatwheninexpansionmodeonlyonemulti-queuedevicecanbe
OutputValidflagandAlmostEmptyflagoperationsarealwaysbasedonwrites writtentoatanymomentintime,thustheFFflagprovidesstatusoftheactive
andreadsofdatawidthsdeterminedbythereadport.Forexample,iftheinput queue on the write port.
portisx9andtheoutputportisx18,twowriteoperationswillberequiredtocause
theoutputvalidflagofanemptyqueuetogoLOW,outputvalid(queueisnot outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheFFflag
empty).
madeonlyasingledevicedrivestheFFflagbusandallotherFFflagoutputs
connectedtotheFFflagbusareplacedintoHigh-Impedance.Theuserdoes
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control
devicewillautomaticallyplaceitsFFflagoutputintoHigh-Impedancewhennone
ofitsqueuesareselectedforwriteoperations.
TABLE 3 — BUS-MATCHING SET-UP
IW
OW
Write Port
Read Port
Whenqueueswithinasingledeviceareselectedforwriteoperations,theFF
flagoutputofthatdevicewillmaintaincontroloftheFFflagbus.ItsFFflagwill
simplyupdatebetweenqueueswitchestoshowtherespectivequeuefullstatus.
Themulti-queuedeviceplacesitsFFflagoutputintoHigh-Impedancebased
onthe3bitIDcodefoundinthe3mostsignificantbitsofthewritequeueaddress
0
0
1
1
0
1
0
1
x18
x18
x9
x18
x9
x18
x9
x9
21
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
bus,WRADD.Ifthe3mostsignificantbitsofWRADDmatchthe3bitIDcodesetup simplyupdatebetweenqueueswitchestoshowtherespectivequeueoutput
onthestaticinputs,ID0,ID1andID2thentheFFflagoutputoftherespective validstatus.
devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheFFflag
Themulti-queuedeviceplacesitsOVflagoutputintoHigh-Impedancebased
outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure onthe3bitIDcodefoundinthe3mostsignificantbitsofthereadqueueaddress
12,FullFlagTiminginExpansionModefordetailsofflagoperation,including bus,RDADD.Ifthe3mostsignificantbitsofRDADDmatchthe3bitIDcodesetup
when more than one device is connected in expansion.
onthestaticinputs,ID0,ID1andID2thentheOVflagoutputoftherespective
devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheOVflag
outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure
OUTPUTVALIDFLAGOPERATION
The multi-queue flow-control device provides a single Output Valid flag 14,OutputValidFlagTimingfordetailsofflagoperation,includingwhenmore
output,OV.TheOVprovidesanemptystatusordataoutputvalidstatusforthe thanone device is connectedinexpansion.
datawordcurrentlyavailableontheoutputregisterofthereadport.Therising
edgeofanRCLKcyclethatplacesnewdataontotheoutputregisteroftheread ALMOST FULL FLAG
port, also updates the OV flag to show whether or not that new data word is
As previously mentioned the multi-queue flow-control device provides a
actually valid. Internally the multi-queue flow-control device monitors and singleProgrammableAlmostFullflagoutput,PAF.ThePAFflagoutputprovides
maintainsastatusoftheemptyconditionofallqueueswithinit,howeveronly astatusofthealmostfullconditionfortheactivequeuecurrentlyselectedonthe
thequeuethatisselectedforreadoperationshasitsoutputvalid(empty)status writeportforwriteoperations.Internallythemulti-queueflow-controldevice
outputtotheOVflag,givingavalidstatusforthewordbeingreadatthattime. monitorsandmaintainsastatusofthealmostfullconditionofallqueueswithin
Thenatureofthefirstwordfallthroughoperationmeansthatwhenthelast it,howeveronlythequeuethatisselectedforwriteoperationshasitsfullstatus
datawordisreadfromaselectedqueue,theOVflagwillgoHIGHonthenext outputtothePAFflag.Thisdedicatedflagisoftenreferredtoasthe“activequeue
enabled read, that is, on the next rising edge of RCLK while REN is LOW.
almostfullflag”.ThepositionofthePAFflagboundarywithinaqueuecanbe
Whenqueueswitchesarebeingmadeonthereadport,theOVflagwillswitch atanypointwithinthatqueuesdepth.Thislocationcanbeuserprogrammed
toshowstatusofthenewqueueinlinewiththedataoutputfromthenewqueue. viatheserialportoroneofthedefaultvalues(8or128)canbeselectedifthe
Whenaqueueselectionismadethefirstdatafromthatqueuewillappearon userhasperformeddefaultprogramming.
theQoutdataoutputs3RCLKcycleslater,theOVwillchangestatetoindicate
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost
validityofthedatafromthenewlyselectedqueueonthis3rd RCLKcyclealso. fullstatus,whenaqueueisselectedonthewriteport,thisstatusisoutputviathe
Thepreviouscycleswillcontinuetooutputdatafromthepreviousqueueand PAFflag.ThePAFflagvalueforeachqueueisprogrammedduringmulti-queue
theOVflagwillindicatethestatusofthoseoutputs.Again,theOVflagalways device programming (along with the number of queues, queue depths and
indicatesstatusforthedatacurrentlypresentontheoutputregister.
almostemptyvalues).ThePAFoffsetvalue,m,forarespectivequeuecanbe
TheOVflagissynchronoustotheRCLKandalltransitionsoftheOVflagoccur programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory
basedonarisingedgeofRCLK.Internallythemulti-queuedevicemonitorsand depthforthatqueue.ThePAFvalueofdifferentqueueswithinthesamedevice
keepsarecordoftheoutputvalid(empty)statusforallqueues.Itispossiblethat canbedifferentvalues.
thestatusofanOVflagmaybechanginginternallyeventhoughthatrespective
Whenqueueswitchesarebeingmadeonthewriteport,thePAFflagoutput
flagisnottheactivequeueflag(selectedonthereadport).Aqueueselected willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
onthewriteportmayexperienceachangeofitsinternalOVflagstatusbased onthethirdcycleafteranewqueueselectionismade,onthesameWCLKcycle
on write operations, that is, data may be written into that queue causing it to thatdata canactuallybe writtentothe newqueue. Thatis, a newqueue can
become“notempty”.
beselectedonthewriteportviatheWRADDbus,WADENenableandarising
SeeFigure13,ReadQueueSelect,ReadOperationandFigure14,Output edgeofWCLK.OnthethirdrisingedgeofWCLKfollowingaqueueselection,
ValidFlagTimingfordetailsofthetiming.
thePAFflagoutputwillshowthefullstatusofthenewlyselectedqueue.ThePAF
isflagoutputistripleregisterbuffered,sowhenawriteoperationoccursatthe
almostfullboundarycausingtheselectedqueuestatustogoalmostfullthePAF
EXPANSION MODE – OUTPUT VALID FLAG OPERATION
Whenmulti-queuedevicesareconnectedinExpansionmode,theOVflags willgoLOW3WCLKcyclesafterthewrite.Thesameistruewhenareadoccurs,
of all devices should be connected together, such that a system controller there will be a 3 WCLK cycle delay after the read operation.
monitoring and managing the multi-queue devices read port only looks at a
singleOVflag(asopposedtoadiscreteOVflagforeachdevice).ThisOVflag
is onlypertinenttothequeuebeingselectedforreadoperations atthattime.
Remember,thatwheninexpansionmodeonlyonemulti-queuedevicecanbe
readfromatanymomentintime,thustheOVflagprovidesstatusoftheactive
queue on the read port.
So the PAF flag delays are:
froma write operationtoPAF flagLOWis 2WCLK+tWAF
ThedelayfromareadoperationtoPAFflagHIGHistSKEW2+WCLK+tWAF
Note, if tSKEW is violated there will be one added WCLK cycle delay.
ThePAFflagissynchronoustotheWCLKandalltransitionsofthePAFflag
occur based on a rising edge of WCLK. Internally the multi-queue device
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheOVflag monitorsandkeepsarecordofthealmostfullstatusforallqueues.Itispossible
outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis thatthestatusofaPAFflagmaybechanginginternallyeventhoughthatflagis
madeonlyasingledevicedrivestheOVflagbusandallotherOVflagoutputs nottheactivequeueflag(selectedonthewriteport).Aqueueselectedonthe
connectedtotheOVflagbusareplacedintoHigh-Impedance.Theuserdoes readportmayexperienceachangeofitsinternalalmostfullflagstatusbased
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control on read operations. The multi-queue flow-control device also provides a
devicewillautomaticallyplaceitsOVflagoutputintoHigh-Impedancewhennone duplicateofthePAFflagonthePAF[7:0]flagbus,thiswillbediscussedindetail
ofitsqueuesareselectedforreadoperations.
inalatersectionofthedatasheet.
Whenqueueswithinasingledeviceareselectedforreadoperations,theOV
flagoutputofthatdevicewillmaintaincontroloftheOVflagbus.ItsOVflagwill
SeeFigures 19and20forAlmostFullflagtimingandqueueswitching.
22
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ALMOSTEMPTYFLAG
nottheactivequeueflag(selectedonthereadport).Aqueueselectedonthe
As previously mentioned the multi-queue flow-control device provides a writeportmayexperienceachangeofitsinternalalmostemptyflagstatusbased
single Programmable Almost Empty flag output, PAE. The PAE flag output on write operations. The multi-queue flow-control device also provides a
providesastatusofthealmostemptyconditionfortheactivequeuecurrently duplicateofthePAEflagonthePAE[7:0]flagbus,thiswillbediscussedindetail
selectedonthereadportforreadoperations.Internallythemulti-queueflow- inalatersectionofthedatasheet.
controldevicemonitorsandmaintainsastatusofthealmostemptyconditionof
allqueueswithinit,howeveronlythequeuethatisselectedforreadoperations
SeeFigures21and22forAlmostEmptyflagtimingandqueueswitching.
hasitsemptystatusoutputtothePAEflag.Thisdedicatedflagisoftenreferred POWER DOWN (PD)
toasthe“activequeuealmostemptyflag”.ThepositionofthePAEflagboundary
This device has a power down feature intended for reducing power
withinaqueuecanbeatanypointwithinthatqueuesdepth.Thislocationcan consumptionforHSTL/eHSTLconfiguredinputswhenthedeviceisidlefora
beuserprogrammedviatheserialportoroneofthedefaultvalues(8or128) long period of time. By entering the power down state certain inputs can be
canbeselectediftheuserhasperformeddefaultprogramming.
disabled,therebysignificantlyreducingthepowerconsumptionofthepart.All
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost WENandRENsignalsmustbedisabledforaminimumoffourWCLKandRCLK
emptystatus,whenaqueueisselectedonthereadport,thisstatusisoutputvia cycles before activating the power down signal. The power down signal is
thePAEflag.ThePAEflagvalueforeachqueueisprogrammedduringmulti- asynchronousandneedstobeheldLOWthroughoutthedesiredpowerdowntime.
queuedeviceprogramming(alongwiththenumberofqueues,queuedepths Duringpowerdown,thefollowingconditionsfortheinputs/outputssignalsare:
andalmostfullvalues).ThePAEoffsetvalue,n,forarespectivequeuecanbe
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory
depthforthatqueue.ThePAEvalueofdifferentqueueswithinthesamedevice
canbedifferentvalues.
• Alldata inQueue(s)memoryare retained.
• Alldatainputsbecomeinactive.
• Allwrite andreadpointers maintaintheirlastvalue before powerdown.
• Allenables,chipselects,andclockinputpinsbecomeinactive.
• Alldataoutputsbecomeinactiveandenterhigh-impedancestate.
• Allflagoutputswillmaintaintheircurrentstatesbeforepowerdown.
• Allprogrammableflagoffsetsmaintaintheirvalues.
• Allechoclocks andenables willbecomeinactiveandenterhigh-
impedancestate.
• TheserialprogrammingandJTAGportwillbecomeinactiveandenter
high-impedancestate.
• AllsetupandconfigurationCMOSstaticinputsarenotaffected,asthese
pins are tied to a known value and do not toggle during operation.
Allinternalcounters,registers,andflagswillremainunchangedandmaintain
Whenqueueswitchesarebeingmadeonthereadport,thePAEflagoutput
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
onthethirdcycleafteranewqueueselectionismade,onthesameRCLKcycle
thatdataactuallyfallsthroughtotheoutputregisterfromthenewqueue.That
is,anewqueuecanbeselectedonthereadportviatheRDADDbus,RADEN
enableandarisingedgeofRCLK.OnthethirdrisingedgeofRCLKfollowing
a queue selection, the data wordfromthe newqueue willbe available atthe
outputregisterandthePAEflagoutputwillshowtheemptystatusofthenewly
selectedqueue.ThePAEisflagoutputistripleregisterbuffered,sowhenaread
operationoccurs atthealmostemptyboundarycausingtheselectedqueue
statustogoalmostemptythePAEwillgoLOW3RCLKcyclesaftertheread. theircurrentstatepriortopowerdown.Clockinputscanbecontinuousandfree-
Thesameistruewhenawriteoccurs,therewillbea3RCLKcycledelayafter runningduringpowerdown,butwillhavenoaffectonthepart.However,itis
thewriteoperation.
So the PAE flag delays are:
from a read operation to PAE flag LOW is 2 RCLK + tRAE
ThedelayfromawriteoperationtoPAEflagHIGHistSKEW2+RCLK+tRAE readandwriteoperationscanresume.Thedevicewillcontinuefromwhereit
Note, if tSKEW is violated there will be one added RCLK cycle delay.
recommendedthattheclockinputsbelowwhenthepowerdownisactive.To
exitpowerdownstateandresumenormaloperations,disablethepowerdown
signalbybringingitHIGH.Theremustbeaminimumof1µswaitingperiodbefore
hadstoppedandnoformofresetisrequiredafterexitingpowerdownstate.The
ThePAEflagissynchronoustotheRCLKandalltransitionsofthePAEflag powerdownfeaturedoesnotprovideanypowersavingswhentheinputsare
occur based on a rising edge of RCLK. Internally the multi-queue device configuredforLVTTLoperation.However,itwillreducethecurrentforI/Osthat
monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible are not tied directly to VCC or GND. See Figure 30, Power Down Operation,
thatthestatusofaPAEflagmaybechanginginternallyeventhoughthatflagis fortheassociatedtimingdiagram.
23
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING
Output Valid, OV Flag Boundary
Full Flag, FF Boundary
I/O Set-Up
OV Boundary Condition
I/O Set-Up
FF Boundary Condition
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenotebelowfortiming)
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after D+1 Writes
(seenotebelowfortiming)
OV Goes LOW after 1st Write
(seenotebelowfortiming)
In18 to out18 or In9 to out9
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after D Writes
(seenotebelowfortiming)
In18 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenotebelowfortiming)
In18 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after D Writes
(seenotebelowfortiming)
In9 to out18
(Bothportsselectedforsamequeue
when the 1st Word is written in)
In18 to out9
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after D Writes
(seenotebelowfortiming)
NOTE:
1. OV Timing
Assertion:
Write to OV LOW: tSKEW1 + RCLK + tROV
If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tROV
De-assertion:
In9 to out18
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after ([D+1] x 2) Writes
(seenotebelowfortiming)
Read Operation to OV HIGH: tROV
In9 to out18
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after (D x 2) Writes
(seenotebelowfortiming)
NOTE:
D = Queue Depth
FF Timing
Assertion:
Write Operation to FF LOW: tWFF
De-assertion:
Read to FF HIGH: tSKEW1 + tWFF
If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
I/O Set-Up
PAF & PAFn Boundary
In18 to out18 or In9 to out9
PAF/PAFn Goes LOW after
(Bothportsselectedforsamequeuewhenthe1st D+1-mWrites
Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)
In18 to out18 or In9 to out9
(Writeportonlyselectedforsamequeuewhenthe D-mWrites
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
PAF/PAFn Goes LOW after
In18 to out9
In9 to out18
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
PAF/PAFn Goes LOW after
([D+1-m] x 2) Writes
(seenotebelowfortiming)
NOTE:
D = Queue Depth
m = Almost Full Offset value.
Default values: if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
PAF Timing
Assertion:
Write Operation to PAF LOW: 2 WCLK + tWAF
De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF
PAFn Timing
Assertion:
Write Operation to PAFn LOW: 2 WCLK* + tPAF
De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
24
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Programmable Almost Empty Flag, PAE Boundary
Programmable Almost Empty Flag Bus, PAEn Boundary
I/O Set-Up
PAE Assertion
PAE Goes HIGH after n+2
I/O Set-Up
PAEn Boundary Condition
PAEn Goes HIGH after
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeuewhenthe1st Writes
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeuewhenthe1st n+2Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
In18 to out18 or In9 to out9
(Writeportonlyselectedforsamequeuewhenthe n+1Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
PAEn Goes HIGH after
In18 to out9
PAE Goes HIGH after n+1
(Bothportsselectedforsamequeuewhenthe1st Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
In18 to out9
In9 to out18
PAEn Goes HIGH after n+1
In9 to out18
PAE Goes HIGH after
Writes (seebelowfortiming)
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
PAEn Goes HIGH after
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
NOTE:
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
In9 to out18
PAEn Goes HIGH after
(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 2) Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
PAE Timing
Assertion:
Read Operation to PAE LOW: 2 RCLK + tRAE
NOTE:
De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAEn Timing
Assertion:
De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE
Read Operation to PAEn LOW: 2 RCLK* + tPAE
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
25
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PAFn FLAG BUS OPERATION
quadrantswithinthedeviceregardlessofhowmanyqueueshavebeensetup
The IDT72T51543/72T51553 multi-queue flow-control devices can be inthepart.EveryrisingedgeoftheWCLKcausesthenextquadranttobeloaded
configuredforupto32queues,eachqueuehavingitsownalmostfullstatus. onthePAFnbus.Thedeviceconfiguredasthemaster(MASTinputtiedHIGH),
Anactivequeuehasitsflagstatusoutputtothediscreteflags,FFandPAF,on willtakecontrolofthePAFnafterMRSgoesLOW.ForthewholeWCLKcycle
thewriteport.Queuesthatarenotselectedforawriteoperationcanhavetheir thatthe firstquadrantis onPAFntheFSYNC(PAFnbus sync)outputwillbe
PAFstatus monitoredviathe PAFnbus.ThePAFnflagbus is 8bits wide,so HIGH, forallotherquadrants, this FSYNCoutputwillbe LOW. This FSYNC
that8queuesatatimecanhavetheirstatusoutputtothebus.If9ormorequeues outputprovides the userwitha markwithwhichtheycansynchronize tothe
aresetupwithinadevicethenthereare2methodsbywhichthedevicecanshare PAFnbus,FSYNCisalwaysHIGHfortheWCLKcyclethatthefirstquadrant
thebusbetweenqueues,"Direct"modeand"Polled"modedependingonthe of a device is present on the PAFn bus.
state ofthe FM(FlagMode)inputduringa MasterReset. If8orless queues
When devices are connected in expansion mode, only one device will be
aresetupwithinadevicetheneachwillhaveitsowndedicatedoutputfromthe setastheMaster,MASTinputtiedHIGH,allotherdeviceswillhaveMASTtied
bus.Itisrecommendedif8orlessqueuesaresetupinsingledevicemodeto LOW.ThemasterdeviceisthefirstdevicetotakecontrolofthePAFnbusand
configure the PAFnbus topolledmode as itdoes notrequire usingthe write willplaceitsfirstquadrantonthebusontherisingedgeofWCLKaftertheMRS
address(WRADD).
inputgoesHIGH.Forthenext3WCLKcyclesthemasterdevicewillmaintain
controlofthePAFnbusandcycleitsquadrantsthroughit,allotherdeviceshold
theirPAFnoutputsinHigh-Impedance.Whenthemasterdevicehascycledall
PAFn - DIRECT BUS
IfFMisLOWatmasterresetthenthePAFnbusoperatesinDirect(addressed) ofitsquadrantsitpassesatokentothenextdeviceinthechainandthatdevice
mode.Indirectmodetheusercanaddressthequadrantofqueuestheyrequire assumescontrolofthePAFnbusandthencyclesitsquadrantsandsoon,the
tobe placedontothe PAFnbus. Forexample, considerthe operationofthe PAFn bus control token being passed on from device to device. This token
PAFn bus when 26 queues have been setup. To output status of the first passing is done via the FXO outputs and FXI inputs of the devices (“PAF
quadrant,Queue[0:7]theWRADDbus is usedinconjunctionwiththeFSTR ExpansionOut”and“PAFExpansionIn”).TheFXOoutputofthemasterdevice
(PAFflagstrobe)inputandWCLK.Theaddresspresentonthe2leastsignificant connectstotheFXIoftheseconddeviceinthechainandtheFXOofthesecond
bitsoftheWRADDbuswithFSTRHIGHwillbeselectedasthequadrantaddress connectstotheFXIofthethirdandsoon.ThefinaldeviceinachainhasitsFXO
onarisingedgeofWCLK.Sotoaddressquadrant1,Queue[0:7]theWRADD connectedtotheFXIofthefirstdevice,sothatoncethePAFnbushascycled
busshouldbeloadedwith“xxxxxx00”,thePAFnbuswillchangestatustoshow throughallquadrantsofalldevices,controlofthePAFnwillpasstothemaster
thenewquadrantselected1WCLKcycleafterquadrantselection.PAFn[0:7] device again and so on. The FSYNC of each respective device will operate
getsstatusofqueues,Queue[0:7]respectively.
To address the second quadrant, Queue[8:15], the WRADD address is ofthe bus andis placingits firstquadrantontothe PAFnbus.
WhenoperatinginsingledevicemodetheFXIinputmustbeconnectedto
independentlyandsimplyindicatewhenthatrespectivedevicehastakencontrol
“xxxxxx01”. PAFn[0:7] gets status of queues, Queue[8:15] respectively. To
addressthethirdquadrant,Queue[16:23],theWRADDaddressis“xxxxxx10”. theFXOoutputofthesamedevice.Insingledevicemodeatokenisstillrequired
PAF[0:7]gets status ofqueues, Queue[16:23]respectively. Toaddress the tobe passedintothe device foraccessingthePAFnbus.
fourthquadrant,Queue[24:31],theWRADDaddressis“xxxxxx11”.PAF[0:1]
getsstatusofqueues,Queue[24:25]respectively.Remember,only26queues
PleaserefertoFigure28,PAFnBus–PolledModefortiminginformation.
weresetup,sowhenquadrant4isselectedtheunusedoutputsPAF[2:7]will PAEn FLAG BUS OPERATION
bedon'tcarestates.
The IDT72T51543/72T51553 multi-queue flow-control devices can be
Note, that if a read or write operation is occurring to a specific queue, say configuredforupto32queues,eachqueuehavingitsownalmostemptystatus.
queue‘x’onthesamecycleasaquadrantswitchwhichwillincludethequeue Anactivequeuehasitsflagstatusoutputtothediscreteflags,OVandPAE,on
‘x’,thentheremaybeanextraWCLKcycledelaybeforethatqueuesstatusis thereadport.Queuesthatarenotselectedforareadoperationcanhavetheir
correctlyshownontherespectiveoutputofthePAFnbus.However,theactive PAEstatusmonitoredviathePAEnbus.ThePAEnflagbusis8bitswide,so
PAFflagwillshowcorrectstatusatalltimes.
that8queuesatatimecanhavetheirstatusoutputtothebus. If9ormorequeues
Quadrantscanbeselectedonconsecutiveclockcycles,thatisthequadrant aresetupwithinadevicethenthereare2methodsbywhichthedevicecanshare
onthePAFnbuscanchangeeveryWCLKcycle.Also,datapresentontheinput thebusbetweenqueues,"Direct"modeand"Polled"modedependingonthe
bus, Din, can be written into a queue on the same WCLK rising edge that a state ofthe FM(FlagMode)inputduringa MasterReset. If8orless queues
quadrantisbeingselected,theonlyrestrictionbeingthatawritequeueselection aresetupwithinadevicetheneachwillhaveitsowndedicatedoutputfromthe
andPAFnquadrantselectioncannotbemadeonthesamecycle.
bus.Itisrecommendedif8orlessqueuesaresetupinsingledevicemodeto
If8orlessqueuesaresetupthenqueues,Queue[0:7]havetheirPAFstatus configure the PAFnbus topolledmode as itdoes notrequire usingthe write
outputonPAF[0:7]constantly.
Whenthemulti-queuedevicesareconnectedinexpansionofmorethanone
address(WRADD).
devicethePAFnbussesofalldevicesareconnectedtogether,whenswitching PAEn - DIRECT BUS
betweenquadrantsofdifferentdevicestheusermustutilizethe3mostsignificant
IfFMisLOWatmasterresetthenthePAEnbusoperatesinDirect(addressed)
bits of the WRADD address bus (as well as the 2 LSB’s). These 3 MSB’s mode.Indirectmodetheusercanaddressthequadrantofqueuestheyrequire
correspondtothedeviceIDinputs,whicharethestaticinputs,ID0,ID1&ID2. tobe placedontothe PAEnbus. Forexample, considerthe operationofthe
PleaserefertoFigure25PAFn-DirectModeQuadrantSelectionfortiming PAEn bus when 26 queues have been setup. To output status of the first
information. AlsorefertoTable 1, WriteAddress Bus, WRADD.
quadrant, Queue[0:7]the RDADDbus is usedinconjunctionwiththe ESTR
(PAEflagstrobe)inputandRCLK.Theaddresspresentonthe2leastsignificant
bitsoftheRDADDbuswithESTRHIGHwillbeselectedasthequadrantaddress
PAFn – POLLED BUS
IfFMisHIGHatmasterresetthenthePAFnbusoperatesinPolled(looped) onarisingedgeofRCLK.Sotoaddressquadrant1,Queue[0:7]theRDADD
mode. In polled mode the PAFn bus automatically cycles through the 4 busshouldbeloadedwith“xxxxxx00”,thePAEnbuswillchangestatustoshow
26
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
thenewquadrantselected1RCLKcycleafterquadrantselection.PAEn[0:7] quadrantswithinthedeviceregardlessofhowmanyqueueshavebeensetup
getsstatusofqueues,Queue[0:7]respectively. inthepart.EveryrisingedgeoftheRCLKcausesthenextquadranttobeloaded
To address the second quadrant, Queue[8:15], the RDADD address is onthePAEnbus.Thedeviceconfiguredasthemaster(MASTinputtiedHIGH),
“xxxxxx01”. PAEn[0:7]gets status ofqueues, Queue[8:15]respectively. To willtakecontrolofthePAEnafterMRSgoesLOW.ForthewholeRCLKcycle
addressthethirdquadrant,Queue[16:23],theRDADDaddressis“xxxxxx10”. thatthefirstquadrantis onPAEntheESYNC(PAEnbussync)outputwillbe
PAE[0:7]gets status ofqueues, Queue[16:23]respectively. Toaddress the HIGH, forallotherquadrants, this ESYNCoutputwillbe LOW. This ESYNC
fourthquadrant,Queue[24:31],theRDADDaddressis“xxxxxx11”.PAE[0:1] outputprovides the userwitha markwithwhichtheycansynchronize tothe
getsstatusofqueues,Queue[24:25]respectively.Remember,only26queues PAEnbus,ESYNCisalwaysHIGHfortheRCLKcyclethatthefirstquadrant
weresetup,sowhenquadrant4isselectedtheunusedoutputsPAE[2:7]will of a device is present on the PAEn bus.
bedon'tcarestates.
When devices are connected in expansion mode, only one device will be
Note, that if a read or write operation is occurring to a specific queue, say setastheMaster,MASTinputtiedHIGH,allotherdeviceswillhaveMASTtied
queue‘x’onthesamecycleasaquadrantswitchwhichwillincludethequeue LOW.ThemasterdeviceisthefirstdevicetotakecontrolofthePAEnbusand
‘x’,thentheremaybeanextraRCLKcycledelaybeforethatqueuesstatusis willplaceitsfirstquadrantonthebusontherisingedgeofRCLKaftertheMRS
correctlyshownontherespectiveoutputofthePAEnbus.
inputgoesLOW.Forthenext3RCLKcyclesthemasterdevicewillmaintain
Quadrantscanbeselectedonconsecutiveclockcycles,thatisthequadrant controlofthePAEnbusandcycleitsquadrantsthroughit,allotherdeviceshold
on the PAEn bus can change every RCLK cycle. Also, data can be read out theirPAEnoutputsinHigh-Impedance.Whenthemasterdevicehascycledall
ofa queue onthe same RCLKrisingedge thata quadrantis beingselected, ofitsquadrantsitpassesatokentothenextdeviceinthechainandthatdevice
the only restriction being that a read queue selection and PAEn quadrant assumescontrolofthePAEnbusandthencyclesitsquadrantsandsoon,the
selectioncannotbemadeonthesameRCLKcycle.
If8orlessqueuesaresetupthenqueues,Queue[0:7]havetheirPAEstatus passing is done via the EXO outputs and EXI inputs of the devices (“PAE
outputonPAE[0:7]constantly. ExpansionOut”and“PAEExpansionIn”).TheEXOoutputofthemasterdevice
PAEn bus control token being passed on from device to device. This token
Whenthemulti-queuedevicesareconnectedinexpansionofmorethanone connectstotheEXIoftheseconddeviceinthechainandtheEXOofthesecond
devicethePAEnbussesofalldevicesareconnectedtogether,whenswitching connectstotheEXIofthethirdandsoon.ThefinaldeviceinachainhasitsEXO
betweenquadrantsofdifferentdevicestheusermustutilizethe3mostsignificant connectedtotheEXIofthefirstdevice,sothatoncethePAEnbushascycled
bits of the RDADD address bus (as well as the 2 LSB’s). These 3 MSB’s throughallquadrantsofalldevices,controlofthePAEnwillpasstothemaster
correspondtothedeviceIDinputs,whicharethestaticinputs,ID0,ID1&ID2. device again and so on. The ESYNC of each respective device will operate
PleaserefertoFigure24,PAEn-DirectModeQuadrantSelectionfortiming independentlyandsimplyindicatewhenthatrespectivedevicehastakencontrol
information. AlsorefertoTable 2, ReadAddress Bus, RDADD.
ofthebus andis placingits firstquadrantontothePAEnbus.
WhenoperatinginsingledevicemodetheEXIinputmustbeconnectedto
theEXOoutputofthesamedevice.Insingledevicemodeatokenisstillrequired
PAEn – POLLED BUS
IfFMisHIGHatmasterresetthenthePAEnbusoperatesinPolled(looped) tobepassedintothedeviceforaccessingthePAEnbus.
mode. In polled mode the PAEn bus automatically cycles through the 4 PleaserefertoFigure29,PAEnBus–PolledModefortiminginformation.
27
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ECHO READ CLOCK (ERCLK)
slowerthantheslowestQn,dataoutput.RefertoFigure3,EchoReadClock
TheEchoReadClockoutputisprovidedinbothHSTLandLVTTLmode, and Data Output Relationship and Figure 23, Echo RCLK & Echo REN
selectableviaIOSEL.TheERCLKisafree-runningclockoutput,itwillalways Operationfortiminginformation.
follow the RCLK input regardless of REN and RADEN.
TheERCLKoutputfollowstheRCLKinputwithanassociateddelay. This ECHO READ ENABLE (EREN)
delayprovidestheuserwithamoreeffectivereadclocksourcewhenreading
TheEchoReadEnableoutputisprovidedinbothHSTLandLVTTLmode,
data from the Qn outputs. This is especially helpful at high speeds when selectableviaIOSEL.
variableswithinthedevicemaycausechangesinthedataaccesstimes. These
The EREN output is provided to be used in conjunction with the ERCLK
variations in access time maybe caused by ambient temperature, supply outputandprovidesthereadingdevicewithamoreeffectiveschemeforreading
voltage,devicecharacteristics.TheERCLKoutputalsocompensatesforany datafromtheQnoutputportathighspeeds.TheERENoutputiscontrolledby
tracelengthdelaysbetweentheQndataoutputsandreceivingdevicesinputs. internallogicthatbehavesasfollows:TheERENoutputisactiveLOWforthe
Anyvariationseffectingthedataaccesstimewillalsohaveacorresponding RCLKcyclethatanewwordisreadoutofthequeue.Thatis,arisingedgeof
effect on the ERCLK output produced by the queue device, therefore the RCLKwillcause EREN togoactive (LOW)ifRENis active andthe queue is
ERCLKoutputleveltransitionsshouldalwaysbeatthesamepositionintime NOTempty.
relativetothedataoutputs.Note,thatERCLKisguaranteedbydesigntobe
RCLK
tERCLK
tERCLK
ERCLK
tD
tA
Q
SLOWEST(3)
5999 drw07
NOTES:
1. REN is LOW. OE is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
Figure 3. Echo Read Clock and Data Output Relationship
28
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
B
Write to Queue
A
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE
IW
L
OW
L
A
B
Read from Queue
L
(a) x18 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
L
B
A
Read from Queue
H
(b) x18 INPUT to x18 OUTPUT - LITTLE ENDIAN
Q8-Q0
Q17-Q9
Q17-Q9
BE
IW
L
OW
H
A
1st: Read from Queue
2nd: Read from Queue
L
Q8-Q0
B
(c) x18 INPUT to x9 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
H
B
1st: Read from Queue
H
Q17-Q9
Q8-Q0
A
2nd: Read from Queue
(d) x18 INPUT to x9 OUTPUT - LITTLE ENDIAN
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
A
1st: Write to Queue
2nd: Write to Queue
D17-Q9
D8-Q0
B
BYTE ORDER ON OUTPUT PORT:
Q17-Q9
Q8-Q0
BE
IW OW
A
B
Read from Queue
L
H
L
(a) x9 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
H
OW
L
A
B
Read from Queue
H
(a) x9 INPUT to x18 OUTPUT - LITTLE ENDIAN
5999 drw08
Figure 4. Bus-Matching Byte Arrangement
29
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
MRS
t
RSS
RSS
WEN
REN
t
tRSR
SENI
tRSS
FSTR,
ESTR
tRSS
WADEN,
RADEN
t
RSS
RSS
RSS
ID0, ID1,
ID2
t
OW, IW
FM
t
HIGH = Looped
LOW = Strobed (Direct)
tRSS
HIGH = Master Device
LOW = Slave Device
MAST
DFM
t
RSS
RSS
HIGH = Default Programming
LOW = Serial Programming
t
HIGH = Offset Value is 128
LOW = Offset value is 8
DF
t
t
t
t
RSF
HIGH-Z if Slave Device
FF
LOGIC "0" if Master Device
RSF
RSF
RSF
LOGIC "1" if Master Device
OV
PAF
PAE
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
HIGH-Z if Slave Device
LOGIC "0" if Master Device
t
RSF
RSF
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PAFn
PAEn
t
HIGH-Z if Slave Device
LOGIC "0" if Master Device
tRSF
LOGIC "1" if OE is LOW and device is Master
Qn
HIGH-Z if OE is HIGH or Device is Slave
5999 drw09
NOTES:
1. OE can toggle during this period.
2. PRS should be HIGH during a MRS.
Figure 5. Master Reset
30
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
w-3
w-2
w-1
w
w+1
w+2
w+3
WCLK
tQH
tQS
WADEN
WEN
tENS
tENS
tAS
tAH
WRADD
Qx
tWFF
FF
tWAF
PAF
tPAF
Active Bus
PAF-Qx(5)
tPRSS
tPRSH
PRS
tPRSH
tPRSS
RCLK
tENS
tENS
REN
tQS
tQH
RADEN
tAS
tAH
RDADD
Qx
tROV
OV
tRAE
PAE
tPAE
Active Bus
PAE-Qx(6)
r-2
r-1
r
r+1
r+2
r+3
r+4
5999 drw10
NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 3 clock cycles before the Partial Reset takes place, on both the write and read ports.
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
Figure 6. Partial Reset
Master Reset
Default Mode
DFM = 0
MRS
MRS
MRS
DFM
DFM
DFM
MQ2
MQn
MQ1
Serial Loading
Complete
SENI
SENO
SO
SENI
SENI
SENO
SO
SENO
SO
Serial Enable
Serial Input
SI
SI
SI
SCLK
SCLK
SCLK
5999 drw11
Serial Clock
Figure 7. Serial Port Connection for Serial Programming
31
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
32
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
33
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
34
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
tENH
tENS
WEN
tDS
tDH
tDS
tDH
tDS
tDH
W3
W1
W2
Dn
tSKEW1
1
2
RCLK
REN
Qout
tENS
tA
tA
tA
Last Word Read Out of Queue
W1 Qy
FWFT
W2 Qy
FWFT
W3 Qy
tROV
tROV
OV
5999 drw15
NOTES:
1. Qy has previously been selected on both the write and read ports.
2. OE is LOW.
3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.
Figure 11. Write Operations & First Word Fall Through
35
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
36
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
37
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
*J*
RCLK
REN
tENS
tAS
tAH
tAS
tAH
RDADD
RADEN
D1
Q30
D1 Q15
tQS
tQH
tQH
tQS
t
A
tA
t
A
t
A
t
tOLZ
Qout
(Device 1)
D
1
Q
30
WD
Last Word
D
1
Q
15
D1
Q
15 We Last Word
W0 Q15
PFT We-1
D
1
t
ROV
tROV
tROV
ROV
t
OVLZ
HIGH-Z
OV
(Device 1)
tOVHZ
OV
(Device 2)
tSKEW1
WCLK
WEN
tENH
tENS
tAS
tAH
WRADD
D1 Q15
tQS
tQ
H
WADEN
Din
tDS
tDH
D
1
W
Q
15
0
5999 drw18
Cycle:
*A* Queue 30 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control
of Qout bus, its Qout outputs are in Low-Impedance. This diagram only shows the Qout outputs of device 1. (Reads are disabled).
*B* Reads are now enabled. A word from the previously selected queue of Device 2 will be read out.
*C* After a queue switch, there is a 3 RCLK latency for output data.
*D* The Qout of Device 1 goes to Low-Impedance and word Wd is read from Q30 of D1. This happens to be the last word of Q30. Device 2 places its Qout outputs into
High-Impedance, device 1 has control of the Qout bus. The OV flag of Device 2 goes to High-Impedance and Device 1 takes control of OV. The OV flag of Device 1 goes LOW
to show that Wd of Q30 is valid.
*E* Queue 15 of device 1 is selected for read operations. The last word of Q30 was read on the previous cycle, therefore OV goes HIGH to indicate that the data on the Qout is
not valid (Q30 was read to empty). Word, Wd remains on the output bus.
*F* The last word of Q30 remains on the Qout bus, OV is HIGH, indicating that this word has been previously read.
*G* The next word (We-1), available from the newly selected queue, Q15 of device 1 is now read out. This will occur regardless of REN, 2 RCLK cycles after queue selection
due to the FWFT operation. The OV flag updates 3 RCLK cycles after a queue selection.
*H* The last word, We is read from Q15, this queue is now empty.
*I* The OV flag goes HIGH to indicate that Q15 was read to empty on the previous cycle.
*J* Due to a write operation the OV flag goes LOW and data word W0 is read from Q15. The latency is: tSKEW1 + 1*RCLK + tROV.
Figure 14. Output Valid Flag Timing (In Expansion Mode)
38
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
39
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
EO
40
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SELECT
NULL QUEUE
NEW QUEUE
*D*
SELECT
*A*
*B*
*C*
*E*
*F*
*G*
RCLK
tAS
tAH
tAS
tAH
Don’t care
00000100
RDADD
RADEN
tQS
tQH
tQS
tQH
tAS
tAH
NULL-Q
tENS
tENH
REN
t
A
tA
tA
tA
t
A
Q4 W0
FWFT
Qout
OV
Q1 Wn-4
Q1 Wn-3
Q1 Wn-2
Q1 Wn-1
Q1 Wn
tROV
tROV
5999 drw21
NOTES:
1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words
from that queue.
2. Please see Figure 18, Null Queue Flow Diagram.
Cycle:
*A* Null Q of device 0 is selected, when word Wn-1 from previously selected Q1 is read.
*C* REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register.
Note: *B* and *C* are a minimum 3 RCLK cycles between queue selects.
*D* The Null Q is seen as an empty queue on the read side, therefore Wn of Q1 remains in the O/P register and OV goes HIGH. A new queue, Q4 is selected.
*G* 1st word, W0 of Q4 falls through present on the O/P register after 3 RCLK cycles after the queue select.
Figure 17. Read Operation and Null Queue Select
*A*
*B*
*C*
*D*
*E*
*F*
*G*
Null
Queue
Null
Queue
Queue 4
Memory
Queue 4
Memory
Queue 1
Memory
Queue 1
Memory
Null
Queue
Q1
Q1
Q1
Q1
Q1
Q4
Q4
Wn
Wn
Wn
Wn
Wn
W0
W1
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
Qn
Q1
Q1
Q1
Q1
Q1
Q4
Wn-2
Wn-1
Wn
Wn
Wn
Wn
W0
5999 drw22
Figure 18. Null Queue Flow Diagram
41
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
WCLK
WEN
2
1
tENH
tENS
tAS
tAH
tAS
tQS
tAH
WRADD
D1
Q5
D1 Q9
tQS
tQH
tQH
WADEN
Din
tDS
tDH
WD-m
D1 Q5
tWAF
tWAF
tAFLZ
HIGH-Z
PAF
(Device 1)
tFFHZ
PAF
(Device 2)
5999 drw23
Cycle:
*A* Queue 5 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* No write occurs.
*D* Word, Wd-m is written into Q5 causing the PAF flag to go from LOW to HIGH. The flag latency is 3 WCLK cycles + tWAF.
*E* Queue 9 in device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 3 WCLK + tWAF latency.
*F* The PAF flag goes LOW based on the write 2 cycles earlier.
*G* No write occurs.
*H* The PAF flag goes HIGH due to the queue switch to Q9.
Figure 19. Almost Full Flag Timing and Queue Switch
tCLKL
tCLKL
WCLK
WEN
PAF
1
2
1
tENS
tENH
tWAF
tWAF
D-(m+1) words
in Queue
D - (m+1) words in Queue
D - m words in Queue
tSKEW2
RCLK
tENS
tENH
5999 drw24
REN
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + tWAF
De-assertion: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there will be one extra WCLK cycle.
Figure 20. Almost Full Flag Timing
42
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
RCLK
REN
HIGH
AS
t
tAH
tAS
tAH
RDADD
D1
Q30
D1 Q15
tQS
tQH
tQH
tQS
RADEN
Qout
tA
tA
tA
tA
tOLZ
HIGH-Z
HIGH-Z
D1
Q30
Wn
D
1
Q30
Wn+1
D1
Q15
W0
D1 Q15 W1
tRAE
t
RAE
tAELZ
PAE
(Device 1)
tAEHZ
PAE
(Device 2)
HIGH-Z
5999 drw25
Cycle:
*A* Queue 30 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* No read occurs.
*D* The PAE flag output now switches to device 1. Word, Wn is read from Q30 due to the FWFT operation. This read operation from Q30 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*E* Q15 of device 1 is selected.
*F* The PAE flag goes LOW due to the read from Q30 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*G* Word, W0 is read from Q15 due to the FWFT operation.
*H* The PAE flag goes HIGH to show that Q15 is not almost empty.
Figure 21. Almost Empty Flag Timing and Queue Switch
tCLKL
tCLKH
WCLK
tENH
tENS
WEN
PAE
n+1 words in Queue
SKEW2
n+2 words in Queue
n+1 words in Queue
tRAE
t
tRAE
RCLK
1
2
tENS
tENH
5999 drw26
REN
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + tRAE
De-assertion: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there will be one extra RCLK cycle.
Figure 22. Almost Empty Flag Timing
43
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ERN
44
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
RCLK
tQS
tQH
t
QS
tQS
Quadrant 0
t
QH
tQH
Device 1
Device 1
Device 1
Quadrant 2
Quadrant 3
001xxx10
001xxx11
001xxx00
RDADD
ESTR
PAEn
tSTS
tSTH
tSTS
tSTH
tPAE
tPAE
tPAE
Device 1 Quadrant 2
Device 1 Quadrant 3
Device 1 Quadrant 0
5999 drw28
NOTES:
1. Quadrants can be selected on consecutive cycles.
2. On an RCLK cycle that the ESTR is HIGH, the RADEN input must be LOW.
3. There is a latency of 2 RCLK for the PAEn bus to switch.
Figure 24. PAEn - Direct Mode - Quadrant Selection
WCLK
tQS
tQH
t
QS
tQS
Quadrant 2
t
QH
tQH
Device 1
Device 1
Device 1
Quadrant 1
Quadrant 3
001xxx01
001xxx11
001xxx10
WRADD
FSTR
tSTS
tSTH
tSTS
tSTH
tPAF
tPAF
tPAF
PAFn
Device 1 Quadrant 1
Device 1 Quadrant 3
Device 1 Quadrant 2
5999 drw29
NOTES:
1. Quadrants can be selected on consecutive cycles.
2. On a WCLK cycle that the FSTR is HIGH, the WADEN input must be LOW.
3. There is a latency of 2 WCLK for the PAFn bus to switch.
Figure 25. PAFn - Direct Mode - Quadrant Selection
45
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
1
*C*
2
*D*
3
*E*
*F*
*G*
*H*
WCLK
WADEN
FSTR
tQS
tQH
tQS
tQH
t
QS
tQH
t
STS
tSTH
tENS
tENS
tENH
tENH
WEN
tAS
tAH
tAH
tAS
tAS
tAH
D4 quad 3
D3Q8
011 01000
WRADD
Dn
D5Q24
100 11000
tDS
tDH
tDS
t
DS
100 xxx10
t
DH
t
DH
Wp
Wp+1
Wp+2
Wn+1
D5Q24
Wn
Wx
D3 Q8
D5 Q24
Writes to Previous Q
t
SKEW3
RCLK
RADEN
ESTR
1
2
3
1
2
3
tQS
tQH
tSTS
t
STH
t
ENS
tENH
REN
tAH
tAS
tAS
tAH
RDADD
D5 quad 4
D5Q24
100 11000
101 xxx11
tA
tA
tA
tA
t
A
Wy+1
D5 Q24
Wy
D5 Q24
Wy+2
D5 Q24
Wy+3
D5 Q24
Device 5 -Qn
Wa
D5 Q17
Wa+1
D5 Q17
Previous value loaded on to PAE bus
Prev PAEn
tPAEHZ
tPAE
tPAEZL
xxxx xxx0
D5Quad4
xxxx xxx1
D5Quad 4
Device 5 PAEn
xxxx xxx0
D5Quad4
xxxx xxx1
D5Quad 4
Previous value loaded on to PAE bus
D5 Q17 Status
Bus PAEn
t
RAE
tRAE
tRAE
D5 Q24
status
Device 5 PAE
5999 drw30
*FF*
*AA*
*BB*
*CC*
*DD*
*GG*
*EE*
Cycle:
*A* Queue 24 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA* Queue 24 of Device 5 is selected for read operations.
A quadrant from another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
*B* Word Wp+1 is written into the previously selected queue.
*BB* Current Word is kept on the output bus since REN is HIGH.
*C* Word Wp+2 is written into the previously selected queue.
*CC* Word Wa+1 of D5 Q17 is read due to FWFT.
*D* Word, Wn is written into the newly selected queue, Q24 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added).
*DD* Word, Wy from the newly selected queue, Q24 will be read out due to FWFT operation.
Quadrant 4 of Device 5 is selected on the PAEn bus. Q24 of device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency before
the PAEn bus changes to the new selection.
*E* Queue 8 of Device 3 is selected for write operations.
Word Wn+1 is written into Q24 of D5.
*EE* Word, Wy+1 is read from Q24 of D5.
*F* No writes occur.
*FF* Word, Wy+2 is read from Q24 of D5.
The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and quadrant 4 is placed onto the outputs. The device of the previously selected
quadrant now places its PAEn outputs into High-Impedance to prevent bus contention.
The discrete PAE flag will go HIGH to show that Q24 of D5 is not almost empty. Q24 of device 5 will have its PAE status output on PAE[0].
*G* Quadrant 3 of device 4 is selected on the write port for the PAFn bus.
*GG* The PAEn bus updates to show that Q24 of D5 is almost empty based on the reading out of word, Wy+1.
The discrete PAE flag goes LOW to show that Q24 of D5 is almost empty based on the reading of Wy+1.
*H* Word, Wx is written into Q8 of D3.
Figure 26. PAEn - Direct Mode, Flag Operation
46
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK
tQH
tQS
tQS
tQH
RADEN
tSTH
tSTS
ESTR
REN
tAS
tAH
tAH
tAH
tAS
tAS
D7 quad 1
RDADD
D6Q2
D0Q31
110 00010
111 xxx00
000 11111
OE
tA
t
A
tA
tA
tOLZ
Qout
W
X
W
X +1
Prev. Q
W
D0 Q31
D - M + 2
W0
D6 Q2
W
D0 Q31
D-M+1
Prev. Q
t
SKEW3
WCLK
FSTR
1
2
3
tSTS
tSTH
tAS
tAH
tAS
tAH
WRADD
D0 quad4
000 xxx11
D0 Q31
tENS
tENH
WEN
tQS
tQH
WADEN
Din
t
DS
t
DH
tDS
t
DH
tDS
tDH
W
y+1
Wy+2
Word W
y
D0 Q31
D0 Q31
D0 Q31
tPAFLZ
tPAF
tPAF
Device 0 PAFn
0xxx xxxx
0xxx xxxx
1xxx xxxx
1xxx xxxx
0xxx xxxx
0xxx xxxx
D0Quad4
D0Quad4
D0Quad4
D0Quad4
D0Quad4
HIGH-Z
DXQuad y
D0Quad4
Bus PAFn
tPAFHZ
HIGH-Z
DXQuad y
Prev.
PAFn
tPAFLZ
tWAF
Device 0
HIGH - Z
5999 drw31
PAF
*AA*
*BB*
*CC*
*DD*
*EE*
*FF*
*GG*
Cycle:
*A* Queue 31 of device 0 is selected for read operations.
The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.
*AA* Quadrant 4 of device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected quadrant, Quad Y of device X.
*B* No read operation.
*BB* Queue 31 of device 0 is selected on the write port.
*C* Word, Wx+1 is read out from the previous queue due to the FWFT effect.
*CC* PAFn continues to show status of Quad4 D0.
The PAFn bus is updated with the quadrant selected on the previous cycle, D0 Quad 4. PAF[7] is LOW showing the status of queue 31.
The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
*D* A new quadrant, Quad 1 of Device 7 is selected for the PAFn bus.
Word, Wd-m+1 is read from Q31 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q31. This read will cause the PAF[7] output to go from
LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.
*DD* No write operation.
*E* No read operations occur, REN is HIGH.
*EE* PAF[7] goes HIGH to show that D0 Q31 is not almost empty due to the read on cycle *C*.
The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q31.
*F* Queue 2 of Device 6 is selected for read operations.
*FF* Word, Wy+1 is written into D0 Q31.
*G* Word, Wd-m+2 is read out due to FWFT operation.
*GG* PAF[7] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q31 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q31.
*H* No read operation.
*I* Word, W0 is read from Q0 of D6, selected on cycle *F*, due to FWFT.
Figure 27. PAFn - Direct Mode, Flag Operation
47
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
APF
48
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PAE
49
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
WEN
tDH
tDS
tDH
tDS
W
tDS
D12
tDH
tDS
D13
D10
WD11
W
W
D[39:0]
1ns
(1)
3
1
2
4
RCLK
REN
(7)
(2)
tPDHZ
tPDLZ
tA
tA
tA
tA
Hi-Z
tPDL
WD1
WD2
WD3
WD4
W
DH
WDS
Q[39:0]
(2)
tPDH
(2)
tPDH
PD
tERCLK
Hi-Z
Hi-Z
ERCLK
tEREN
tEREN
EREN
5999 drw34
NOTES:
1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted.
2. When the PD input becomes deasserted, there will be a 1µs waiting period before read and write operations can resume.
All input and output signals will also resume after this time period.
3. Set-up and configuration static inputs are not affected during power down.
4. Serial programming and JTAG programming port are inactive during power down.
5. RCS = 0, WCS = 0 and OE = 0. These signals can toggle during and after power down.
6. All flags remain active and maintain their current states.
7. During power down, all outputs will be in high-impedance.
Figure 30. Power Down Operation
50
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Serial Programming Data Input
Serial Enable
SENI
SI FXI EXI
Output Data Bus
Data Bus
Q
-Q
17
D
-D
17
0
0
Read Clock
Write Clock
RCLK
WCLK
Write Enable
Read Enable
WEN
REN
Read Queue Select
Read Address
Write Queue Select
Write Address
RDADD
RADEN
WRADD
WADEN
DEVICE
1
Empty Strobe
Full Strobe
ESTR
FSTR
PAFn
Programmable Almost Full
Programmable Almost Empty
PAEn
Empty Sync 1
Output Valid Flag
Almost Empty Flag
Full Sync1
ESYNC
OV
FSYNC
Full Flag
FF
Almost Full Flag
Serial Clock
PAF
PAE
SCLK
SENO SO FXO EXO
SENI SI FXI EXI
Q
-Q
17
D
-D
17
0
0
WCLK
RCLK
WEN
REN
WRADD
WADEN
RDADD
RADEN
DEVICE
2
FSTR
PAFn
ESTR
PAEn
Empty Sync 2
Full Sync2
FSYNC
ESYNC
FF
OV
PAF
PAE
SCLK
SO FXO EXO
SENO
SENI SI FXI EXI
Q
-Q
17
D
-D
17
0
0
WCLK
RCLK
REN
WEN
WRADD
WADEN
RDADD
RADEN
DEVICE
n
FSTR
PAFn
FSYNC
ESTR
PAEn
Full Sync n
Empty Sync n
ESYNC
FF
OV
PAF
PAE
SCLK
SENO
FXO EXO
DONE
5999 drw35
NOTES:
1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO
outputs are DNC (Do Not Connect).
2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.
Figure 31. Multi-Queue Expansion Diagram
51
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T51543/72T51553
incorporates thenecessarytapcontrollerandmodifiedpadcellstoimplement
theJTAG facility.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
The Figure belowshows the standardBoundary-ScanArchitecture
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5999 drw36
Figure 32. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
52
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-IR
Shift-DR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-IR
Pause-DR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-IR
Update-DR
1
0
1
0
5999 drw37
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal Queue operations can begin.
Figure 33. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram.
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overthe Queue andmustbe resetafterpowerupofthe device. See TRST
descriptionformoredetailsonTAPcontrollerreset.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IR This state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenabling
thenormaloperationoftheIC.TheTAPcontrollerstatemachineisdesigned
insuchawaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-
Logic-ResetstatecanbeenteredbyholdingTMSathighandpulsingTCKfive
times. This is the reasonwhythe TestReset(TRST)pinis optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-Scan This is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
53
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
JTAG INSTRUCTION REGISTER
THE INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
•
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions. Instructionsaredecodedasfollows.
TESTDATAREGISTER
Hex
Value
00
01
02
04
0F
Instruction
Function
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
EXTEST
SAMPLE/PRELOAD
IDCODE
HIGH-IMPEDANCE
BYPASS
SelectBoundaryScanRegister
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
JTAG
SelectBypassRegister
JTAG INSTRUCTION REGISTER DECODING
TEST BYPASS REGISTER
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
EXTEST
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO.Duringthisinstruction,theboundary-scanregisterisaccessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
IDCODE
THE DEVICE IDENTIFICATION REGISTER
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDI and TDO. The device identification register is a 32-bit shift register
containinginformationregardingtheICmanufacturer,devicetype,andversion
code.Accessingthedeviceidentificationregisterdoesnotinterferewiththe
operationoftheIC.Also,accesstothedeviceidentificationregistershouldbe
immediatelyavailable,viaaTAPdata-scanoperation,afterpower-upofthe
ICoraftertheTAPhasbeenresetusingtheoptionalTRSTpinorbyotherwise
movingtotheTest-Logic-Resetstate.
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
For the IDT72T51543/72T51553, the Part Number field contains the
followingvalues:
Device
IDT72T51543
IDT72T51553
Part# Field (HEX)
0x482
SAMPLE/PRELOAD
0x483
TherequiredSAMPLE/PRELOADinstructionallowstheICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.This instructionis alsousedtopreloadtestdata
intotheboundary-scanregisterbeforeloadinganEXTESTinstruction.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
JTAG DEVICE IDENTIFICATION REGISTER
54
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
toTDOwithoutaffectingtheconditionoftheICoutputs.
theIC.
55
IDT72T51543/72T515532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(32QUEUES)18BITWIDECONFIGURATION1,179,648and2,359,296bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5999 drw38
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 34. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions
Min. Max. Units
SYSTEMINTERFACEPARAMETERS
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
IDT72T51543
IDT72T51553
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
56
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to
+70°C)
Industrial (-40°C to +85°C)
Plastic Ball Grid Array (PBGA, BB256-1)
BB
Commercial Only
5
6
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Commercial & Industrial
Low Power
L
72T51543 1,179,648 bits 2.5V Multi-Queue Flow-Control Device
72T51553 2,359,296 bits 2.5V Multi-Queue Flow-Control Device
5999 drw39
NOTE:
1. Industrial temperature range product for the 6ns speed grade is available as a standard device. All other speed grades available by special order.
DATASHEETDOCUMENTHISTORY
06/06/2003
11/06/2003
pgs. 1 through 57.
pgs. 1, 4, 16 and 17.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1533
email:Flow-Controlhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
57
相关型号：
IDT72T51553L6BB8
FIFO, 128KX18, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT
IDT72T51553L7-5BBI
FIFO, 128KX18, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT
IDT72T51556
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT
IDT72T51556L5BB
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT
IDT72T51556L5BB8
FIFO, 64KX36, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT
IDT72T51556L5BBI
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT
IDT72T51556L6BB
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT
IDT72T51556L6BBI
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT
IDT72T54242
2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT
IDT72T54242L5BB
2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT
©2020 ICPDF网 联系我们和版权申明