ICS8431AM-11T [IDT]
Clock Generator, 400MHz, PDSO28, SOIC-28;
| 型号： | ICS8431AM-11T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 400MHz, PDSO28, SOIC-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总7页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8431-11
CLOCK SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL
The ICS8431-11 is a general purpose clock
,&6
frequency synthesizer and a member of the
• Differential 3.3V LVPECLoutput
HiPerClockS™ HiPerClockS™ family of High Performance
Clock Solutions from ICS. The VCO operates at
a frequency range of 280MHz to 400MHz. The
output frequency can be programmed using the parallel inter-
face, M0 thru M8, to the configuration logic. Spread spectrum
clocking is programmed via the Power Up Latch inputs
SSC_CTL0 and SSC_CTL1.
• Programmable PLL loop divider for generating a variety of
output frequencies.
• Crystal oscillator interface
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI
• Master reset for programming contents of the Power Up
Latch
• LVTTL/ LVCMOS control inputs
• PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
• 3.3V supply voltage
• 28 lead SOIC
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
XTAL1
OSC
XTAL2
M0
M1
M2
M3
M4
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
VDDI
XTAL2
XTAL1
nc
2
3
4
5
6
7
÷ 16
M5
M6
nc
PLL
VDDA
GND
MR
PHASE
DETECTOR
M7
M8
8
9
VCO
SSC_CTL 0
SSC_CTL 1
GND
TEST_I/O
VDD
10
11
12
13
14
nc
÷ N
FOUT
nFOUT
VDDO
FOUT
nFOUT
GND
÷ M
TEST_I/O
ICS8431-11
28-Lead SOIC
M Package
Configuration
Logic
Power Up
Latch
M0:M8
Top View
SSC_CTL0 SSC_CTL1
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8431-11
www.icst.com
REV.A- SEPTEMBER 25, 2000
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8431-11
CLOCK SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS8431-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A
16MHz series-resonant , fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over
a range of 280 to 400MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle.
The programmable features of the ICS8431-11 support four output operational modes and a programmable PLL loop divider.
The four output operational modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes and
are controlled by the Power Up Latch. After power up the latch is disabled and the initial programmed values can only be
overwritten by removing all power to the device or by asserting the master reset input, MR. A HIGH-to-LOW transition on MR
latches new data into the Power Up Latch.
Programming the Spread Spectrum Clocking (SSC) feature is accomplished by configuring the internal Power Up Latch. The
input to this latch is encoded by the SSC_CTL[1:0] pins which define all functional states after power is applied. Figure 1
shows the timing relationship of the latched SSC_CTL[1:0] in relationship to the PLL power-on condition.
VDD = 0V
VDD = 3.3V
VDD Power On
SSC_CTL[1:0]
t = 100µs
Data Valid
TPUL_SU
TPUL_HD
FIGURE 1. POWER-UP CONFIGURATION TIMING
Approximately 100µs after power is applied or a HIGH-to-LOW transistion on MR, the control bits SSC_CTL0 and SSC_CTL1
are latched. TPUL_SU is the time during which the data on the control bits is required to be valid before being latched.
TPUL_HD is the time after the data is latched that the control bits are required to remain valid. The configuration latch can be
overwritten by removing the power or by asserting MR and applying data to the inputs that meet the setup and hold time
requirment during power-on or of the master rest input. The power-on setup and hold time requirements are defined in Figure
1. Table 3A, Control Input Function Table defined the valid commands for SSC_CTL[1:0] lines.
The PLL loop divider or M divider is programmed by using inputs M0 through M8. Normally upon system power-up the nP_LOAD
input is held LOW until sometime after power becomes valid. On the LOW-to-HIGH transistion of nP_LOAD, the values
present at M[8:0] are captured. The relationship between the VCO frequency, the crystal frequency and the loop counter/
divider is defined as follows:
fxtal
16
x
fVCO =
M
The M count and the required values of M0:M8 for programming the VCO are shown in Table 3B, Programmable VCO Frequency
Function Table. The frequency out is defined as follows:
fVCO fxtal
M
N
fout
x
=
=
N
16
For the ICS8431-11 N equals 2. Valid M values for which the PLL will achieve lock are defined as 280 ≤ M ≤ 400.
8431-11
www.icst.com
REV.A- SEPTEMBER 25, 2000
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8431-11
CLOCK SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input.
LVCMOS / LVTTL pins interface levels.
1 -9
M0-M8
Input
SSC CTL 0,
SSC CTL 1
These LVCMOS / LVTTL pins are sampled during power-up to configure the
SSC control.
10, 11
12
Input
Pullup
GND
Power
Ground pin for core and test output.
Input /
Output
13
TEST I/O
Programmed as input in PLL bypass mode.
14
15
VDD
GND
Power
Power
Power supply pin for core and test output.
Ground pin for output.
These differential outputs are main output drivers for the synthesizer. They are
compatible with terminated positive referenced LVPECL logic.
16, 17
nFOUT, FOUT
Output
Power
18
VDDO
nc
Power supply pin for output.
No connection.
19, 23, 24
Unused
Input
Reset M counter. Loads and latches data on SSC_CTL0, SSC_CTL1 into
Power-Up latch.
20
MR
Pulldown
21
22
GND
VDDA
Power
Power
Input
PLL ground pin.
PLL power supply pin.
25, 26
27
XTAL1, XTAL2
VDDI
Crystal oscillator input.
Power
Input
Power supply pin for core.
28
nP_LOAD
Pullup
M divider latch enable input. LVTTL / LVCMOS interface levels.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
RPULLUP
Input Pullup Resistor
51
51
KΩ
RPULLDOWN Input Pulldown Resistor
KΩ
TABLE 3A. SSC CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
FOUT, nFOUT TEST_I/O
Disabled fXTAL ÷ 16 ÷ N fXTAL ÷ 16 ÷ M
TEST_I/O
Source
Operational Modes
SSC
SSC_CTL1 SSC_CTL0
PLL bypass; Oscillator, oscillator, M and N
dividers test mode. NOTE 1
0
0
Internal
0
1
1
1
0
1
PLL
External
PLL
Enabled
Disabled
Disabled
200MHz
Test Clk
200MHz
Hi-Z
Input
Hi-Z
Default SSC; Modulation Factor = ½ Percent
PLL Bypass Mode, (1MHz ≤ Test Clk ≤ 200MHz)
No SSC Modulation
NOTE 1: Used for in house debug and characterization.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
128
M7
64
32
16
8
4
2
1
VCO Frequency
(MHz)
M Count
M6
M5
M4
M3
M2
M1
M0
250
251
252
253
•
250
251
252
253
•
0
0
0
0
•
1
1
1
1
•
1
1
1
1
•
1
1
1
1
•
1
1
1
1
•
1
1
1
1
•
0
0
1
1
•
1
1
0
0
•
0
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
498
499
500
498
499
500
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
8431-11
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REV.A- SEPTEMBER 25, 2000
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8431-11
CLOCK SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
0°C to 70°C
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical Charac-
teristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
TABLE 4A. LVTTL, LVCMOS DC ELECTRICAL CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Power Supply Voltage
Test Conditions
Minimum
3.135
2
Typical
Maximum
3.465
3.765
0.8
Units
VDDA,
VDDO, VDD
3.3
V
V
V
Input High
Voltage
M0:M8, SSC_CTL0,
SSC_CTL1, TEST_I/O
VIH
VIL
3.135V ≤ VDD ≤ 3.465V
3.135V ≤ VDD ≤ 3.465V
M0:M8, SSC_CTL0,
SSC_CTL1, TEST_I/O
Input Low Voltage
-0.3
Input High
Current
M0:M8, SSC_CTL0,
SSC_CTL1
VDD = VIN = 3.465V
VDD = VIN = 3.465V
50
50
µA
µA
µA
µA
IIH
IIL
TEST_I/O
M0:M8, SSC_CTL0,
SSC_CTL1
Input Low Current
TEST_I/O
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-600
-50
TABLE 4B. LVPECL DC ELECTRICAL CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
VDDx = 3.3V
VDDx = 3.3V
Minimum
Typical
Maximum
Units
V
VOH
Output High Voltage; NOTE 1, 2
Output Low Voltage; NOTE 1, 2
Peak-to-Peak Output Voltage Swing
Output High Current
2.1
1.4
600
16
2.2
1.5
800
18
VOL
V
VSWING
IOH
V
mA
mA
IOL
Output Low Current
2
4
NOTE 1: These values are for VDDO equal to 3.3V. Output levels will vary 1:1 with VDDO.
NOTE 2: Output terminated with 50Ω to VDDO - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Min
Typ
Max
Units
Crystal Cut
Mode of Oscillation
Frequency Tolerance
Frequency Stability
Drive Level
ppm
ppm
µW
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitiance
Series Pin Inductance
Aging
pF
nH
ppm
8431-11
www.icst.com
REV.A- SEPTEMBER 25, 2000
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8431-11
CLOCK SYNTHESIZER
TABLE 6. AC ELECTRICAL CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
tjit
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Peak Jitter (Short Cycle); NOTE 1
Output Duty Cycle; NOTE 1
Output Rise Time
50
53
ps
%
tDC
tR
47
300
300
30
20% to 80%
20% to 80%
800
800
33.33
ps
ps
KHz
%
tF
Output Fall Time
Fm
SSC Modulation Frequency
SSC Modulation Factor
PLL Lock Time
Fmf
tLOCK
tPW
0.5
TBD
µs
ns
ns
Input Pulse Width
nP_LOAD
TBD
10
SSC_CTLx to MR
M to nP_LOAD
SSC_CTLx to MR
M to nP_LOAD
tS
tH
Setup Time
TBD
0
ns
Hold Time
TBD
10
tPUL_SU Configuration Latch Setup Time
tPUL_HD Configuration Latch Hold Time
NOTE 1: Spread spectrum clocking enabled.
ns
ns
0
8431-11
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REV.A- SEPTEMBER 25, 2000
5
Integrated
Circuit
Systems, Inc.
ICS8431-11
CLOCK SYNTHESIZER
PACKAGE OUTLINE AND DIMENSIONS - M SUFFIX
8431-11
www.icst.com
REV.A- SEPTEMBER 25, 2000
6
Integrated
Circuit
Systems, Inc.
ICS8431-11
CLOCK SYNTHESIZER
ORDERING INFORMATION
Part/Order Number
ICS8431AM-11
Marking
Package
28 Lead SOIC
Count
Temperature
0°C to 70°C
0°C to 70°C
ICS8431AM-11
ICS8431AM-11
ICS8431AM-11T
28 Lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8431-11
www.icst.com
REV.A- SEPTEMBER 25, 2000
7
相关型号：
ICS8431CM-01LFT
Clock Generator, 200MHz, PDSO28, 7.5 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28
IDT
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