ICS8431CM-01 [ICSI]
200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER; 200MHZ ，低抖动， LVPECL频率合成器
| 型号： | ICS8431CM-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总11页 (文件大小：2085K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8431-01 is a general purpose clock • Fully integrated PLL
,&6
frequency synthesizer for IA64/32 application and
• Differential 3.3V LVPECLoutput
HiPerClockS™
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8431-01 consists of one independent low
• 200MHz output frequency
• 48% to 52% duty cycle
• Crystal oscillator interface
bandwidth PLL timing channel. A 16.666MHz crystal is used
as the input to the on-chip oscillator. The M is configured to
produce a fixed output frequency of 200MHz.
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI. Typical10dB EMI
reduction can be achieved with spread spectrum modulation
Programmable features of the ICS8431-01 support four
operational modes. The four modes are spread spectrum
clocking (SSC), non-spread spectrum clock and two test
modes which are controlled by the SSC_CTL[1:0] pins. Un-
like other synthesizers, the ICS8431-01 can immediately
change spread-spectrum operation without having to reset
the device.
• LVTTL/ LVCMOS control inputs
• PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
• 28 lead SOIC
In SSC mode, the output clock is modulated in order to
achieve a reduction in EMI. In one of the PLL bypass test
modes, the PLL is disconnected as the source to the
differential output allowing an external source to be
connnected to the TEST_I/O pin. This is useful for in-
circuit testing and allows the differential output to be driven
at a lower frequency throughout the system clock tree. In the
other PLL bypass mode, the oscillator divider is used as the
source to both the M and the Fout divide by 2. This is useful
for characterizing the oscillator and internal dividers.
• RMS cycle-to-cycle jitter of 2ps
• Typical cycle-to-cycle jitter of 18ps
• 0° to 85°C ambiant operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
nc
nc
nc
nc
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nc
XTAL1
OSC
VDDI
XTAL2
XTAL1
nc
nc
VDDA
VEE
XTAL2
÷ 16
nc
nc
nc
nc
nc
5
6
7
8
PLL
9
RESERVED
nc
PHASE
DETECTOR
SSC_CTL0
SSC_CTL1
VEE
TEST_I/O
VDD
10
11
12
13
14
VDDO
FOUT
nFOUT
VEE
VCO
÷ 2
FOUT
nFOUT
÷ M
ICS8431-01
28-Lead SOIC
M Package
TEST_I/O
SSC_CTL0
SSC
Top View
Control
SSC_CTL1
Logic
ICS8431CM-01
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REV. A JUNE 5, 2001
1
ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Unused
Description
1-9, 19,
23, 24, 28
nc
Unused pins.
SSC_CTL0,
SSC_CTL1
10, 11
12
Input
Pullup SSC control pins. LVTTL/LVCMOS interface levels.
Ground pin for core and test output.
GND
Power
Input /
Output
13
TEST_ I/O
Programmed as defined in Table 3 Function Table..
14, 27
15
VDD
GND
Power
Power
Power supply pin for core and test output.
Ground pin for output.
These differential outputs are main output drivers for the synthesizer.
They are compatible with terminated positive referenced LVPECL
logic.
16, 17
nFOUT, FOUT
Output
18
20
VDDO
RESERVED
VEE
Power
Reserve
Power
Power
Input
Power supply pin for output.
Reserve pin.
21
Ground pin.
22
VDDA
PLL power supply pin.
25, 26
27
XTAL1, XTAL2
VDDI
Crystal oscillator input.
Input and core power supply pin. Connect to 3.3V.
Power
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Pin Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3. SSC CONTROL INPUTS FUNCTION TABLE
Inputs
TEST_I/O
SSC
Outputs
FOUT,
nFOUT
Operational Modes
Source
SSC_CTL1 SSC_CTL0
TEST_I/O
fXTAL ÷ 16
÷ M
PLL bypass; Oscillator, oscillator, M and N
dividers test mode. NOTE 1
0
0
1
1
0
1
0
1
Internal
PLL
Disabled fXTAL ÷ 32
Enabled
200MHz
Test Clk
200MHz
Hi-Z
Input
Hi-Z
Default SSC; Modulation Factor = ½ Percent
Diagnostic Mode; NOTE 1
(1MHz ≤ Test Clk ≤ 200MHz)
External Disabled
PLL Disabled
No SSC Modulation
NOTE 1: Used for in house debug and characterization.
ICS8431CM-01
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REV. A JUNE 5, 2001
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ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
0°C to 85°C
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
VDDA
VDDI
IEE
Power Supply Voltage
3.135
3.135
3.135
3.135
3.3
3.3
3.3
3.3
3.465
3.465
3.465
3.465
140
V
V
Output Power Supply Voltage
Analog Power Supply Voltage
Input Power Supply Voltage
V
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
SSC_CTL0,
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage SSC_CTL1,
TEST_I/O
SSC_CTL0,
Input Low Voltage SSC_CTL1,
TEST_I/O
SSC_CTL0,
Input High Current SSC_CTL1,
TEST_IO
SSC_CTL0,
Input Low Current SSC_CTL1,
TEST_IO
3.135V ≤ VDD ≤ 3.465V
2
VDD + 0.3
V
V
VIL
IIH
IIL
3.135V ≤ VDD ≤ 3.465V
VDD = VIN = 3.465V
-0.3
0.8
5
µA
µA
VDD = 3.465V, VIN = 0V
-150
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VDDO - 1.28
VDDO - 2.0
600
Typical
Maximum
VDDO - 0.980
VDDO - 1.7
850
Units
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
VSWING Peak-to-Peak Output Voltage Swing
700
mV
NOTE 1: Output terminated with 50Ω to VDDO - 2V.
ICS8431CM-01
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REV. A JUNE 5, 2001
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ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Fundamental
Units
Mode of Oscillation
Frequency
16.666
MHz
ppm
ppm
µW
Ω
Frequency Tolerance
Frequency Stability
Drive Level
-50
+50
+100
100
50
-100
Equivalent Series Resistance (ESR)
Shunt Capacitiance
Load Capacitiance
Series Pin Inductance
Operating Temperature Range
Aging
3
10
3
7
pF
18
32
pF
7
nH
0
70
°C
Per year @25°C
-5
+5
ppm
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C, 16.666MHZ CRYSTAL
Symbol
Parameter
Test Conditions
FOUT = 200 MHz
FOUT = 200 MHz
FOUT = 200 MHz
20% to 80%
Minimum Typical Maximum Units
tPERIOD
Average Output Period; NOTE 2
Cycle-to-Cycle Jitter; NOTE 2
Output Duty Cycle; NOTE 2
Output Rise Time; NOTE 1, 2
Output Fall Time; NOTE 1, 2
Crystal Input Range
4995
5005
30
ps
ps
18
t
jit(cc)
odc
tR
48
300
300
14
52
%
450
450
600
600
18
ps
tF
20% to 80%
ps
Fxtal
16.666
MHz
SSC Modulation Frequency;
NOTE 1, 2
SSC Modulation Factor;
NOTE 1, 2
Fm
30
33.33
0.6
KHz
%
Fmf
0.4
10
SSCred
Spectral Reduction; NOTE 1, 2
Power-up to Stable Clock Output
7
dB
ms
tSTABLE
10
NOTE 1: Spread Spectrum clocking enabled.
NOTE 2: Outputs terminated with 50Ω to VDDO - 2V.
t
jit(cc), tR, tF, odc conform to JEDEC JESD65 definitions.
ICS8431CM-01
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REV. A JUNE 5, 2001
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ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
80%
80%
Vswing
20%
20%
Clock Inputs
and Outputs
➤
➤
➤
➤
trise
tfall
FIGURE 1 — INPUT AND OUTPUT SLEW RATES
X_CLK, 1X_FOUT
nX_CLK, n1X_FOUT
➤
➤
tcycle n+1
tcycle n
➤
➤
tjit(cc) = tcycle n –tcycle n+1
FIGURE 2 — CYCLE-TO-CYCLE JITTER
nX_CLK, n1X_FOUT
X_CLK, 1X_FOUT
➤
Pulse Width (tpw)
➤
➤
tPERIOD
➤
tpw
tPERIOD
odc =
FIGURE 3 — odc & tPERIOD
ICS8431CM-01
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REV. A JUNE 5, 2001
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ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
CRYSTAL INPUT AND OSCILLATOR INTERFACE
The ICS8431-01 features an internal oscillator that uses an
external quartz crystal as the source of its reference frequency.
A 16.666 MHz crystal divided by 16 before being sent to the phase
detector provides the reference frequency. The oscillator is a
series resonant, multi-vibrator type design. This design provides
better stability and eliminates the need for large on chip capacitors.
Though a series resonant crystal is preferred, a parallel resonant
crystal can be used. A parallel resonant mode crystal used in a
series resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified. A few hundred ppm translates
to KHz inaccuracy. In general computing applications this level
of inaccuracy is irrelevant. If better ppm accuracy is required, an
external capacitor can be added to a parallel resonant crystal in
series to pin 25. Figure 1A shows how to interface with a crystal.
ICS8431-01
XTAL2
(Pin 26, SOIC)
XTAL1
(Pin 25, SOIC)
Optional
Quartz Crystal Selection:
(1) Raltron Series Resonant:AS-16.66-S-SMD-T-MI
(2) Raltron Parallel Resonant:AS-16.66-18-SMD-T-MI
Figures 1A, 1B, and 1C show various crystal parameters
which are recommended only as guidelines. Figure 1A shows
how to interface a capacitor with a parallel resonant crystal.
Figure 1B shows the capacitor value needed for the optimum
PPM performance over various parallel resonant crystals.
Figure 1C shows the recommended tuning capacitance for a
16.666MHz parallel resonant crystal.
FIGURE 1A. CRYSTAL INTERFACE
FIGURE 1B. Recommended tuning capacitance for various parallel
FIGURE 1C. Recommended tuning capacitance for 16.666MHz
parallel resonant crystal.
resonant crystals.
16.666MHz
100
60
14.318
50
80
60
40
20
0
15.000
40
16.667
19.440
30
20.000
20
24.000
10
0
10
20
30
40
50
60
-20
-40
0
14 15 16 17 18 19 20 21 22 23 24 25
-60
Crystal Frequency (MHz)
-80
-100
Series Capacitor, C1 (pF)
ICS8431CM-01
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ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
Integrated
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Systems, Incꢀ
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation tech- The ICS8431-01 triangle modulation frequency deviation will
nique for EMI reduction. When spread-spectrum is enabled, a not exceed 0.6% down-spread from the nominal clock fre-
30KHz triangle waveform is used with 0.5% down-spread quency (+0.0%/-0.5%). An example of the amount of down
(+0.0% / -0.5%) from the nominal 200MHz clock frequency. spread relative to the nominal clock frequency can be seen in
An example of a triangle frequency modulation profile is shown the frequency domain, as shown in Figure 3. The ratio of this
in Figure 2 below. The ramp profile can be expressed as:
width to the fundamental frequency is typically 0.4%, and will
not exceed 0.6%. The resulting spectral reduction will be
greater than 7dB, as shown in Figure 3. It is important to note
the ICS8431-01 7dB minimum spectral reduction is the com-
ponent-specific EMI reduction, and will not necessarily be the
same as the system EMI reduction.
• Fnom = Nominal Clock Frequency in Spread OFF mode
(200MHz with 16.666MHz IN)
• Fm = Nominal Modulation Frequency (30KHz)
• δ = Modulation Factor (0.5% down spread)
1
(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t <
,
2 fm
1
1
fm
(1 - δ) fnom - 2 fm x δ x fnom x t when
< t <
2 fm
Fnom
∆ − 10 dBm
A
B
(1 - δ) Fnom
δ = .4%
➤
1/fm
0.5/fm
FIGURE 3. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
FIGURE 2. TRIANGLE FREQUENCY MODULATION
(A) SPREAD-SPECTRUM OFF
(B) SPREAD-SPECTRUM ON
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8431-01 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDI, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be used
for each pin. To achieve optimum jitter performance, better
power supply isolation is required. Figure 4 illustrates how a
10Ω along with a 10µF and a .01µF bypass capacitor should
be connected to each power supply pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10 µF
FIGURE 4. POWER SUPPLY FILTERING
ICS8431CM-01
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ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
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TERMINATION FOR PECL OUTPUTS
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. There are a few simple termination
schemes. Figures 5A and 5B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/PECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
Zo = 50Ω
5
2
5
Zo
Zo
2
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
50Ω
Zo = 50Ω
FOUT
FIN
50Ω
➤
Zo = 50Ω
Zo = 50Ω
VCC-2V
RTT
1
3
2
3
Zo
RTT =
Zo
Zo
2
(VOH + VOL / VCC –2) –2
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8431-01 layout example used in this layout guideline is shown in Figure 6A. The ICS8431-01 recommended
PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of
the P.C. board.
U1
C6
0.01uF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nc
nc
nc
nc
nc
nc
nc
nc
nc
VDDI
XTAL2
XTAL1
nc
nc
VDDA
VEE
nc
nc
VDDO
FOUT
nFOUT
VEE
VDD
Termination A
Termination
B (not shown
in the layout)
X1
R5
10
VDDA
VDD0
nc
C3
0.01uF
C4
SSC_CTL0
SSC_CTL1
VEE
TEST_IO
VDD
VDD
10uF
IN+
IN-
R1
125
VDD
Zo = 50 Ohm
IN+
TL1
8431-01
R3
125
R2
50
R1
50
C1
0.1uF
Zo = 50 Ohm
IN-
C2
0.1uF
TL2
R2
84
R4
84
R3
50
FIGURE 6A. RECOMMENDED SCHEMATIC LAYOUT
ICS8431CM-01
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ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
Integrated
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Systems, Incꢀ
The following component footprints are used in this layout
example:
the component location. While routing the traces, the clock signal
traces should be routed first and should be locked prior to routing
other signals traces.
All the resistors and capacitors are size 0603.
• The traces with 50Ω transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other.Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
The Crystal X1 is Raltron Part #AS-16.666-18-SMD.
POWER AND GROUNDING
Place the decoupling capacitors C1, C2 and C3, C4, C5, C6 as
close as possible to the power pins. If space allows, placing the
decoupling capacitor at the component side is preferred. This can
reduce unwanted inductance between the decoupling capacitor
and the power pin generated by the via.
• Keep the clock trace on same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace
can affect the trace characteristic impedance and hence
degrade signal quality.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
If VDDAshares the same power supply with VDD, insert the RC
filter R5, C3, and C4 in between. Place this RC filter as close to
the VDDAas possible.
• Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should be
located as close to the receiver input pins as possible. Other termi-
nation scheme can also be used but is not shown in this example.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
CRYSTAL
The crystal X1 should be located as close as possible to the pins
26 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
U1
ICS8431-01
GND
VDD
C6
X1
Signals
VIA
C3
C4
R5
Close to the input
pins of the
receiver
R1
C2
R2
TL1 (50 Ohm)
TL2 (50 Ohm)
IN+
IN-
C1
R3
R4
FIGURE 6B. PCB BOARD LAYOUT FOR ICS8431-01
ICS8431CM-01
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REV. A JUNE 5, 2001
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ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - M SUFFIX
C
N
28
15
14
L
E
H
1
h x 45º
α
D
A2
A
e
A1
SEATING
PLANE
B
.10 (.004)
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Inches
MIN
MAX
MIN
MAX
N
A
28
--
2.65
--
--
0.104
--
A1
A2
B
0.10
2.05
0.33
0.18
17.70
7.40
0.0040
0.081
0.013
0.007
0.697
0.291
2.55
0.51
0.32
18.40
7.60
0.100
0.020
0.013
0.724
0.299
C
D
E
e
1.27 BASIC
0.050 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
0.394
0.010
0.016
0°
0.419
0.029
0.050
8°
L
α
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-013, MO-119
ICS8431CM-01
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REV. A JUNE 5, 2001
10
ICS8431-01
200MHZ, LOW JITTER,
LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8431CM-01
Marking
Package
28 Lead SOIC
Count
26 Per Tube
1000
Temperature
0°C to 85°C
0°C to 85°C
ICS8431CM-01
ICS8431CM-01
ICS8431CM-01T
28 Lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
ICS8431CM-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 5, 2001
11
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