ICS8431CM-01LFT [IDT]
Clock Generator, 200MHz, PDSO28, 7.5 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28;
| 型号： | ICS8431CM-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 200MHz, PDSO28, 7.5 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8431-01 is a general purpose clock • Fully integrated PLL
frequency synthesizer for IA64/32 applications
• Differential 3.3V LVPECLoutput
HiPerClockS™
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8431-01 consists of one independent low
• Crystal oscillator interface
• Output frequency: 200MHz
• 48% to 52% duty cycle
bandwidth PLL timing channel. A 16.666MHz crystal is used
as the input to the on-chip oscillator. The M divide is config-
ured to produce a fixed output frequency of 200MHz.
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI. Typical10dB EMI
reduction can be achieved with spread spectrum modulation
Programmable features of the ICS8431-01 support four
operational modes. The four modes are spread spectrum
clocking (SSC), non-spread spectrum clocking and two test
modes which are controlled by the SSC_CTL[1:0] pins. Un-
like other synthesizers, the ICS8431-01 can immediately
change spread-spectrum operation without having to reset
the device.
• PLLbypass modes supporting in-circuit testing and on-chip
functional block characterization
• Cycle-to-cycle jitter: 30ps (maximum)
• 3.3V supply voltage
In SSC mode, the output clock is modulated in order to
achieve a reduction in EMI. In one of the PLL bypass test
modes, the PLL is disconnected as the source to the
differential output allowing an external source to be
connnected to the TEST_I/O pin. This is useful for in-
circuit testing and allows the differential output to be driven
at a lower frequency throughout the system clock tree. In the
other PLL bypass mode, the oscillator divider is used as the
source to both the M divide and the Fout divide by 2. This is
useful for characterizing the oscillator and internal dividers.
• 0° to 85°C Ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
nc
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nc
XTAL1
OSC
nc
nc
2
3
VCC
XTAL2
XTAL1
nc
XTAL2
nc
nc
4
5
÷ 16
nc
nc
6
7
nc
VCCA
VEE
nc
8
PLL
nc
9
RESERVED
nc
PHASE
DETECTOR
SSC_CTL0
SSC_CTL1
VEE
10
11
12
13
14
VCCO
FOUT
nFOUT
VEE
VCO
÷ 2
TEST_I/O
VCC
FOUT
nFOUT
÷ M
ICS8431-01
TEST_I/O
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
SSC_CTL0
SSC
M Package
Top View
Control
SSC_CTL1
Logic
8431CM-01
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REV. B FEBRUARY 3, 2003
1
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Unused
Description
1-9, 19,
23, 24, 28
nc
No connect.
SSC_CTL0,
SSC_CTL1
10, 11
12, 15, 21
13
Input
Pullup SSC control pins. LVTTL/LVCMOS interface levels.
Negative supply pins. Connect all VEE pins to board ground.
Programmed as defined in Table 3 Function Table.
Core supply pins.
VEE
TEST_ I/O
VCC
Power
Input /
Output
14, 27
16, 17
Power
Differential output for the synthesizer. Compatible with terminated
positive reference LVPECL logic.
nFOUT, FOUT
Output
18
20
VCCO
RESERVED
VCCA
Power
Reserve
Power
Input
Output supply pin.
Reserve pin.
22
Analog supply pin.
Crystal oscillator inputs.
25, 26
XTAL1, XTAL2
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Pin Capacitance
Input Pullup Resistor
4
pF
RPULLUP
51
KΩ
TABLE 3. SSC CONTROL INPUT FUNCTION TABLE
Inputs
TEST_I/O
SSC
Outputs
Operational Modes
FOUT,
Source
SSC_CTL1 SSC_CTL0
TEST_I/O
nFOUT
fXTAL ÷ 16
÷ M
PLL bypass; oscillator, M and N dividers test
mode. NOTE 1
0
0
1
1
0
1
0
1
Internal
PLL
Disabled fXTAL ÷ 32
Enabled
200MHz
Test Clk
200MHz
Hi-Z
Input
Hi-Z
Default SSC; Modulation Factor = ½ Percent
Diagnostic Mode; NOTE 1
(1MHz ≤ Test Clk ≤ 200MHz)
External Disabled
PLL Disabled
No SSC Modulation
NOTE 1: Used for in house debug and characterization.
8431CM-01
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REV. B FEBRUARY 3, 2003
2
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
-0.5V to VCCO + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 39.7°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCO
VCCA
IEE
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
140
V
V
Output Supply Voltage
Analog Supply Voltage
Power Supply Current
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VCC + 0.3
V
V
Input Low Voltage
Input High Curren
Input Low Current
-0.3
0.8
5
SSC_CTL0,
SSC_CTL1, TEST_IO
SSC_CTL0,
VCC = VIN = 3.465V
VCC = VIN = 3.465V
µA
IIL
-150
µA
SSC_CTL1, TEST_IO
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
600
Typical
Maximum
VCCO - 1.0
VCCO - 1.7
850
Units
V
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
V
VSWING
Peak-to-Peak Output Voltage Swing
700
mV
NOTE 1: Output terminated with 50Ω to VCCO - 2V.
8431CM-01
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REV. B FEBRUARY 3, 2003
3
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
16.666
70
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Series Pin Inductance
3
3
7
7
pF
nH
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
tPERIOD
tjit(cc)
odc
Parameter
Test Conditions
FOUT = 200MHz
FOUT = 200MHz
FOUT = 200MHz
20% to 80%
Minimum Typical Maximum Units
Average Output Period; NOTE 2
Cycle-to-Cycle Jitter; NOTE 2, 3
Output Duty Cycle; NOTE 2
Output Rise/ Fall Time; NOTE 1, 2
Crystal Input Range
4995
5005
30
ps
ps
18
48
300
14
52
%
tR / tF
Fxtal
450
600
18
ps
16.666
MHz
KHz
%
Fm
SSC Modulation Frequency; NOTE 1, 2
SSC Modulation Factor; NOTE 1, 2
Spectral Reduction; NOTE 1, 2
Power-up to Stable Clock Output
30
33.33
0.6
Fmf
0.4
10
SSCred
tSTABLE
7
dB
ms
10
NOTE 1: Spread Spectrum clocking enabled.
NOTE 2: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8431CM-01
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REV. B FEBRUARY 3, 2003
4
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO = 2V
nFOUT
SCOPE
Qx
FOUT
➤
➤
LVPECL
tcycle n
tcycle n+1
➤
➤
nQx
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
VEE = -1.3V ± 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
nFOUT
FOUT
80%
80%
VSWING
20%
Pulse Width
20%
tPERIOD
Clock Outputs
t
t
F
R
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
odc & tPERIOD
8431CM-01
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REV. B FEBRUARY 3, 2003
5
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
CRYSTAL INPUT AND OSCILLATOR INTERFACE
The ICS8431-01 features an internal oscillator that uses an
external quartz crystal as the source of its reference frequency.
A 16.666MHz crystal divided by 16 before being sent to the phase
detector provides the reference frequency. The oscillator is a
series resonant, multi-vibrator type design. This design provides
better stability and eliminates the need for large on chip capacitors.
Though a series resonant crystal is preferred, a parallel resonant
crystal can be used. A parallel resonant mode crystal used in a
series resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified. A few hundred ppm translates
to KHz inaccuracy. In general computing applications this level
of inaccuracy is irrelevant. If better ppm accuracy is required, an
external capacitor can be added to a parallel resonant crystal in
series to pin 25. Figure 1A shows how to interface with a crystal.
ICS8431-01
XTAL2
(Pin 26, SOIC)
XTAL1
(Pin 25, SOIC)
Optional
Quartz Crystal Selection:
(1) Raltron Series Resonant:AS-16.66-S-SMD-T-MI
(2) Raltron Parallel Resonant:AS-16.66-18-SMD-T-MI
Figures 1A, 1B, and 1C show various crystal parameters which
are recommended only as guidelines. Figure 1A shows how to
interface a capacitor with a parallel resonant crystal. Figure 1B
shows the capacitor value needed for the optimum ppm perfor-
mance over various parallel resonant crystals. Figure 1C shows
the recommended tuning capacitance for a 16.666MHz parallel
resonant crystals.
FIGURE 1A. CRYSTAL INTERFACE
FIGURE 1C. Recommended tuning capacitance for 16.666MHz
FIGURE 1B. Recommended tuning capacitance for various parallel
parallel resonant crystal.
resonant crystals.
16.666MHz
100
60
14.318
50
80
60
40
20
0
15.000
40
16.667
19.440
30
20.000
20
24.000
10
0
10
20
30
40
50
60
-20
-40
0
14 15 16 17 18 19 20 21 22 23 24 25
-60
Crystal Frequency (MHz)
-80
-100
Series Capacitor, C1 (pF)
8431CM-01
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REV. B FEBRUARY 3, 2003
6
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation tech- The ICS8431-01 triangle modulation frequency deviation will
nique for EMI reduction. When spread-spectrum is enabled, a not exceed 0.6% down-spread from the nominal clock fre-
30KHz triangle waveform is used with 0.5% down-spread
quency (+0.0%/-0.5%). An example of the amount of down
(+0.0% / -0.5%) from the nominal 200MHz clock frequency. spread relative to the nominal clock frequency can be seen in
An example of a triangle frequency modulation profile is shown the frequency domain, as shown in Figure 2A. The ratio of this
in Figure 2 below. The ramp profile can be expressed as:
width to the fundamental frequency is typically 0.4%, and will
not exceed 0.6%. The resulting spectral reduction will be
greater than 7dB, as shown in Figure 2B. It is important to
note the ICS8431-01 7dB minimum spectral reduction is the
component-specific EMI reduction, and will not necessarily
be the same as the system EMI reduction.
• Fnom = Nominal Clock Frequency in Spread OFF mode
(200MHz with 16.666MHz IN)
• Fm = Nominal Modulation Frequency (30KHz)
• δ = Modulation Factor (0.5% down spread)
1
(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t <
,
2 fm
1
1
fm
(1 - δ) fnom - 2 fm x δ x fnom x t when
< t <
2 fm
∆ − 10 dBm
Fnom
A
B
➤
δ = .4%
(1 - δ) Fnom
➤
➤
0.5/fm
1/fm
FIGURE 2B. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
FIGURE 2A. TRIANGLE FREQUENCY MODULATION
(A) SPREAD-SPECTRUM OFF
(B) SPREAD-SPECTRUM ON
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8431-01 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VCC, VCCA, and VCCO should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, better power supply iso-
lation is required. Figure 3 illustrates how a 10Ω along with a
10µF and a .01µF bypass capacitor should be connected to
each VCCA pin.
3.3V
VCC
10Ω
.01µF
.01µF
VCCA
10 µF
FIGURE 3. POWER SUPPLY FILTERING
8431CM-01
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REV. B FEBRUARY 3, 2003
7
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is typical for
drive 50Ω transmission lines. Matched impedance techniques
IA64/32 platforms. The two different layouts mentioned are should be used to maximize operating frequency and minimize
recommended only as guidelines.
signal distortion. Figures 4Aand 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECLcompatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
VCC-2V
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8431-01 layout example used in
this layout guideline is shown in Figure 5A. The ICS8431-01
recommended PCB board layout for this example is shown
in Figure 5B. This layout example is used as a general guide-
line. The layout in the actual system will depend on the
selected component types, the density of the components,
the density of the traces, and the stack up of the P.C. board.
U1
C5
0.01uF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nc
nc
nc
nc
nc
nc
nc
nc
nc
VCCI
XTAL2
XTAL1
nc
nc
VCCA
VEE
nc
nc
VCCO
FOUT
nFOUT
VEE
VCC
Termination A
Termination
B (not shown
in the layout)
X1
R5
10
VCCA
VCC0
nc
C3
0.01uF
C4
SSC_CTL0
SSC_CTL1
VEE
TEST_IO
VCC
VCC
10uF
IN+
IN-
R1
125
VCC
Zo = 50 Ohm
IN+
TL1
8431-01
R3
125
R2
50
R1
50
C1
0.1uF
Zo = 50 Ohm
IN-
C2
0.1uF
TL2
R2
84
R4
84
R3
50
FIGURE 5A. RECOMMENDED SCHEMATIC LAYOUT
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8431CM-01
REV. B FEBRUARY 3, 2003
8
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
• The differential 50Ω output traces should have same
length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
All the resistors and capacitors are size 0603.
The Crystal X1 is Raltron Part #AS-16.666-18-SMD.
POWER AND GROUNDING
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Place the decoupling capacitors C1, C2, C3, C4, and C5, as
close as possible to the power pins. If space allows, placment of
the decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin generated by the via.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• Make sure no other signal traces are routed between the
clock trace pair.
The RC filter consisting of R5, C3, and C4 should be placed as
close to the VCCA pin as possible.
• The matching termination resistors should be located as
CLOCK TRACES AND TERMINATION
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible.
Other termination scheme can also be used but is not shown
in the example.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
25 (XTAL1) and 26 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
U1
ICS8431-01
GND
VCC
C5
X1
Signals
VIA
C3
C4
R5
Close to the input
pins of the
receiver
R1
C2
R2
TL1 (50 Ohm)
TL2 (50 Ohm)
IN+
IN-
C1
R3
R4
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8431-01
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8431CM-01
REV. B FEBRUARY 3, 2003
9
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8431-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8431-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA= 485.1mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 30.2mW = 515.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.515W * 39.7°C/W = 105.4°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 7. THERMAL RESISTANCE qJA FOR 28-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
76.2°C/W
60.8°C/W
53.2°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8431CM-01
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10
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
- V ) =
OH_MAX
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
OH_MAX
CCO_MAX
L
CCO
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8431CM-01
www.icst.com/products/hiperclocks.html
REV. B FEBRUARY 3, 2003
11
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
76.2°C/W
60.8°C/W
53.2°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8431-01 is: 5323
8431CM-01
www.icst.com/products/hiperclocks.html
REV. B FEBRUARY 3, 2003
12
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - M SUFFIX
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MINIMUM
MAXIMUM
N
A
28
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
17.70
7.40
2.55
0.51
0.32
18.40
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-013, MO-119
8431CM-01
www.icst.com/products/hiperclocks.html
REV. B FEBRUARY 3, 2003
13
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
28 Lead SOIC
Count
26 Per Tube
1000
Temperature
0°C to 85°C
0°C to 85°C
ICS8431CM-01
ICS8431CM-01T
ICS8431CM-01
ICS8431CM-01
28 Lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8431CM-01
www.icst.com/products/hiperclocks.html
REV. B FEBRUARY 3, 2003
14
ICS8431-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Incꢀ
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
B
T6
4
9
Updated tjit(cc) row from 13ps Typical to 18ps Typical; 25ps Max. to 30ps Max.
Updated Figures 8A and 8B, LVPECL Output Termination.
12/7/01
B
B
T5
4
Crystal Characteristics table, ESR row value updated from 50Ω Max. to 70Ω Max.
1/10/02
6/17/02
T1
T1
2
2
2
3
5
Pin Description table, revised VEE description.
Pin Description table, revised VCC description.
T2
Pin Characteristics table, deleted RPULLDOWN row.
T4A
Power Supply table, changed VCC parameter to correspond with description.
B
2/3/03
3.3V Output Load AC Test diagram, corrected VEE equation to read -1.3V±0.165V
from 1.3V±0.135V.
8
9
Updated Figure 2B 200MHz Clock Output in Frequency Domain plot.
Updated Figures 4A & 4B LVPECL Output Termination Diagrams.
8431CM-01
www.icst.com/products/hiperclocks.html
REV. B FEBRUARY 3, 2003
15
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