ICS8431CM-11 [ICSI]
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER; 255MHZ ，低抖动， LVPECL频率合成器
| 型号： | ICS8431CM-11 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总13页 (文件大小：2096K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8431-11
255MHZ, LOW JITTER,
Integrated
Circuit
Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL
The ICS8431-11 is a general purpose clock
frequency synthesizer for IA64/32 application and
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The VCO
operates at a frequency range of 190MHz to
• Differential 3.3V LVPECLoutput
HiPerClockS™
• Programmable PLL loop divider for generating a variety of
output frequencies.
510MHz providing an output frequency range of 95MHz to
255MHz. The output frequency can be programmed using the
parallel interface, M0 thru M8, to the configuration logic.
Spread spectrum clocking is programmed via the control
inputs SSC_CTL0 and SSC_CTL1.
• Crystal oscillator interface
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI
• Typical RMS cycle-to-cycle jitter 2.6 ps
• LVTTL / LVCMOS control inputs
Programmable features of the ICS8431-11 support four
operational modes. The four modes are spread spectrum
clocking (SSC), non-spread spectrum clock and two test
modes which are controlled by the SSC_CTL[1:0] pins. Un-
like other synthesizers, the ICS8431-11 can immediately
change spread-spectrum operation without having to reset
the device.
• PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
• 3.3V supply voltage
• 28 lead SOIC
• 0°C to 85°C ambient operating temperature
In SSC mode, the output clock is modulated in order to
achieve a reduction in EMI. In one of the PLL bypass test
modes, the PLL is disconnected as the source to the
differential output allowing an external source to be
connnected to the TEST_I/O pin. This is useful for in-
circuit testing and allows the differential output to be driven
at a lower frequency throughout the system clock tree. In the
other PLL bypass mode, the oscillator divider is used as the
source to both the M and the Fout divide by 2. This is useful
for characterizing the oscillator and internal dividers.
BLOCK DIAGRAM
PIN ASSIGNMENT
M0
M1
M2
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
VDDI
XTAL2
XTAL1
nc
XTAL1
2
3
OSC
XTAL2
M3
4
M4
M5
5
6
÷ 16
nc
M6
M7
7
8
VDDA
VEE
PLL
M8
9
MR
nc
PHASE
DETECTOR
SSC_CTL0
SSC_CTL1
VEE
TEST_I/O
VDD
10
11
12
13
14
VDDO
FOUT
nFOUT
VEE
VCO
÷ 2
FOUT
nFOUT
÷ M
ICS8431-11
28-Lead SOIC
M Package
TEST_I/O
Top View
SSC
Control
Logic
Configuration
Logic
M0:M8
nP_LOAD
SSC_CTL0 SSC_CTL1
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REV. A JULY 11, 2001
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ICS8431-11
255MHZ, LOW JITTER,
Integrated
Circuit
Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
M divider inputs. Data latched on LOW-to-HIGH transistion of
nP_LOAD input. LVCMOS / LVTTL pins interface levels.
M divider inputs. Data latched on LOW-to-HIGH transistion of
nP_LOAD input. LVCMOS / LVTTL pins interface levels.
1 - 5
M0-M6
Input
Input
6 - 8
M7-M8
Pullup
Pullup
SSC CTL0,
SSC CTL1
10, 11
12
Input
SCC control pins. LVTTL / LVCMOS interface levels.
Ground pin for core and test output.
VEE
Power
Input /
Output
13
TEST I/O
Programmed as input in PLL bypass mode.
14
15
VDD
VEE
Power
Power
Power supply pin for core and test output.
Ground pin for output.
These differential outputs are main output drivers for the synthesizer.
They are compatible with terminated positive referenced LVPECL
logic.
16, 17
nFOUT, FOUT
Output
18
19, 23, 24
20
VDDO
nc
Power
Unused
Input
Power supply pin for output.
No connection.
MR
Pulldown Reset M counter. Forces FOUT low.
Ground pin.
21
VEE
Power
Power
Input
22
VDDA
PLL power supply pin.
25, 26
27
XTAL1, XTAL2
VDDI
Crystal oscillator input.
Power
Input
Power supply pin for core.
28
nP_LOAD
Pulldown M divider latch enable input. LVTTL / LVCMOS interface levels.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Pin Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
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ICS8431-11
255MHZ, LOW JITTER,
Integrated
Circuit
Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
TABLE 3A. SSC CONTROL INPUT FUNCTION TABLE
Inputs
TEST_I/O
SSC
Outputs
FOUT,
nFOUT
Operational Modes
Source
SSC_CTL1 SSC_CTL0
TEST_I/O
fXTAL ÷ 16 PLL bypass; Oscillator, oscillator, M and N
0
0
1
1
0
1
0
1
Internal
PLL
Disabled fXTAL ÷ 32
÷ M
dividers test mode. NOTE 1
fXTAL x M
Enabled
32
Hi-Z
Default SSC; Modulation Factor = ½ Percent
PLL Bypass Mode,
(1MHz≤ Test Clk ≤ 200MHz); NOTE 1
External Disabled
PLL Disabled
Test Clk
Input
Hi-Z
fXTAL x M
32
No SSC Modulation
NOTE 1: Used for in house debug and characterization.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
256
M8
0
128
M7
1
64
M6
0
32
M5
1
16
M4
1
8
M3
1
4
M2
1
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Count
190
191
192
193
•
190
191
192
193
•
0
1
0
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
508
509
510
508
509
510
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
NOTE 1: Assumes a 16MHz crystal.
ICS8431CM-11
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REV. A JULY 11, 2001
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ICS8431-11
255MHZ, LOW JITTER,
Integrated
Circuit
Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
0°C to 85°C
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
VDDA
VDDI
IEE
Power Supply Voltage
3.135
3.135
3.135
3.135
3.3
3.3
3.3
3.3
3.465
3.465
3.465
3.465
140
V
V
Output Power Supply Voltage
Analog Power Supply Voltage
Input Power Supply Voltage
V
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
M0:M8, SSC_CTL0,
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage SSC_CTL1, MR,
TEST_I/O, nP_LOAD
M0:M8, SSC_CTL0,
Input Low Voltage SSC_CTL1, MR,
TEST_I/O, nP_LOAD
3.135V ≤ VDD ≤ 3.465V
2
VDD + 0.3
0.8
V
V
VIL
IIH
3.135V ≤ VDD ≤ 3.465V
-0.3
M7, M8, SSC_CTL0,
VDD = VIN = 3.465V
VDD = VIN = 3.465V
5
µA
µA
µA
µA
SSC_CTL1, TEST_IO
Input High Current
M0:M6,
150
nP_LOAD, MR
M7, M8, SSC_CTL0,
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-150
-5
SSC_CTL1, TEST_IO
IIL
Input Low Current
M0:M6,
nP_LOAD, MR
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VDDO - 1.28
VDDO - 2.0
600
Typical
Maximum
VDDO - 0.98
VDDO - 1.7
850
Units
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VOL
V
VSWING Peak-to-Peak Output Voltage Swing
700
mV
NOTE 1: Output terminated with 50Ω to VDDO - 2V.
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REV. A JULY 11, 2001
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ICS8431-11
255MHZ, LOW JITTER,
Integrated
Circuit
Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
16.0
MHz
ppm
ppm
µW
Ω
Frequency Tolerance
Frequency Stability
Drive Level
-50
+50
+100
100
50
-100
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance
Series Pin Inductance
Operating Temperature Range
Aging
3
10
3
7
pF
18
32
pF
7
nH
0
70
°C
Per year @25°C
-5
+5
ppm
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C, 16MHZ CRYSTAL
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
Fave
Average Output Frequency; NOTE 4
-750
+750
30
ppm
ps
FOUT = 200 MHz
18
Cycle-to-Cycle Jitter; NOTE 2
t
jit(cc)
35
ps
odc
tR
Output Duty Cycle; NOTE 2
Output Rise Time; NOTE 1, 2
Output Fall Time; NOTE 1, 2
Crystal Input Range; NOTE 3
47
300
300
14
53
%
20% to 80%
20% to 80%
450
450
16
600
600
20
ps
tF
ps
Fxtal
MHz
SSC Modulation Frequency;
NOTE 1, 2
SSC Modulation Factor;
NOTE 1, 2
Fm
30
33.33
0.6
KHz
%
Fmf
0.4
10
SSCred
Spectral Reduction; NOTE 1, 2
Power-up to Stable Clock Output
7
dB
ms
tSTABLE
10
NOTE 1: Spread Spectrum clocking enabled.
NOTE 2: Outputs terminated with 50Ω to VDDO - 2V.
NOTE 3: Only valid within the VCO operating range.
NOTE 4: Without external crystal components.
t
jit(cc), tR, tF, odc conform to JEDEC JESD65 definitions.
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REV. A JULY 11, 2001
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ICS8431-11
255MHZ, LOW JITTER,
Integrated
Circuit
Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
80%
80%
Vswing
20%
20%
Clock Inputs
and Outputs
➤
➤
➤
➤
trise
tfall
FIGURE 1 — INPUT AND OUTPUT SLEW RATES
FOUT
nFOUT
➤
➤
tcycle n+1
tcycle n
➤
➤
tjit(cc) = tcycle n –tcycle n+1
FIGURE 2 — CYCLE-TO-CYCLE JITTER
nFOUT
FOUT
Pulse Width (tPW
)
tPERIOD
tPW
odc =
tPERIOD
FIGURE 3 — odc & tPERIOD
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ICS8431-11
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Integrated
Circuit
Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS8431-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A16MHz series-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLLoperates over
a range of 190 to 510MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle.
The programmable features of the ICS8431-11 support four output operational modes and a programmable PLL loop divider.
The four output operational modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes and
are controlled by the SSC_CTL[1:0] pins.
The PLL loop divider or M divider is programmed by using inputs M0 through M8. While the nP_LOAD input is held LOW, the
data present at M0:M8 is transparent to the M-divider. On the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is latched
into the M-divider and any further changes at the M0:M8 inputs will not be seen by the M-divider until the next LOW transition
on nP_LOAD.
The relationship between the VCO frequency, the crystal frequency and the loop counter/divider is defined as follows:
fxtal
x
fVCO =
M
16
The M count and the required values of M0:M8 for programming the VCO are shown in Table 3B, Programmable VCO Frequency
Function Table. The frequency out is defined as follows:
fVCO fxtal x M
FOUT
=
=
2
32
For the ICS8431-11, the output divider equals 2. Valid M values for which the PLL will achieve lock are defined as 190 ≤ M ≤ 510.
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Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
CRYSTAL INPUT AND OSCILLATOR INTERFACE
The ICS8431-11 features an internal oscillator that uses an
external quartz crystal as the source of its reference frequency.
A 16MHz crystal divided by 16 before being sent to the phase
detector provides the reference frequency. The oscillator is a
series resonant, multi-vibrator type design. This design provides
better stability and eliminates the need for large on chip capacitors.
Though a series resonant crystal is preferred, a parallel resonant
crystal can be used. A parallel resonant mode crystal used in a
series resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified. A few hundred ppm translates
to KHz inaccuracy. In general computing applications this level
of inaccuracy is irrelevant. If better ppm accuracy is required, an
external capacitor can be added to a parallel resonant crystal in
series to pin 25. Figure 1A shows how to interface with a crystal.
ICS8431-11
XTAL2
(Pin 26, SOIC)
XTAL1
(Pin 25, SOIC)
Optional
FIGURE 1A. CRYSTAL INTERFACE
Figures 1A, 1B, and 1C show various crystal parameters
which are recommended only as guidelines. Figure 1A shows
how to interface a capacitor with a parallel resonant crystal.
Figure 1B shows the capacitor value needed for the optimum
PPM performance over various parallel resonant crystals.
Figure 1C shows the recommended tuning capacitance for a
various parallel resonant crystal.
FIGURE 1B. Recommended tuning capacitance for various parallel FIGURE 1C. Recommended tuning capacitance for various
resonant crystals.
parallel resonant crystal.
60
100
80
60
40
20
0
14.318
50
15.000
40
30
20
10
0
16.667
19.440
20.000
-20
-40
24.000
0
10
20
30
40
50
60
-60
-80
14 15 16 17 18 19 20 21 22 23 24 25
Crystal Frequency (MHz)
-100
19.44MHz
16MHz
Series Capacitor, C1 (pF)
15.00MHz
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ICS8431-11
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LVPECLFREQUENCY SYNTHESIZER
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation tech- The ICS8431-11 triangle modulation frequency deviation will
nique for EMI reduction. When spread-spectrum is enabled, a
not exceed 0.6% down-spread from the nominal clock fre-
30KHz triangle waveform is used with 0.5% down-spread quency (+0.0%/-0.5%). An example of the amount of down
(+0.0% / -0.5%) from the nominal 200MHz clock frequency. spread relative to the nominal clock frequency can be seen in
An example of a triangle frequency modulation profile is shown the frequency domain, as shown in Figure 3. The ratio of this
in Figure 2 below. The ramp profile can be expressed as:
width to the fundamental frequency is typically 0.4%, and will
not exceed 0.6%. The resulting spectral reduction will be
greater than 7dB, as shown in Figure 3. It is important to note
the ICS8431-11 7dB minimum spectral reduction is the com-
ponent-specific EMI reduction, and will not necessarily be the
same as the system EMI reduction.
• Fnom = Nominal Clock Frequency in Spread OFF mode
(200MHz with 16MHz IN)
• Fm = Nominal Modulation Frequency (30KHz)
• δ = Modulation Factor (0.5% down spread)
1
(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t <
,
2 fm
1
1
fm
(1 - δ) fnom - 2 fm x δ x fnom x t when
< t <
2 fm
Fnom
∆ − 10 dBm
A
B
(1 - δ) Fnom
δ = .4%
➤
1/fm
0.5/fm
FIGURE 3. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
FIGURE 2. TRIANGLE FREQUENCY MODULATION
(A) SPREAD-SPECTRUM OFF
(B) SPREAD-SPECTRUM ON
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8431-11 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDI, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be used
for each pin. To achieve optimum jitter performance, better
power supply isolation is required. Figure 4 illustrates how a
10Ω along with a 10µF and a .01µF bypass capacitor should
be connected to each power supply pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10 µF
FIGURE 4. POWER SUPPLY FILTERING
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ICS8431-11
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LVPECLFREQUENCY SYNTHESIZER
TERMINATION FOR PECL OUTPUTS
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. There are a few simple termination
schemes. Figures 5A and 5B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/PECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
Zo = 50Ω
5
2
5
Zo
Zo
2
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
50Ω
Zo = 50Ω
FOUT
FIN
50Ω
➤
Zo = 50Ω
Zo = 50Ω
VCC-2V
RTT
1
3
2
3
Zo
RTT =
Zo
Zo
2
(VOH + VOL / VCC –2) –2
FIGURE 5A. LVPECLOUTPUT TERMINATION
FIGURE 5B. LVPECLOUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8431-11 layout example used in this layout guideline is shown in Figure 6A. The ICS8431-11 recommended
PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of
the P.C. board.
U1
C6
0.01uF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
M0
M1
M2
M3
M4
M5
M6
M7
nP_LOAD
VDDI
XTAL1
XTAL2
NC
NC
VDDA
NC
NC
NC
VDDO
FOUT
nFOUT
GND
VDD
Termination A
Termination
B (not shown
in the layout)
X1
R5
10
VDDA
VDD0
M8
C3
0.01uF
C4
SSC_CTL0
SSC_CTL1
GND
TEST_IO
VDD
VDD
10uF
IN+
IN-
R1
125
VDD
Zo = 50 Ohm
IN+
TL1
8431-11
R3
125
R2
50
R1
50
C1
0.1uF
Zo = 50 Ohm
IN-
C2
0.1uF
TL2
R2
84
R4
84
R3
50
FIGURE 6A. RECOMMENDED SCHEMATIC LAYOUT
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ICS8431CM-11
REV. A JULY 11, 2001
ICS8431-11
255MHZ, LOW JITTER,
Integrated
Circuit
Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example:
traces should be routed first and should be locked prior to routing
other signals traces.
• The traces with 50Ω transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other.Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C1, C2 and C3, C4, C5, C6 as
close as possible to the power pins. If space allows, placing the
decoupling capacitor at the component side is preferred. This can
reduce unwanted inductance between the decoupling capacitor
and the power pin generated by the via.
• Keep the clock trace on same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace
can affect the trace characteristic impedance and hence
degrade signal quality.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
If VDDAshares the same power supply with VDD, insert the RC
filter R5, C3, and C4 in between. Place this RC filter as close to
the VDDAas possible.
• Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should be
located as close to the receiver input pins as possible. Other termi-
nation scheme can also be used but is not shown in this example.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
the component location. While routing the traces, the clock signal
CRYSTAL
The crystal X1 should be located as close as possible to the pins
26 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
U1
ICS8431-11
GND
VDD
C6
X1
Signals
VIA
C3
C4
R5
Close to the input
pins of the
receiver
R1
C2
R2
TL1 (50 Ohm)
TL2 (50 Ohm)
IN+
IN-
C1
R3
R4
FIGURE 6B. PCB BOARD LAYOUT FOR ICS8431-11
ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
11
ICS8431-11
255MHZ, LOW JITTER,
Integrated
Circuit
Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
PACKAGE OUTLINE - M SUFFIX
C
N
28
15
14
L
E
H
1
h x 45º
α
D
A2
A
e
A1
SEATING
PLANE
B
.10 (.004)
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Inches
MIN
MAX
MIN
MAX
N
A
28
--
2.65
--
--
0.104
--
A1
A2
B
0.10
2.05
0.33
0.18
17.70
7.40
0.0040
0.081
0.013
0.007
0.697
0.291
2.55
0.51
0.32
18.40
7.60
0.100
0.020
0.013
0.724
0.299
C
D
E
e
1.27 BASIC
0.050 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
0.394
0.010
0.016
0°
0.419
0.029
0.050
8°
L
α
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-013, MO-119
ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
12
ICS8431-11
255MHZ, LOW JITTER,
Integrated
Circuit
Systems, Incꢀ
LVPECLFREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8431CM-11
Marking
Package
28 Lead SOIC
Count
26 Per Tube
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8431CM-11
ICS8431CM-11
ICS8431CM-11T
28 Lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
13
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