854S14AKILFT_技术文档

PRELIMINARY

LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-

LVDS FANOUT BUFFER

ICS854S14I

GENERAL DESCRIPTION

FEATURES

The ICS854S14I is a high speed 1-to-4 Differential-

• Four differential LVDS outputs

ICS

HiPerClockS™

to-LVDS Fanout Buffer and is a member of the

HiPerClockS™ family of high performance clock

• IN, nIN pair can accept the following differential input levels:

LVPECL, LVDS, SSTL

solutions from IDT. The ICS854S14I is optimized

for high speed and very low output skew, making

• 50Ω internal input termination to V_T

• Output frequency: 1.5GHz

it suitable for use in demanding applications such as SONET,

1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The

internally terminated differential input and V^REF_AC pin allow

other differential signal families such as LVPECL, LVDS, and

SSTL to be easily interfaced to the input with minimal use of

external components. The device also has output enable pins

which may be useful for system test and debug purposes.

• Output skew: 30ps (typical)

• Part-to-part skew: TBD

• Additive phase jitter, RMS: 0.135ps (typical)

• Propagation delay: 1.1ns (typical)

• 2.5V operating supply

APPLICATIONS:

• -40°C to 85°C ambient operating temperature

• Processor clock distribution

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

• 622MHz central office clock distribution

• High speed network routing

• Wireless basestations

• Serdes LVPECL output to FPGA LVDS input translator

• Fibre channel clock distribution

• AMC clock driver for ATCA systems

• Gigabit ethernet clock distibution

BLOCK DIAGRAM

PIN ASSIGNMENT

OE0

24 23 22 21 20 19

Q0

nQ0

1

2

3

18

17

16

GND

Q0

VDD

Q3

OE1

nQ0

nQ3

IN

nQ1

Q1

4

15 nQ2

14 Q2

Q1

50Ω

5

6

V_T

nQ1

50Ω

13

V^DD

GND

nIN

OE2

7

8

9 10 11 12

Q2

V_{REF_AC}

nQ2

ICS854S14I

OE3

24-Lead VFQFN

Q3

4mm x 4mm x 0.95 package body

K Package

nQ3

Top View

The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization

and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER

PRELIMINARY

TABLE 1. PIN DESCRIPTIONS

Number

Name

GND

Type

Power

Description

1, 12, 13, 24

Power supply ground.

2, 3

Q0, nQ0

nQ1, Q1

V_DD

Output

Power

Input

Differential output pair. LVDS interface levels.

Positive supply pins.

4, 5

6, 7, 18, 19

8

9

nIN

Inverting differential clock input. 50Ω internal input termination to V_T.

Termination input.

V_T

Input

10

IN

Input

Non-inverting differential clock input. 50Ω internal input termination to V_T.

Reference voltage for AC-coupled applications.

Differential output pair. LVDS interface levels.

11

V_{REF_AC}

Q2, nQ2

nQ3, Q3

Output

14, 15

16, 17

Active high output enable. When logic HIGH, the output pair is enabled.

When logic LOW, the output pair is in a high impedance state. The OEx

pins have an internal pullup resistor so the default power-up state of the

outputs are enabled. LVCMOS/LVTTL interface levels.

20, 21,

22, 23

OE3, OE2,

OE1, OE0

Input

Pullup

NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

R_PULLUP

Input Pullup Resistor

51

kΩ

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PRELIMINARY

TABLE 3. OEX TRUTH TABLE

Inputs

Outputs

IN

0

nIN

1

OE0

Q0

0

nQ0

1

0

1

0

1

0

X

IN

0

X

HI-Z

Q1

0

HI-Z

nQ1

1

nIN

1

OE1

1

0

1

0

X

IN

0

X

0

HI-Z

Q2

0

HI-Z

nQ2

1

nIN

1

OE2

1

0

1

0

X

IN

0

X

0

HI-Z

Q3

0

HI-Z

nQ3

1

nIN

1

OE3

1

0

1

0

X

0

HI-Z

IN

nIN

Enabled

Disabled

OE[0:3]

Q[0:3]

High Impedance State

nQ[0:3]

FIGURE 1. OE TIMING DIAGRAM

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PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device.These ratings are stress specifications only. Functional op-

eration of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

Supply Voltage, V

4.6V

DD

Inputs, V

-0.5V to V_DD+ 0.5 V

I

Outputs, I_O(LVDS)

Continuous Current

Surge Current

10mA

15mA

Input Current, IN, nIN

50mA

V_TCurrent, I_VT

100mA

Input Sink/Source, I_{REF_AC}

Operating Temperature Range, TA

Storage Temperature, T_STG

0.5mA

-40°C to +85°C

-65°C to 150°C

50.2°C (0 mps)

Package Thermal Impedance, θ_JA

(Junction-to-Ambient)

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD= 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

2.5

Maximum Units

V_DD

I_DD

Positive Supply Voltage

Power Supply Current

2.375

2.625

V

88

mA

TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V_DD= 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical

Maximum Units

V_IH

V_IL

I_IH

Input High Voltage

1.7

0

V_DD+ 0.3

V

Input Low Voltage

0.7

5

Input High Current OE[0:3]

V_DD= V_IN= 2.625V

µA

I_IL

Input Low Current

OE[0:3]

V_DD= 2.625V, V_IN= 0V

-150

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V_DD= 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

IN-to-VT

Minimum

Typical

50

Maximum Units

R_IN

Differential Input Resistance (IN, nIN)

40

1.2

0

60

V_DD

Ω

V

V_IH

Input High Voltage

Input Low Voltage

Input Voltage Swing

Reference Voltage

(IN, nIN)

V_IL

V_IH- 0.15

2.8

V

V_IN

0.15

V

V_{REF_AC}

V_{DIFF_IN}

I_IN

V_DD- 1.42 V_DD- 1.37 V_DD- 1.32

V

Differential Input Voltage Swing

Input Current% NOTE 1 (IN, nIN)

0.3

3.4

35

V

mA

NOTE 1: Guaranteed by design.

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TABLE 4D. LVDS DC CHARACTERISTICS, V_DD= 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

350

50

Maximum Units

V_OD

Differential Output Voltage

mV

V

Δ V_OD

V_OS

V_ODMagnitude Change

Offset Voltage

1.2

Δ V_OS

V_OSMagnitude Change

50

mV

TABLE 5. AC CHARACTERISTICS, V_DD= 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Condition

Minimum Typical Maximum Units

f_MAX

Maximum Output Frequency

1.5

GHz

Propagation Delay% (Differential)%

NOTE 1

t_PD

1.1

ns

tsk(o)

Output Skew% NOTE 2, 4

30

ps

tsk(pp)

Part-to-Part Skew% NOTE 3, 4

TBD

Buffer Additive Phase Jitter, RMS%

refer to Additive Phase Jitter section

200MHz, Integration Range:

12kHz - 20MHz

tjit

0.135

170

ps

t_R/t_F

Output Rise/Fall Time

20ꢀ to 80ꢀ

All parameters are measured at ≤ 1GHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

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PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

V_DD

SCOPE

Qx

V_DD

nIN

2.5V 5ꢀ

POWER SUPPLY

V_IN

+

Float GND –

V_IH

LVDS

Cross Points

V_IL

IN

nQx

GND

OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

nQx

PART 1

Qx

nQx

Qx

nQy

PART 2

Qy

tsk(pp)

tsk(o)

PART-TO-PART SKEW

OUTPUT SKEW

nIN

IN

80ꢀ

t_F

80ꢀ

V_OD

Clock

20ꢀ

nQ0:nQ3

Outputs

t_R

Q0:Q3

t_PD

OUTPUT RISE/FALL TIME

PROPAGATION DELAY

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PRELIMINARY

V_DD

out

➤

V_IN, V_OUT

V_{DIFF_IN}, V_{DIFF_OUT}

DC Input

LVDS

400mV

(typical)

800mV

(typical)

V_OS/Δ V_OS

➤

SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING

OFFSET VOLTAGE SETUP

V_DD

➤

out

LVDS

DC Input

100

V

_OD/Δ V_OD

➤

out

DIFFERENTIAL OUTPUT VOLTAGE SETUP

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PRELIMINARY

APPLICATION INFORMATION

LVPECL INPUT WITH BUILT-IN 50ΩTERMINATIONS INTERFACE

The IN /nIN with built-in 50Ω terminations accepts LVDS,

common driver types. The input interfaces suggested here are

examples only. If the driver is from another vendor, use their

termination recommendation. Please consult with the vendor

of the driver component to confirm the driver termination

requirements.

LVPECL, LVHSTL, CML, SSTL and other differential signals.

The signal must meet the V and V

input requirements.

PP

CMR

Figures 2A to 2F show interface examples for the HiPerClockS

IN/nIN input with built-in 50Ω terminations driven by the most

2.5V

3.3V or 2.5V

2.5V

Zo = 50 Ohm

IN

VT

nIN

VT

nIN

Receiver

With

Receiver

With

Built-In

50 Ohm

2.5V LVPECL

LVDS

R1

18

Built-In

50 Ohm

FIGURE 2A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω

FIGURE 2B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω

DRIVEN BY AN LVDS DRIVER

DRIVEN BY AN LVPECL DRIVER

2.5V

Zo = 50 Ohm

IN

VT

nIN

VT

nIN

Receiver

With

Receiver

With

CML - Built-in 50 Ohm Pull-up

CML - Open Collector

Built-In

50 Ohm

Built-In

50 Ohm

FIGURE 2D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω

DRIVEN BY A CML DRIVER WITH

FIGURE 2C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω

DRIVEN BY AN OPEN COLLECTOR CML DRIVER

BUILT-IN 50Ω P^ULLUP

2.5V

3.3V

Zo = 50 Ohm

C1

C2

3.3V LVPECL

3.3V CML with

Built-In Pullup

Zo = 50 Ohm

C1

C2

IN

50 Ohm

VT

nIN

REF_AC

Receiver with Built-In 50Ω

REF_AC

Receiver with Built-In 50Ω

R5

100 - 200 Ohm

R5

100 - 200 Ohm

FIGURE 2E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω

FIGURE 2F. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω

DRIVEN BY A 3.3V CML DRIVER WITH

BUILT-IN PULLUP

DRIVEN BY A 3.3V LVPECL DRIVER

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PRELIMINARY

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

LVCMOS CONTROL PINS:

OUTPUTS:

LVDS Output

All control pins have internal pull-ups; additional resistance is

not required but can be added for additional protection. A 1kΩ

resistor can be used.

All unused LVDS outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

2.5V LVDS DRIVER TERMINATION

Figure 3 shows a typical termination for LVDS driver in

characteristic impedance of 100Ω differential (50Ω single)

transmission line environment. For buffer with multiple LVDS

driver, it is recommended to terminate the unused outputs.

2.5V

LVDS_Driv er

+

R1

100

-

100 Ohm Differential Transmission Line

100Ω DifferentialTransmission Line

FIGURE 3. TYPICAL LVDS DRIVER TERMINATION

THERMAL RELEASE PATH

The expose metal pad provides heat transfer from the device to

the P.C. board. The expose metal pad is ground pad connected

to ground plane through thermal via. The exposed pad on the

device to the exposed metal pad on the PCB is contacted through

solder as shown in Figure 4. For further information, please refer

to the Application Note on Surface Mount Assembly of Amkor’s

Thermally /Electrically Enhance Leadframe Base Package, Amkor

Technology.

EXPOSED PAD

SOLDER

SOLDER MASK

SIGNAL

TRACE

SIGNAL

TRACE

GROUND PLANE

Expose Metal Pad

(GROUND PAD)

THERMAL VIA

FIGURE 4. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE

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PRELIMINARY

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS854S14I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS854S14I is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V = 2.5V + 5ꢀ = 2.625V, which gives worst case results.

DD

•

Power_ = V

* I

= 2.625V * 88mA = 231mW

DD_MAX

MAX

DD_MAX

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

TM

device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = θ_JA* Pd_total + T_A

Tj = Junction Temperature

θ_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JAmust be used. Assuming a

moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 43.9°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.231W * 43.9°C/W = 95.1°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and

the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θ FOR 24-PIN VFQFN, FORCED CONVECTION

JA

θ by Velocity (Meters per Second)

JA

0

1

2.5

39.3°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

50.2°C/W

43.9°C/W

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PRELIMINARY

RELIABILITY INFORMATION

TABLE 7. θ VS. AIR FLOW TABLE FOR 24 LEAD VFQFN

JA

θ vs. 0 Air Flow (Meters per Second)

JA

0

1

2.5

39.3°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

50.2°C/W

43.9°C/W

TRANSISTOR COUNT

The transistor count for ICS854S14I is: 288

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PRELIMINARY

P^ACKAGEOUTLINE - K SUFFIX FOR 24 LEAD VFQFN

TABLE 8. PACKAGE DIMENSIONS FOR 24 LEAD VFQFN

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

SYMBOL

MINIMUM

MAXIMUM

N

A

24

0.80

0

1.0

A1

A3

b

0.05

0.25 Reference

0.18

0.30

e

0.50 BASIC

N_D

N_E

D

6

4

D2

E

2.30

2.55

4

E2

L

2.30

0.30

2.55

0.50

Reference Document: JEDEC Publication 95, MO-220

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PRELIMINARY

TABLE 9. ORDERING INFORMATION

Part/Order Number

854S14AKI

Marking

TBD

Package

Shipping Packaging

tube

Temperature

24 Lead VFQFN,

-40°C to 85°C

854S14AKT

TBD

24 Lead VFQFN

2500 tape & reel

tube

854S14AKILF

854S14AKILFT

S14AIL

24 Lead "Lead-Free" VFQFN

2500 tape & reel

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and

industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT

reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

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PRELIMINARY

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

800-345-7015

408-284-8200

Fax: 408-284-2775

For Tech Support

netcom@idt.com

480-763-2056

Corporate Headquarters

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138

Asia Pacific and Japan

Integrated Device Technology

Singapore (1997) Pte. Ltd.

Reg. No. 199707558G

435 Orchard Road

Europe

IDT Europe, Limited

321 Kingston Road

Leatherhead, Surrey

KT22 7TU

United States

800 345 7015

#20-03 Wisma Atria

England

+408 284 8200 (outside U.S.)

Singapore 238877

+44 (0) 1372 363 339

Fax: +44 (0) 1372 378851

+65 6 887 5505

of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be

trademarks or registered trademarks used to identify products or services of their respective owners.

Printed in USA


型号：	854S14AKILFT
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Skew Clock Driver, 854S Series, 4 True Output(s), 0 Inverted Output(s), 4 X 4 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VQFN-24 驱动逻辑集成电路
文件：	总14页 (文件大小：288K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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