854S54AKI-01LFT [IDT]
Dual 2:1, 1:2 Differential-to-LVDS Multiplexer;
| 型号： | 854S54AKI-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual 2:1, 1:2 Differential-to-LVDS Multiplexer |
| 文件： | 总17页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 2:1, 1:2 Differential-to-LVDS
Multiplexer
ICS854S54I-01
Datasheet
Description
Features
The ICS854S54I-01 is a 2:1/1:2 Multiplexer. The 2:1 Multiplexer
allows one of two inputs to be selected onto one output pin and the
1:2 MUX switches one input to both outputs. This device may be
useful for multiplexing multi-rate Ethernet PHYs which have 100Mbit
and 1000Mbit transmit/receive pairs onto an optical SFP module
which has a single transmit/receive pair. Another mode allows loop
back testing and allows the output of a PHY transmit pair to be routed
to the PHY input pair. For examples, please refer to the Application
Information section of the data sheet.
• Dual 2:1, 1:2 MUX
• Three LVDS output pairs
• Three differential clock inputs can accept: LVPECL, LVDS, CML
• Loopback test mode available
• Maximum output frequency: 2.5GHz
• Propagation delay: 600ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Additive phase jitter, RMS: 0.031ps (typical)
• Full 2.5V supply mode
The ICS854S54I-01 is optimized for applications requiring very high
performance and has a maximum operating frequency of 2.5GHz.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Pin Assignment
Block Diagram
SELB
16 15 14 13
1
2
3
12
11
10
QA0
nQA0
QA1
INA0
nINA0
INA1
INA0
nINA0
nQA1
4
nINA1
9
5
6
7
8
INB
LOOP0
0
nINB
QA0
ICS854S54I-01
nQA0
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
Top View
1
0
QB
nQB
INA1
1
nINA1
LOOP1
QA1
nQA1
SELA
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ICS854S54I-01 Datasheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 2
Name
QA0, nQA0
QA1, nQA1
INB
Type
Description
Output
Output
Input
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Non-inverting differential clock input.
3, 4
5
Pulldown
Pullup/
Pulldown
6
nINB
Input
Inverting differential clock input. VDD/2 default when left floating.
Select pin for QAx outputs. When HIGH, selects same inputs used for QB output.
When LOW, selects INB input. LVCMOS/LVTTL interface levels.
7
8
SELB
GND
Input
Power
Input
Input
Input
Pulldown
Power supply ground.
Pullup/
Pulldown
9
nINA1
INA1
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
10
11
Pulldown
Pullup/
Pulldown
nINA0
Inverting differential clock input. VDD/2 default when left floating.
12
13
INA0
VDD
Input
Pulldown
Non-inverting differential clock input.
Power supply pin.
Power
Select pin for QB outputs. When HIGH, selects INA1 input.
When LOW, selects INA0 input. LVCMOS/LVTTL interface levels.
14
SELA
Input
Pulldown
15, 16
nQB, QB
Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
37.5
Maximum
Units
k
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
37.5
k
Function Tables
Table 3. Control Input Function Table
Control Inputs
SELA
SELB
Mode
0
1
0
1
0
0
1
1
LOOP0 selected (default)
LOOP1 selected
Loopback mode: LOOP0
Loopback mode: LOOP1
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DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
74.7C/W (0 mps)
-65C to 150C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
VDD Positive Supply Voltage
IDD Power Supply Current
Test Conditions
Minimum
Typical
Maximum
2.625
82
Units
V
2.375
2.5
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
VDD + 0.3
0.7
Units
V
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
1.7
0
VIL
V
IIH
SELA, SELB
SELA, SELB
VDD = VIN = 2.625V
150
µA
µA
IIL
VDD = 2.625V, VIN = 0V
-150
Table 4C. DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Min
Typ
Max
Min
Max
Min
Max
Units
Input
IIH
INAx, INB
nINAx, nINB
150
150
150
µA
High Current
INAx, INB
-10
-150
0.15
-10
-150
0.15
-10
-150
0.15
µA
µA
V
Input
IIL
Low Current
nINAx, nINB
VPP
Peak-to-Peak Input Voltage
1.2
1.2
1.2
Common Mode Input Voltage;
NOTE 1
VCMR
1.2
VDD
1.2
VDD
1.2
VDD
V
NOTE 1: Common mode input voltage is defined as VIH.
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Table 4D. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
-40°C
25°C
Typ
350
85°C
Symbol Parameter
Min
Typ
Max
454
60
Min
Max
454
60
Min
Typ
Max
454
60
Units
mV
mV
V
VOD
Differential Output Voltage
247
350
247
247
350
VOD
VOS
VOD Magnitude Change
Offset Voltage
1.125
1.25
1.375
50
1.125
1.25
1.375
50
1.125
1.25
1.375
50
VOS
VOS Magnitude Change
mV
NOTE: Refer to Parameter Measurement Information, 2.5V Output Load Test Circuit diagram.
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
2.5
Units
GHz
ps
fOUT
Output Frequency
INAx to QB or INB to QAx
INAx to QAx
250
300
600
tPD
Propagation Delay; NOTE 1
600
ps
tsk(pp)
tjit
Part-to-Part Skew; NOTE 2, 3
300
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
ƒOUT = 622.08MHz,
12kHz – 20MHz
0.031
65
ps
ps
dB
tR / tF
Output Rise/Fall Time
20% to 80%
60
300
ƒOUT = 500MHz output,
VPP = 400mV
MUX_ISOLATION MUX Isolation; NOTE 4
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: All parameters measured at 1.7GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Q, nQ output measured differentially. See MUX Isolation Diagram in Parameter Measurement Information section.
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DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 0.031ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator.
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DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Parameter Measurement Information
V
DD
nINA[0:1], nINB
INA[0:1], INB
GND
VPP
VCMR
Cross Points
V
DD
LVDS Output Load AC Test Circuit
Differential Input Level
Spectrum of Output Signal Q
MUX selects active
input clock signal
A0
A1
Part 1
nQx
Qx
MUX_ISOL = A0 – A1
Part 2
nQy
MUX selects static input
Qy
tsk(pp)
ƒ
Frequency
(fundamental)
Part-to-Part Skew
MUX Isolation
nINA[0:1],
nINB
nQA[0:1],
nQB
INA[0:1],
INB
80%
80%
tR
VOD
20%
nQA[0:1],
nQB
QA[0:1],
QB
20%
QA[0:1],
QB
tF
tPD
Output Rise/Fall Time
Propagation Delay
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DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Parameter Measurement Information, continued
Offset Voltage Setup
Differential Output Voltage Setup
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DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VDD/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
IN/nIN Inputs
LVDS Outputs
For applications not requiring the use of the differential input, both INx
and nINx can be left floating. Though not required, but for additional
protection, a 1k resistor can be tied from INx to ground.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, we recommend that there
is no trace attached.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
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DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Differential Clock Input Interface
The IN /nIN accepts LVPECL, CML, LVDS and other differential
signals. The differential signal must meet the VPP and VCMR input
requirements. Figures 2A to 2D show interface examples for the IN
/nIN input driven by the most common driver types. The input
interfaces suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
2.5V
2.5V
3.3V
3.3V
Zo = 50Ω
R1
R2
50Ω
50Ω
Zo = 50Ω
Zo = 50Ω
IN
IN
R1
100Ω
nIN
Zo = 50Ω
LVPECL
nIN
LVPECL
Differential
Inputs
Differential
Inputs
CML Built-In Pullup
CML
Figure 2A. IN/nIN Input Driven by an
Open Collector CML Driver
Figure 2B. IN/nIN Input Driven by a
Built-In Pullup CML Driver
3.3V
2.5V
2.5V
3.3V
3.3V
R1
R3
Zo = 50Ω
125Ω
125Ω
Zo = 50Ω
Zo = 50Ω
IN
IN
R1
100Ω
nIN
nIN
LVPECL
Zo = 50Ω
LVPECL
Differential
Inputs
LVPECL
Differential
Input
LVDS
R2
84Ω
R4
84Ω
Figure 2C. IN/nIN Input Driven by a 3.3V LVPECL Driver
Figure 2D. IN/nIN Input Driven by a 3.3V LVDS Driver
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DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
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DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. Standard termination
for LVDS type output structure requires both a 100 parallel resistor
at the receiver and a 100 differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 4 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the input receivers amplitude and
common mode input range should be verified for compatibility with
the output.
+
LVDS
Receiver
–
LVDS Driver
100Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
Internal
Connector
Host Adapter Board
SELB
INA0
nINA0
INB
nINB
QA0
SerDes
Protocol
Controller
nQA0
0
QB
nQB
INA1
1
nINA1
QA1
nQA1
SELA
PCI Bus
Figure 5. Typical Application Diagram for Host Bus Adapter Boards for routing Between Internal and External
Connectors
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DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
SELB
LOOP 0
INA0
nINA0
QA0
INB
TX
0
1
nINB
Switch
Fabric
nQA0
INA1
0
1
SerDes
QB
nQB
nINA1
QA1
RX
nQA1
#0
SELA
LOOP 1
#1
Redundant
Switch Card
Linecard
Backplane
Figure 6. Typical Application Diagram for Hot Swappable Links to Redundant Switch Fabric Cards
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DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S54I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S54I-01 is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 82mA = 214.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.215W * 74.7°C/W = 101.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 16 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
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Reliability Information
Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
Transistor Count
The transistor count for ICS854S54I-01 is: 329
This device is pin and function compatible and a suggested replacement for ICS85454-01.
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Package Outline Drawings
Package Outline Drawings – Sheet 1
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Package Outline Drawings – Sheet 2
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Ordering Information
Table 9. Ordering Information
Part/Order Number
854S54AKI-01LF
854S54AKI-01LFT
Marking
4A01
4A01
Package
“Lead-Free” 16 Lead VFQFN
“Lead-Free” 16 Lead VFQFN
Shipping Packaging
Tube
2500 Tape & Reel
Temperature
-40C to 85C
-40C to 85C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Revision History
Revision Date
July 17, 2017
Description of Change
Updated the Package Outline Drawings. No technical changes.
Initial release.
March 29, 2010
Corporate Headquarters
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www.IDT.com
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
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without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
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