854S204BGILFT [IDT]
Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer;
| 型号： | 854S204BGILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总23页 (文件大小：1425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, Dual, Programmable 1-to-2
Differential-to-LVDS, LVPECL Fanout Buffer
ICS854S204I
DATA SHEET
General Description
Features
The ICS854S204I is a low skew, high performance dual,
• Two programmable differential LVDS or LVPECL output banks
• Two differential clock input pairs
programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer.
The PCLKx, nPCLKx pairs can accept most standard differential
input levels. With the selection of SEL_OUT signal, outputs can be
selected be to either LVDS or LVPECL levels. The ICS854S204I is
characterized to operate from either a 2.5V or a 3.3V power supply.
Guaranteed output and bank skew characteristics make the
ICS854S204I ideal for those clock distribution applications
demanding well defined performance and repeatability.
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, SSTL, CML
• Maximum output frequency: 3GHz
• Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx inputs
• Output skew: 15ps (maximum)
• Bank skew: 15ps (maximum)
• Propagation delay: 500ps (maximum)
• Additive phase jitter, RMS: 0.15ps (typical)
• Full 3.3V or 2.5V supply modes
Power Supply Configuration Table
VDD = 3.3V
3.3V Operation
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
VTAP = nc
V
DD = 2.5V
2.5V Operation
VTAP = 2.5V
SEL_OUT Function Table
SEL_OUT
Output Level
LVDS
LVPECL
0
1
Block Diagram
Pin Assignment
VTAP
PCLKA
nPCLKA
QA0
1
2
3
4
5
6
7
8
16 nPCLKB
PCLKB
14 QB0
Pulldown
15
SEL_OUT
QA0
nQA0
Pulldown
CLKA
13
12
11
10
9
nQB0
QB1
nQA0
QA1
Pullup
nCLKA
QA1
nQA1
VTAP
nQB1
VDD
nQA1
GND
SEL_OUT
QB0
nQB0
Pulldown
CLKB
ICS854S204I
Pullup
nCLKB
QB1
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
nQB1
Top View
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
PCLKA
Type
Description
1
Input
Input
Pulldown Non-inverting differential clock input.
2
nPCLKA
Pullup
Inverting differential clock input.
3, 4
5, 6
QA0, nQA0
QA1, nQA1
Output
Output
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Power supply pin. Tie to VDD for 2.5V operation. For 3.3V operation, do not
connect.
7
8
9
VTAP
GND
Power
Power
Input
Power supply ground.
Output select pin. Selects between LVDS or LVPECL outputs.
LVCMOS/LVTTL interface levels.
SEL_OUT
Pulldown
10
11, 12
13, 14
15
VDD
Power
Output
Output
Input
Power supply pin.
nQB1, QB1
nQB0, QB0
PCLKB
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
16
nPCLKB
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
1
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
Function Tables
Table 3. Clock Input Function Table
Inputs
Outputs
PCLKA or
PCLKB
nPCLKA or
nPCLKB
QA[0:1], QB[0:1]
nQA[0:1], nQB[0:1]
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
0
1
LOW
HIGH
LOW
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Biased; NOTE 1
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information, Wiring the Differential Input to Accept Single Ended Levels section.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
92°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
VDD Power Supply Voltage
IDD Power Supply Current
Test Conditions
Minimum
Typical
Maximum
3.465
Units
V
3.135
3.3
120
mA
Table 4B. LVDS Power Supply DC Characteristics, VDD = VTAP = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
115
Units
V
VDD
VTAP
IDD
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
2.375
2.5
V
mA
mA
ITAP
5
Table 4C. LVPECL Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
Maximum
3.465
66
Units
V
Power Supply Voltage
Power Supply Current
3.135
3.3
IDD
mA
Table 4D. LVPECL Power Supply DC Characteristics, VDD = VTAP = 2.5V 5%, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
60
Units
V
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
VTAP
IDD
2.375
2.5
V
mA
mA
ITAP
5
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Table 4E. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5% or VDD = VTAP = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
DD = 3.465V
VDD = 2.625V
DD = 3.465V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
V
V
2
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
V
V
Input Low Voltage
VDD = 2.625V
0.7
V
IIH
IIL
Input High Current SEL_OUT
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
150
µA
µA
Input Low Current
SEL_OUT
-10
Table 4F. Differential DC Characteristics, VDD = 3.3V 5% or VDD = VTAP = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
150
Units
µA
µA
µA
µA
V
PCLKA, PCLKB
nPCLKA, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
Input
IIH
High Current
10
-10
-150
0.15
Input
IIL
Low Current
V
DD = 3.465V or 2.625V, VIN = 0V
VPP
Peak-to-Peak Voltage
Common Mode Input Voltage;
1.3
VCMR
1.2
VDD
V
NOTE 1
NOTE 1: Common mode input voltage is defined as VIH.
Table 4G. LVDS DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
Minimum
Typical
Maximum
454
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
350
∆VOD
VOS
50
1.11
1.25
1.38
50
∆VOS
VOS Magnitude Change
mV
NOTE: Please refer to Parameter Measurement Information section for output information.
Table 4H. LVDS DC Characteristics, VDD = VTAP = 2.5V 5%, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
Minimum
Typical
Maximum
454
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
350
∆VOD
VOS
50
1.08
1.21
1.34
50
∆VOS
VOS Magnitude Change
mV
NOTE: Please refer to Parameter Measurement Information section for output information.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Table 4I. LVPECL DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
Minimum
VDD – 1.3
VDD – 2.0
0.6
Typical
Maximum
VDD – 0.8
VDD – 1.6
0.9
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VDD – 2V.
Table 4J. LVPECL DC Characteristics, VDD = VTAP = 2.5V 5%, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
Minimum
VDD – 1.3
VDD – 2.0
0.6
Typical
Maximum
VDD – 0.8
VDD – 1.55
0.9
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VDD – 2V.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
AC Electrical Characteristics
Table 5A. LVDS AC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
GHz
ps
Output Frequency
3
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 4, 6
Bank Skew; NOTE 3, 4
500
15
tsk(o)
tsk(b)
ps
15
ps
Buffer Additive Phase Jitter, RMS; Refer
to Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
tjit
0.15
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
49
200
51
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at 550MHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. LVDS AC Characteristics, VDD = VTAP = 2.5V 5%, TA = -40°C to 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
GHz
ps
Output Frequency
3
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 4, 6
Bank Skew; NOTE 3, 4
500
15
tsk(o)
tsk(b)
ps
15
ps
Buffer Additive Phase Jitter, RMS; Refer
to Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
tjit
0.13
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
49
200
51
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at 550MHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Table 5C. LVPECL AC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
GHz
ps
Output Frequency
3
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 4, 6
Bank Skew; NOTE 3, 4
500
15
tsk(o)
tsk(b)
ps
15
ps
Buffer Additive Phase Jitter, RMS; Refer
to Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
tjit
0.12
ps
t
R / tF
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
49
200
51
ps
%
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at 550MHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. LVPECL AC Characteristics, VDD = VTAP = 2.5V 5%, TA = -40°C to 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
GHz
ps
Output Frequency
3
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 4, 6
Bank Skew; NOTE 3, 4
500
15
tsk(o)
tsk(b)
ps
15
ps
Buffer Additive Phase Jitter, RMS; Refer
to Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz
tjit
0.07
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
49
200
51
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at 550MHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.12ps (typical)
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Parameter Measurement Information
2V
2V
SCOPE
SCOPE
V
V
V
DD
Qx
DD,
Qx
TAP
LVPECL
LVPECL
nQx
nQx
GND
GND
-1.3V 0.165V
-0.5V 0.125V
3.3V LVPECL Output Load AC Test Circuit
2.5V LVPECL Output Load AC Test Circuit
Float
SCOPE
SCOPE
Qx
V
V
DD,
2.5V 5%
Qx
POWER SUPPLY
V
3.3V 5%
POWER SUPPLY
AP
DD,
+
Float GND
–
+
Float GND –
LVDS
nQx
nQx
3.3V LVDS Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
V
nQXx
QXx
DD
nPCLKA, nPCLKB
nQXy
VPP
VCMR
Cross Points
PCLKA, PCLKB
GND
QXy
tsk(b)
Where X = A or B
Differential Input Level
Bank Skew
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Parameter Measurement Information, continued
nPCLKA,
nPCLKB
nQx
Qx
PCLKA,
nPCLKB
nQA[0:1]
nQB[0:1]
nQy
Qy
QA[0:1]
QB[0:1]
tsk(o)
tPD
Output Skew
Propagation Delay
nQA[0:1]
nQB[0:1]
nQA[0:1]
nQB[0:1]
80%
tF
80%
tF
80%
tR
80%
VOD
20%
VSWING
20%
QA[0:1]
QB[0:1]
QA[0:1]
20%
20%
QB[0:1]
tR
LVDS Output Rise/Fall Time
LVPECL Output Rise/Fall Time
VDD
nQA[0:1]
nQB[0:1]
out
out
QA[0:1]
QB[0:1]
tPW
➤
DC Input
LVDS
tPERIOD
tPW
VOS/∆ VOS
odc =
x 100%
➤
tPERIOD
Offset Voltage Setup
Output Duty Cycle/Pulse Width/Period
VDD
➤
out
out
LVDS
DC Input
100
V
OD/∆ VOD
➤
Differential Output Voltage Setup
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VDD/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
3.3V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2F show interface examples
for the PCLK/ nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
R1
100Ω
nPCLK
Zo = 50Ω
nPCLK
LVPECL
LVPECL
Input
CML Built-In Pullup
CML
Input
Figure 2B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Figure 2A. PCLK/nPCLK Input Driven by a CML Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
3.3V
R3
84
R4
84
Zo = 50Ω
Zo = 50Ω
C1
C2
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL
PCLK
PCLK
nPCLK
nPCLK
LVPECL
Input
LVPECL
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84Ω
R2
84Ω
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
2.5V
3.3V
3.3V
3.3V
2.5V
R3
120Ω
R4
120Ω
Zo = 50Ω
Zo = 60Ω
Zo = 60Ω
PCLK
PCLK
R1
100Ω
nPCLK
nPCLK
Zo = 50Ω
LVPECL
Input
LVPECL
Input
SSTL
LVDS
R1
R2
120Ω
120Ω
Figure 2E. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
Figure 2F. PCLK/nPCLK Input Driven by a
3.3V SSTL Driver
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface examples
for the PCLK/ nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
2.5V
2.5V
2.5V
2.5V
2.5V
R1
50Ω
R2
50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
R1
100Ω
nPCLK
Zo = 50Ω
nPCLK
LVPECL
LVPECL
Input
CML Built-In Pullup
CML
Input
Figure 3B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver
2.5V
2.5V
2.5V
2.5V
R3
R4
3.3V
250Ω
250Ω
R1
100
R3
Ω
100Ω
C1
C2
Zo = 50Ω
Zo = 50Ω
Zo = 50
Ω
Ω
PCLK
PCLK
nPCLK
nPCLK
Zo = 50
LVPECL
Input
LVPECL
3.3V LVPECL Driver
R1
R2
62.5Ω
62.5Ω
R6
100Ω-180Ω
R7
100
R2
100
R4
100
Ω
-180Ω
Ω
Ω
Figure 3C. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
Figure 3D. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
2.5V
2.5V
2.5V
2.5V
R3
R4
2.5V
120Ω
120Ω
Zo = 50Ω
Zo = 60Ω
Zo = 60Ω
PCLK
PCLK
R1
100Ω
nPCLK
nPCLK
Zo = 50Ω
LVPECL
Input
SSTL
LVPECL
Input
LVDS
R1
120Ω
R2
120Ω
Figure 3E. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
Figure 3F. PCLK/nPCLK Input Driven by a
2.5V SSTL Driver
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
PCLK/nPCLK Inputs
LVPECL Outputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100Ω across. If they are left floating, there should be no trace
attached.
Termination for 2.5V LVPECL Outputs
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω
to VDD– 2V. For VDD = 2.5V, the VDD – 2V is very close to ground
level. The R3 in Figure 4B can be eliminated and the termination is
shown in Figure 4C.
2.5V
2.5V
VDD = 2.5V
2.5V
VDD = 2.5V
R1
R3
50Ω
250
250
+
50Ω
50Ω
+
–
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
2.5V LVPECL Driver
R2
62.5
R4
62.5
R3
18
Figure 4A. 2.5V LVPECL Driver Termination Example
Figure 4B. 2.5V LVPECL Driver Termination Example
2.5V
VDD = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 4C. 2.5V LVPECL Driver Termination Example
ICS854S204BGI REVISION B NOVEMBER 18, 2011
14
©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
3.3V
3.3V
Z
o = 50Ω
3.3V
+
_
Z
o = 50Ω
+
_
Input
LVPECL
Zo = 50Ω
LVPECL
Input
Zo = 50Ω
R1
R2
50Ω
50Ω
R1
84Ω
R2
84Ω
VCC - 2V
1
RTT =
* Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
Figure 5A. 3.3V LVPECL Output Termination
Figure 5B. 3.3V LVPECL Output Termination
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90Ω and 132Ω. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100Ω parallel resistor at the receiver and a 100Ω differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 6A can be used
with either type of output structure. Figure 6B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO • ZT
LVDS
Driver
LVDS
Receiver
ZT
Figure 6A. Standard Termination
ZT
ZO • ZT
LVDS
Driver
2
ZT
2
LVDS
Receiver
C
Figure 6B. Optional Termination
LVDS Termination
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Power Considerations (3.3V LVPECL Outputs)
This section provides information on power dissipation and junction temperature for the ICS854S204I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S204I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 66mA = 228.69mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 32mW = 128mW
Total Power_MAX (3.465V, with all outputs switching) = 228.69mW + 128mW = 356.69mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 92°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.357W * 92°C/W = 117.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7A. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92°C/W
87.6°C/W
85.5°C/W
ICS854S204BGI REVISION B NOVEMBER 18, 2011
17
©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 7.
VDD
Q1
VOUT
RL
50Ω
VDD - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VDD – 2V.
•
•
For logic high, VOUT = VOH_MAX = VDD_MAX – 0.8V
(VDD_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VDD_MAX – 1.6V
(VDD_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOH_MAX) = [(2V – (VDD_MAX – VOH_MAX))/RL] * (VDD_MAX – VOH_MAX) =
[(2V – 0.8V)/50Ω] * 0.8V = 19.2mW
Pd_L = [(VOL_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOL_MAX) = [(2V – (VDD_MAX – VOL_MAX))/RL] * (VDD_MAX – VOL_MAX) =
[(2V – 1.6V)/50Ω] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
ICS854S204BGI REVISION B NOVEMBER 18, 2011
18
©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Power Considerations (3.3V LVDS Outputs)
This section provides information on power dissipation and junction temperature for the ICS854S204I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S204I is the sum of the core power plus the power dissipated in the load(s). The following is the
power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 120mA = 415.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 92°C/W per Table 7B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.416W * 92°C/W = 123.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7B. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92°C/W
87.6°C/W
85.5°C/W
ICS854S204BGI REVISION B NOVEMBER 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Reliability Information
Table 8. θJA vs. Air Flow Table for a 16 Lead TSSOP
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92°C/W
87.6°C/W
85.5°C/W
Transistor Count
The transistor count for ICS854S204I is: 454
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 9. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
16
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.5
0.80
0.19
0.09
4.90
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS854S204BGI REVISION B NOVEMBER 18, 2011
20
©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Ordering Information
Table 10. Ordering Information
Part/Order Number
854S204BGILF
854S204BGILFT
Marking
4S204BIL
4S204BIL
Package
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
21
©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T4F
4
Differential DC Characteristics Table - corrected VCMR spec from GND + 0.5V min. to
1.2V min; VDD - 0.85V max. to VDD max.
B
11/18/2011
Deleted NOTE.
Converted datasheet format.
ICS854S204BGI REVISION B NOVEMBER 18, 2011
22
©2011 Integrated Device Technology, Inc.
ICS854S204I Data Sheet
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
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IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2011. All rights reserved.
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