854S202AYIT [IDT]
Clock Driver;
| 型号： | 854S202AYIT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver |
| 文件： | 总17页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
ICS854S202I
GENERAL DESCRIPTION
FEATURES
The ICS854S202I is a 12:2 Differential-to-LVDS
• Two differential 3.3V LVDS clock outputs
ICS
Clock Multiplexer which can operate >3GHz and
is a member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. The
ICS854S202I has 12 selectable differential clock
• Twelve selectable differential clock inputs
HiPerClockS™
• CLKx, nCLKx pairs can accept the following differential input
levels: LVPECL, LVDS, HSTL, SSTL, HCSL
inputs, any of which can be independently routed to either of
the two LVDS outputs. The CLKx, nCLKx input pairs can
accept LVPECL, LVDS, CML or SSTL levels. The fully differen-
tial architecture and low propagation delay make it ideal for
use in clock distribution circuits.
•
•
•
•
•
•
•
•
•
Maximum output frequency: >3GHz
Propagation delay: 660ps (typical)
Input skew: TBD
Output skew: 25ps (typical)
Part-to-part skew: TBD
Additive phase jitter, RMS: 0.16ps (typical)
Full 3.3V operating supply mode
-40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
4
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pulldown
SELA_[3:0]
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
QA
nQA
OEA
CLK3
PIN ASSIGNMENT
nCLK3
CLK4
nCLK4
CLK5
48 47 46 45 44 43 42 41 40 39 38 37
nCLK5
CLK2
nCLK2
SELA_0
SELA_1
VDD
CLK9
1
36
35
34
33
32
31
30
29
28
27
26
25
2
nCLK9
SELB_0
SELB_1
VDD
CLK6
3
nCLK6
4
ICS854S202I
5
48-Pin LQFP
7mm x 7mm x 1.4mm
package body
CLK7
QA
QB
nQB
6
nCLK7
nQA
7
CLK8
GND
8
GND
QB
nQB
OEB
Y Package
nCLK8
SELA_2
SELA_3
CLK3
SELB_2
SELB_3
CLK8
9
Top View
10
11
12
CLK9
nCLK9
nCLK3
nCLK8
13 14 15 16 17 18 19 20 21 22 23 24
CLK10
nCLK10
CLK11
nCLK11
4
Pulldown
SELB_[3:0]
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS MULTIPLEXER
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ICS854S202I
12:2, DIFFERENTIAL-LVDS MULTIPLEXER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS (CONTINUED ON NEXT PAGE)
Number
Name
Type
Pullup
Description
1
CLK2
Input
Input
Non-inverting differential clock input.
Pullup/
Pulldown
2
nCLK2
Inverting differential clock input. VDD/2 default when left floating.
3,
4,
9,
SELA_0,
SELA_1,
SELA_2,
SELA_3
Clock select pins for Bank A outputs. See Control Input
Pulldown Function Table. LVCMOS/LVTTL interface levels.
See Table 3B.
Input
10
5, 18, 32, 43
VDD
QA, nQA
GND
Power
Output
Power
Input
Positive supply pins.
6, 7
8, 15, 22, 29, 39, 46
11
Clock outputs. LVDS interface levels.
Power supply ground.
CLK3
Pullup
Non-inverting differential clock input.
Pullup/
Pulldown
Pullup/
12
nCLK3
Input
Inverting differential clock input. VDD/2 default when left floating.
13
14
16
17
19
20
21
23
24
nCLK4
CLK4
nCLK5
CLK5
OEA
Input
Input
Input
Input
Input
Input
Input
Input
Input
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Pulldown
Pullup
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Pullup
Pullup
Pullup
Output enable pin. Controls enabling and disabling of QA/nQA
outputs. LVCMOS/LVTTL internface levels.
CLK6
nCLK6
CLK7
nCLK7
Non-inverting differential clock input.
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Pullup
Pullup/
Pulldown
Pullup/
Inverting differential clock input. VDD/2 default when left floating.
25
26
nCLK8
CLK8
Input
Input
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Pulldown
Pullup
27,
28,
33,
34
SELB_3,
SELB_2,
SELB_1,
SELB_0
Clock select pins for Bank B outputs. See Control Input
Pulldown Function Table. LVCMOS/LVTTL interface levels.
See Table 3C.
Input
30, 31
nQB, QB
nCLK9
CLK9
Output
Input
Input
Input
Input
Input
Input
Clock outputs. LVDS interface levels.
Pullup/
35
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
36
Pullup
Non-inverting differential clock input.
Pullup/
Pulldown
37
nCLK10
CLK10
nCLK11
CLK11
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
38
Pullup
Pullup/
Pulldown
40
Inverting differential clock input. VDD/2 default when left floating.
41
Pullup
Non-inverting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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PRELIMINARY
TABLE 1. PIN DESCRIPTIONS (CONTINUED ON NEXT)
Number
42
Name
OEB
Type
Pullup
Description
Output enable pin. Controls enabling and disabling of QB/nQB
outputs. LVCMOS/LVTTL internface levels. See Table 3A.
Input
Input
Input
Input
Input
44
CLK0
nCLK0
CLK1
nCLK1
Pullup
Non-inverting differential clock input.
Pullup/
Pulldown
45
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
47
Pullup
Pullup/
Pulldown
48
Inverting differential clock input. VDD/2 default when left floating.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Units
pF
Symbol Parameter
Test Conditions
Minimum Typical Maximum
CIN
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
TABLE 3B. OEA, OEB CONTROL INPUT FUNCTION TABLE
Input
Output
QA/nQA, QB/nQB
Disabled (Logic LOW)
Active
OEA, OEB
0
1
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12:2, DIFFERENTIAL-LVDS MULTIPLEXER
PRELIMINARY
TABLE 3B. SEL_A CONTROL INPUT FUNCTION TABLE
Control Input
Input Selected to QA/nQA
SELA_3
SELA_2
SELA_1
SELA_0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK0, nCLK0
CLK1, nCLK1
CLK2, nCLK2
CLK3, nCLK3
CLK4, nCLK4
CLK5, nCLK5
CLK6, nCLK6
CLK7, nCLK7
CLK8, nCLK8
CLK9, nCLK9
CLK10, nCLK10
CLK11, nCLK11
L/H
L/H
L/H
L/H
TABLE 3C. SEL_B CONTROL INPUT FUNCTION TABLE
Control Input
Input Selected to QB/nQB
SELB_3
SELB_2
SELB_1
SELB_0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK0, nCLK0
CLK1, nCLK1
CLK2, nCLK2
CLK3, nCLK3
CLK4, nCLK4
CLK5, nCLK5
CLK6, nCLK6
CLK7, nCLK7
CLK8, nCLK8
CLK9, nCLK9
CLK10, nCLK10
CLK11, nCLK11
L/H
L/H
L/H
L/H
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
I
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA 70.2°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
IDD
Core Supply Voltage
Power Supply Current
3.135
3.3
3.465
V
115
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
SELA_0:3,
SELB_0:3
V
DD = 3.3V 5ꢀ
VDD = 3.3V 5ꢀ
DD = 3.3V 5ꢀ
VDD = 3.3V 5ꢀ
150
5
µA
µA
µA
µA
IIH
Input High Current
OEA, OEB
SELA_0:3,
SELB_0:3
V
-5
IIL
Input Low Current
OEA, OEB
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
CLK0:CLK11
nCLK0:nCLK11
CLK0:CLK11
nCLK0:nCLK11
VDD = VIN = 3.465V
150
150
µA
µA
µA
µA
V
V
DD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
V
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
V
DD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V.
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12:2, DIFFERENTIAL-LVDS MULTIPLEXER
PRELIMINARY
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
410
50
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.3
Δ VOS
VOS Magnitude Change
50
mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
>3
GHz
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
tpLH
tpHL
660
660
ps
ps
tsk(o)
tsk(i)
Output Skew; NOTE 2, 3
Input Skew; NOTE 3
25
ps
ps
ps
TBD
TBD
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
155.52MHz,
Integration Range:
12kHz - 20MHz
tjit
0.16
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
110
50
ps
ꢀ
MUXISOLATION MUX Isolation
fOUT < 1.2GHz
45
dB
All parameters measured at 500MHz, unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDD/2.
NOTE 5: Driving only one input clock.
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12:2, DIFFERENTIAL-LVDS MULTIPLEXER
PRELIMINARY
ADDITIVE PHASE JITTER
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications.Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
Additive Phase Jitter @ 155.5MHz
(12kHz to 20MHz) = 0.16ps (typical)
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT™ / ICS™ LVDS MULTIPLEXER
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12:2, DIFFERENTIAL-LVDS MULTIPLEXER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
nCLK0,
nCLK11
Qx
VDD
3.3V 5ꢀ
POWER SUPPLY
VPP
VCMR
Cross Points
CLK0,
CLK11
+
Float GND –
LVDS
nQx
GND
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
Part 1
nQx
nQx
Qx
Qx
Part 2
nQy
nQy
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK0:
nCLK11
CLK0:
CLK11
80ꢀ
80ꢀ
nQA, nQB
VOD
Clock
20ꢀ
20ꢀ
QA, QB
Outputs
tPD
tF
tR
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
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PRELIMINARY
nCLK0:
nCLK11
CLK0:
CLK11
nQA, nQB
nQA, nQB
QA, QB
QA, QB
tPD1
tPW
tPERIOD
tPW
odc =
x 100ꢀ
nCLKy
CLKy
tPERIOD
nQA, nQB
QA, QB
tPD2
tsk(i) = |tPD1 - tPD2
|
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
INPUT SKEW
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
➤
out
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
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12:2, DIFFERENTIAL-LVDS MULTIPLEXER
PRELIMINARY
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUT:
LVDS OUTPUT
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias DcDircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
VDD
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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PRELIMINARY
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 2A to 2E show interface
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types.The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 2A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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PRELIMINARY
3.3V LVDS DRIVER TERMINATION
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the unused outputs.
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS854S202I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S202I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
DD
•
Power (core) = V
* I
= 3.465V * 115mA = 398.48mW
DD_MAX
MAX
DD_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 60.4°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.399W * 60.4°C/W = 109.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 48-LEAD LQFP, FORCED CONVECTION
JA
θ vs. Air Flow (Linear Feet per Minute)
JA
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70.2°C/W
60.4°C/W
56.9°C/W
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RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 48 LEAD LQFP
JA
θ vs. Air Flow (Linear Feet per Minute)
JA
0
200
60.4°C/W
500
56.9°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
70.2°C/W
TRANSISTOR COUNT
The transistor count for ICS854S202I is: 8,485
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PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS854S202AYI
Marking
Package
Shipping Packaging
tray
Temperature
ICS854S202AI
ICS854S202AI
ICS54S202AIL
ICS54S202AIL
48 Lead LQFP
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS854S202AYIT
ICS854S202AYILF
ICS854S202AYILFT
48 Lead LQFP
1000 tape & reel
tray
48 Lead "Lead-Free" LQFP
48 Lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
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Singapore (1997) Pte. Ltd.
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Europe
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United States
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+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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