854S057B_16 [IDT]
4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination;
| 型号： | 854S057B_16 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination |
| 文件： | 总15页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4:1 or 2:1 LVDS Clock Multiplexer with
Internal Input Termination
854S057B
Datasheet
General Description
Features
The 854S057B is a 4:1 or 2:1 LVDS Clock Multiplexer which can
operate up to 2GHz. The PCLK, nPCLK pairs can accept most
standard differential input levels. Internal termination is provided on
each differential input pair. The 854S057B operates using a 2.5V
supply voltage. The fully differential architecture and low propagation
delay make it ideal for use in high speed multiplexing applications.
The select pins have internal pulldown resistors. Leaving one input
unconnected (pulled to logic low by the internal resistor) will
transform the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins will
select the same numbered data input (i.e., 00 selects PCLK0,
nPCLK0).
• High speed differential multiplexer. The device can be configured
as either a 4:1 or 2:1 multiplexer
• One LVDS output pair
• Four selectable PCLK, nPCLK inputs with internal termination
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >2GHz
• Part-to-part skew: 200ps (maximum)
• Propagation delay: 800ps (maximum)
• Additive phase jitter, RMS: 0.065ps (typical)
• Full 2.5V power supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
VT0
V
DD
1
2
20
19
VDD
PCLK3
PCLK0
VT0
50
50
3
4
18 VT3
17 nPCLK3
nPCLK0
PCLK0
nPCLK0
SEL1
SEL0
PCLK1
5
6
7
16
15
14
Q
nQ
PCLK2
VT1
VT1
nPCLK1
GND
8
13 VT2
50
50
9
10
12 nPCLK2
PCLK1
nPCLK1
11
GND
0 0
0 1
1 0
1 1
854S057B
VT2
Q
nQ
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm package body
G Package
50
50
50
PCLK2
nPCLK2
Top View
VT3
50
PCLK3
nPCLK3
Pulldown
Pulldown
SEL1
SEL0
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854S057B Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
VDD
Type
Description
1, 20
2
Power
Input
Input
Input
Input
Input
Input
Input
Power
Input
Input
Input
Output
Input
Input
Input
Power supply pins.
PCLK0
VT0
Non-inverting LVPECL differential clock input. RT = 50 termination to VT0.
Termination input. For LVDS input, leave floating. RT = 50 termination to VT0.
Inverting LVPECL differential clock input. RT = 50 termination to VT0.
3
4
nPCLK0
SEL1, SEL0
PCLK1
VT1
5, 6
7
Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.
Non-inverting LVPECL differential clock input. RT = 50 termination to VT1.
Termination input. For LVDS input, leave floating. RT = 50 termination to VT1.
Inverting LVPECL differential clock input. RT = 50 termination to VT1.
Power supply ground.
8
9
nPCLK1
GND
10, 11
12
nPCLK2
VT2
Inverting LVPECL differential clock input. RT = 50 termination to VT2.
Termination input. For LVDS input, leave floating. RT = 50 termination to VT2.
Non-inverting LVPECL differential clock input. RT = 50 termination to VT2.
Differential output pair. LVDS interface levels.
13
14
PCLK2
nQ, Q
15, 16
17
nPCLK3
VT3
Inverting LVPECL differential clock input. RT = 50 termination to VT3.
Termination input. For LVDS input, leave floating. RT = 50 termination to VT3.
Non-inverting LVPECL differential clock input. RT = 50 termination to VT3.
18
19
PCLK3
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
2
RPULLDOWN Input Pulldown Resistor
RT Input Termination Resistor
50
50
k
40
60
Function Table
Table 3. Control Input Function Table
Inputs
Outputs
SEL1
SEL0
PCLKx, nPCLKx
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK2, nPCLK2
PCLK3, nPCLK3
0
0
1
1
0
1
0
1
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854S057B Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Input Current, PCLK, nPCLK
VT Current, IVT
50mA
100mA
Package Thermal Impedance, JA
Storage Temperature, TSTG
92.1°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
Maximum
2.625
50
Units
V
Power Supply Voltage
Power Supply Current
2.375
2.5
IDD
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VDD = 2.5V
Minimum
1.7
Typical
Maximum
VDD + 0.3
0.7
Units
V
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VDD = 2.5V
-0.3
V
SEL0, SEL1
SEL0, SEL1
VDD = VIN = 2.625V
VDD = 2.625V, VIN = 0V
150
µA
µA
IIL
-10
Table 4C. LVPECL Differential DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
35
Units
mA
V
IIN
Absolute Input Current; NOTE 1
VDD = VIN = 2.625V
VPP
VCMR
Peak-to-Peak Voltage; NOTE 2
0.15
1.2
Common Mode Input Voltage; NOTE 2, 3
GND + 1.2
VDD
V
NOTE 1: Guaranteed by design.
NOTE 2: VIL should not be less than -0.3V.
NOTE 3: Common mode input voltage is defined as VIH.
©2016 Integrated Device Technology, Inc.
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854S057B Datasheet
Table 4D. LVDS DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
325
4
Maximum
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
225
425
35
VOD
VOS
1.125
1.25
5
1.375
25
VOS
VOS Magnitude Change
mV
Table 5. AC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
GHz
ps
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Input Skew
>2
tPD
300
800
200
40
tsk(pp)
tsk(i)
ps
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
622.08MHz, Integration Range:
12kHz – 20MHz
tjit
0.065
ps
tR / tF
Output Rise/Fall Time
20% to 80%
700MHz
ƒ 1.1GHz
ƒ 2GHz
50
49
47
43
250
51
ps
%
odc
Output Duty Cycle
53
%
57
%
MUXISOLATION MUX Isolation
ƒ= 500MHz
-65
dBm
NOTE: All parameters measured at ƒ 1.9GHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between different devices operating at the same supply voltage, same frequency and with equal load conditions.
Using the same type of inputs on each device, the output is measured at the differential cross point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc.
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Revision B, February 10, 2016
854S057B Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "Rohde & Schwarz SMA100A Low Noise
Signal Generator as external input to an Agilent 8133A 3GHz Pulse
Generator".
©2016 Integrated Device Technology, Inc.
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854S057B Datasheet
Parameter Measurement Information
V
DD
SCOPE
nPCLK[0:3]
PCLK[0:3]
GND
Q
V
DD
2.5V 5%
POWER SUPPLY
VPP
VCMR
Cross Points
+
Float GND –
nQ
LVDS Output Load AC Test Circuit
Differential Input Level
Spectrum of Output Signal Q
MUX selects active
input clock signal
Part 1
nQ
A0
Q
MUX_ISOL = A0 – A1
Part 2
nQ
MUX selects static input
Q
A1
tsk(pp)
ƒ
Frequency
(fundamental)
MUX Isolation
Part-to-Part Skew
nPCLKx
PCLKx
nPCLKy
PCLKy
nQ
nPCLK[0:3]
PCLK[0:3]
nQ
Q
tPD
Q
tPD2
tPD1
tsk(i)
tsk(i) = |tPD1 - tPD2
|
Input Skew
Propagation Delay
©2016 Integrated Device Technology, Inc.
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854S057B Datasheet
Parameter Measurement Information, continued
nQ
Q
nQ
80%
tF
80%
tR
VOD
20%
20%
Q
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
Differential Output Voltage Setup
Offset Voltage Setup
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854S057B Datasheet
Application Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
2.5V Differential Input with Built-In 50 Termination Unused Input Handling
To prevent oscillation and to reduce noise, it is recommended to have
pullup and pulldown connect to true and compliment of the unused
2.5V
input as shown in Figure 1.
2.5V
R1
680
PCLK
VT
nPCLK
Receiver
With
Built-In
R2
50Ω
680
Figure 1. Unused Input Handling
©2016 Integrated Device Technology, Inc.
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854S057B Datasheet
2.5V LVPECL Input with Built-In 50 Termination Interface
The PCLK /nPCLK with built-in 50 terminations accept LVDS,
LVPECL, CML, SSTL and other differential signals. Both differential
signals must meet the VPP and VCMR input requirements. Figures 2A
to 2E show interface examples for the PCLK /nPCLK with built-in 50
termination input driven by the most common driver types. The input
interfaces suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
2.5V
2.5V
3.3V or 2.5V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
VT
VT
nPCLK
nPCLK
Receiver
With
Receiver
With
LVPECL
LVDS
R1
18Ω
Built-In
50Ω
Built-In
50Ω
Figure 2A. PCLK/nPCLK Input with
Figure 2B. PCLK/nPCLK Input with
Built-In 50 Driven by an LVDS Driver
Built-In 50 Driven by an LVPECL Driver
2.5V
2.5V
2.5V
2.5V
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
VT
VT
Zo = 50Ω
Zo = 50Ω
nPCLK
nPCLK
Receiver
Receiver
With
With
CML - Built-in 50Ω Pull-up
CML
Built-In
50Ω
Built-In
50Ω
Figure 2C. PCLK/nPCLK Input with
Built-In 50 Driven by a CML Driver
Figure 2D. PCLK/nPCLK Input with Built-In 50 Driven
by a CML Driver with Built-In 50 Pullup
2.5V
2.5V
Zo = 50Ω
Zo = 50Ω
R1
R2
25Ω
25Ω
PCLK
VT
nPCLK
Receiver
With
SSTL
Built-In
50Ω
Figure 2E. PCLK/nPCLK Input with
Built-In 50 Driven by an SSTL Driver
©2016 Integrated Device Technology, Inc.
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854S057B Datasheet
LVDS Driver Termination
A general LVDS interface is shown in Figure 3. Standard termination
for LVDS type output structure requires both a 100 parallel resistor
at the receiver and a 100 differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 3 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the input receivers amplitude and
common mode input range should be verified for compatibility with
the output.
+
LVDS
Receiver
–
LVDS Driver
100Ω
100Ω Differential Transmission Line
Figure 3. Typical LVDS Driver Termination
Schematic Example
Figure 4 shows a schematic example of the 854S057B. In this
example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are used.
The decoupling capacitors should be physically located near the
power pin.
VDD
VDD
VDD
LVDS
VDD
VDD
U1
R1
680
R3
680
R1
1K
Zo = 50
Zo = 50
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
VDD
PCLK3
VT3
nPCLK3
+
-
Zo = 50
Zo = 50
Q
nQ
PCLK2
VT2
nPCLK2
GND
R5
100
VDD
10
LVDS
Zo = 50
Zo = 50
R2
680
R4
680
R1
1K
R6
18
VDD
(U1,1)
(U1,20)
C2
LVPECL
C1
0.1u
0.1u
VDD=2.5V
Figure 4. 854S057B LVDS Schematic Example
©2016 Integrated Device Technology, Inc.
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Revision B, February 10, 2016
854S057B Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 854S057B.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 854S057B is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 50mA = 131.25mW
Power Dissipation for internal termination RT
Power (RT)MAX = 4 * (VPP_MAX)2 / RT_MIN = (1.2V)2 / 80 = 72mW
Total Power_MAX = 131.25mW + 72mW = 203.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 92.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.203W * 92.1°C/W = 103.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92.1°C/W
86.5°C/W
83.0°C/W
©2016 Integrated Device Technology, Inc.
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854S057B Datasheet
Reliability Information
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92.1°C/W
86.5°C/W
83.0°C/W
Transistor Count
The transistor count for 854S057B is: 375
This device is pin and function compatible and a suggested replacement for 854057.
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
©2016 Integrated Device Technology, Inc.
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Revision B, February 10, 2016
854S057B Datasheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Tube
Temperature
-40C to 85C
-40C to 85C
854S057BGILF
854S057BGILFT
ICS54S057BIL
ICS54S057BIL
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
©2016 Integrated Device Technology, Inc.
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Revision B, February 10, 2016
854S057B Datasheet
Revision History Sheet
Rev
Table
Page
Description of Change
Date
10
11
Updated LVDS Output Termination application note.
Updated Power Dissipation calculation in Power Considerations Application Note.
A
3/26/10
A
11
Corrected Power Dissipation calculation in the Power Considerations Application Note.
3/29/10
2/10/16
1
General Description - deleted HiperClocks logo.
B
T9
13
Ordering Information Table - deleted count for Tape & Reel.
Deleted "ICS" prefix and "I" suffix in the part number throughout the datasheet.
©2016 Integrated Device Technology, Inc.
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Revision B, February 10, 2016
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
Sales
Tech Support
email: clocks@idt.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
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While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as
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Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.
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