854S01AKILFT [IDT]
2:1 Differential-to-LVDS Multiplexer;
| 型号： | 854S01AKILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2:1 Differential-to-LVDS Multiplexer 逻辑集成电路 |
| 文件： | 总17页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2:1 Differential-to-LVDS Multiplexer
ICS854S01I
DATASHEET
General Description
Features
The ICS854S01I is a high performance 2:1 Differential-to-LVDS
Multiplexer. The ICS854S01I can also perform differential translation
because the differential inputs accept LVPECL, LVDS or CML levels.
The ICS854S01I is packaged in a small 3mm x 3mm 16 VFQFN
package, making it ideal for use on space constrained boards.
• 2:1 LVDS MUX
• One LVDS output pair
• Two differential clock inputs can accept: LVPECL, LVDS, CML
• Maximum input/output frequency: 2.5GHz
• Translates LVCMOS/LVTTL input signals to LVDS levels by using
a resistor bias network on nPCLK0, nPCLK1
• RMS additive phase jitter: 0.06ps (typical)
• Propagation delay: 600ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Pin Assignment
Block Diagram
Pulldown
PCLK0
0
Pullup/Pulldown
nPCLK0
Q
nQ
16 15 14 13
1
2
3
PCLK0
nPCLK0
PCLK1
12
11
10
GND
Q
Pulldown
PCLK1
nPCLK1
Pullup/Pulldown
1
nQ
nPCLK1
4
GND
9
Pulldown
5
6
7
8
CLK_SEL
ICS854S01I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS854S01AKI June 15, 2017
1
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
PCLK0
Input
Input
Input
Input
Pulldown
Non-inverting differential clock input.
Pullup/
Pulldown
2
3
4
nPCLK0
PCLK1
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Pulldown
Pullup/
Pulldown
nPCLK1
Inverting differential clock input. VDD/2 default when left floating.
5
6
RESERVED
CLK_SEL
Reserve
Input
Reserve pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When
LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels.
Pulldown
7, 16
8, 13
nc
Unused
Power
Power
Output
No connects.
VDD
Power supply pins.
9, 12, 14, 15
10, 11
GND
nQ, Q
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
2
RPULLUP
RPULLDOWN
37
37
k
k
Function Tables
Table 3. Control Input Function Table
CLK_SEL
PCLK Selected
PCLK0, nPCLK0
PCLK1, nPCLK1
0
1
ICS854S01AKI June 15, 2017
2
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
74.7C/W (0 mps)
-65C to 150C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
VDD Power Supply Voltage
IDD Power Supply Current
Test Conditions
Minimum
Typical
Maximum
3.465
40
Units
V
3.135
3.3
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.2
Typical
Maximum
VDD + 0.3
0.8
Units
V
VIH
VIL
IIH
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
-0.3
V
CLK_SEL
CLK_SEL
VDD = VIN = 3.465V
150
μA
μA
IIL
VDD = 3.465V, VIN = 0V
-10
Table 4C. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Input High
Current
PCLK0, nPCLK0,
PCLK1, nPCLK1
IIH
VDD = VIN = 3.465V
150
μA
PCLK0, PCLK1
V
DD = 3.465V, VIN = 0V
-10
-150
0.15
μA
μA
V
Input Low
Current
IIL
nPCLK0, nPCLK1
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Voltage; NOTE 1
1.2
Common Mode Input Voltage;
NOTE 1, 2
VCMR
1.2
VDD
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
ICS854S01AKI June 15, 2017
3
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
454
Units
mV
mV
V
VOD
Differential Output Voltage
247
VOD
VOS
VOD Magnitude Change
Offset Voltage
50
1.125
1.375
50
VOS
VOS Magnitude Change
mV
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
2.5
GHz
Propagation Delay;
NOTE 1
tPD
250
400
600
ps
ps
ps
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
155.52MHz, Integration Range:
12kHz – 20MHz)
tjit
0.06
Part-to-Part Skew;
NOTE 2, 3
tsk(pp)
350
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
49
275
51
ps
%
MUX Isolation;
NOTE 4
fOUT = 155.52MHz, VPP
400mV
=
MUX_ISOLATION
86
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: All parameters measured at 1.0GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Q, nQ outputs measured differentially. See Parameter Measurement Information to MUX Isolation diagram.
ICS854S01AKI June 15, 2017
4
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.06ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator”
ICS854S01AKI June 15, 2017
5
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Parameter Measurement Information
V
DD
SCOPE
Q
nPCLK[0:1]
PCLK[0:1]
V
3.3V±5%
DD
POWER SUPPLY
VPP
VCMR
Cross Points
+
Float GND –
nQ
GND
LVDS Output Load AC Test Circuit
Differential Input Level
Spectrum of Output Signal Q
MUX selects active
input clock signal
A0
A1
Part 1
nQx
MUX_ISOL = A0 – A1
Qx
Part 2
nQy
MUX selects static input
Qy
tsk(pp)
ƒ
Frequency
(fundamental)
Part-to-Part Skew
MUX Isolation
nPCLK[0:1]
PCLK[0:1
nQ
80%
80%
VOD
20%
nQ
Q
20%
Q
tF
tR
tPD
Output Rise/Fall Time
Propagation Delay
ICS854S01AKI June 15, 2017
6
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Parameter Measurement Information, continued
nQ
Q
Output Duty Cycle/Pulse Width/Period
Differential Output Voltage Setup
Offset Voltage Setup
ICS854S01AKI June 15, 2017
7
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
PCLKx
V_REF
nPCLKx
C1
0.1uF
R2
1K
Figure 1. Single-Ended Signal Driving Differential Input
Recommendations for Unused Input Pins
Inputs:
PCLK/nPCLK Inputs:
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from PCLK to
ground.
ICS854S01AKI June 15, 2017
8
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS and other differential
signals. Both signals must meet the VPP and VCMR input
requirements. Figures 2A to 2C show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
3.3V
3.3V
R3
R4
125Ω
125Ω
Zo = 50Ω
Zo = 50Ω
PCLK
nPCLK
LVPECL
Input
LVPECL
R1
R2
84Ω
84Ω
Figure 2A. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
Figure 2B. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
R1
100Ω
nPCLK
LVPECL
Input
LVPECL
nPCLK
Zo = 50Ω
R1
84Ω
R2
84Ω
LVPECL
CML Built-In Pullup
Input
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
3.3V
3.3V
R1
R2
50Ω
50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
nPCLK
LVPECL
Input
CML
Figure 2E. PCLK/nPCLK Input Driven by a CML Driver
ICS854S01AKI June 15, 2017
9
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Application Schematic Example
Figure 3 shows an example of ICS854S01I application schematic.
This device can accept different types of input signal. In this example,
the input is driven by a LVDS driver. The decoupling capacitor should
be located as close as possible to the power pin.
Note: Thermal pad (E-pad) must be connected to ground (GND).
Figure 3. ICS854S01I Application Schematic Example
ICS854S01AKI June 15, 2017
10
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS854S01AKI June 15, 2017
11
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 5 In a 100 differential
transmission line environment, LVDS drivers require a matched load
termination of 100 across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 5. Typical LVDS Driver Termination
ICS854S01AKI June 15, 2017
12
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S01I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for theICS854S01I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 40mA = 138.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.139W * 74.7°C/W = 95.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 16 Lead VFQFN, Forced Convection
JA by Velocity
0
Meters per Second
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
ICS854S01AKI June 15, 2017
13
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Reliability Information
Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN
JA by Velocity
0
Meters per Second
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
Transistor Count
The transistor count for ICS854S01I is: 257
This is a suggested replacement for ICS85401
ICS854S01AKI June 15, 2017
14
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Package Drawings – Sheet 1
ICS854S01AKI June 15, 2017
15
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Package Drawings – Sheet 2
ICS854S01AKI June 15, 2017
16
©2017 Integrated Device Technology, Inc.
ICS854S01I Datasheet
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Ordering Information
Table 9. Ordering Information
Part/Order Number
854S01AKILF
854S01AKILFT
Marking
4S1A
4S1A
Package
“Lead-Free” 16 Lead VFQFN
“Lead-Free” 16 Lead VFQFN
Shipping Packaging
Temperature
-40C to 85C
-40C to 85C
Tube
Tape & Reel
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Revision History
Date
Description of Change
6/15/2017
11/2/2012
Updated the package drawings
Added Note: Thermal pad (E-pad) must be connected to ground (GND).
Deleted HiperClockS Logo. Updated GD paragraph to include CML.
Added CML to 3rd bullet.
10/29/2012
Added figures 2D and 2E.
Deleted quantity from tape and reel.
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
相关型号：
854S14AKI
Low Skew Clock Driver, 854S Series, 4 True Output(s), 0 Inverted Output(s), 4 X 4 MM, 0.95 MM HEIGHT, MO-220, VQFN-24
IDT
854S14AKILFT
Low Skew Clock Driver, 854S Series, 4 True Output(s), 0 Inverted Output(s), 4 X 4 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VQFN-24
IDT
854S14AKT
Low Skew Clock Driver, 854S Series, 4 True Output(s), 0 Inverted Output(s), 4 X 4 MM, 0.95 MM HEIGHT, MO-220, VQFN-24
IDT
854S202AYIFT
Low Skew Clock Driver, 854S Series, 4 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BBC-HD, LQFP-48
IDT
©2020 ICPDF网 联系我们和版权申明